From nobody Sun May 10 12:55:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70789C433F5 for ; Tue, 3 May 2022 19:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242065AbiECTqJ (ORCPT ); Tue, 3 May 2022 15:46:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242013AbiECTp6 (ORCPT ); Tue, 3 May 2022 15:45:58 -0400 Received: from JPN01-OS0-obe.outbound.protection.outlook.com (mail-os0jpn01on2110.outbound.protection.outlook.com [40.107.113.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75BC43525F; Tue, 3 May 2022 12:42:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dzoEpypc7GFDigDbkr+ifwr1/4PUwrerfSPB+etJXcrQ5iIKwprvxRQLNTfwYYQ9utQvGr8hyk1hvkQYik4lykvSUkgCk3ceZAqn9/ZEArZoz8nCca5wzET4Ie+rMjZ+e+xJrvMbp0Eb2OGtyEoMZANO/o1RO0LUsZwfdxR9gh/9aH6DbJXcTGr8Hf2SKkP8VB8heJFlsvUUqQj+ciBT9pmnJ7Nj7lpckXnGCwxzZZTQjQCq4Gp4Ieywchmc+otPYvnnMtESOkq23f9MRznsw7CrzPCpFwFCEmL0CDQMySZ4fS+k61DeM/T23tbnIb3YcFP27hQI0eZ5epMT8LM19Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=x8vtGgRLuv3nRyP88JXO6ZK6yZKrqIXDuyBIUjFkNfA=; b=PAg1Rx9lDhKQ64c7sdJvhbhnldaqyHC0D1LBihb2lI524+mCI6eAO67OPW1ulbVnjgbQzs2hBJWYMkjxW0Xiz/rgtxbaUgJJa9rNOPnWp4zAZ1zYfrrSrss5L4OzWeqNfo0dFYFHZp6XipWqw7ko5v/7+KAsjG56M0LGJNwLDHhTt5fpLGgR35LsHvzX2LisTolQixZ9piKvazd6wte2oUGaiSK4J0D8X+HSfcDkXX05TUA/Mu7FjOM4AFjmWrRTOrNMlL/ElMUmWVEMWIrzvco/+of8K0uegdknVQxBG+qWGA/LSwG+EXmfP0b6HSCKGMfybAKtQRGzL5wK0v2Puw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=renesas.com; dmarc=pass action=none header.from=renesas.com; dkim=pass header.d=renesas.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=renesas.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x8vtGgRLuv3nRyP88JXO6ZK6yZKrqIXDuyBIUjFkNfA=; b=Gg9ypdHkgBXvwka89rcQP52ni31O61f8DrQzZy0jbsi6o/usuuDAoN72AcGWQwAmMVs7ibzZ2TXW8vsFlQUIKXvyEwh4dGUTjeMCgMIe5RYnnGDeqLcQwXySkDrl81NF1gcKt/IyfGaA8206TW71lzf1xaVwwt6SfX4bgCsP7Os= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=renesas.com; Received: from OSAPR01MB3892.jpnprd01.prod.outlook.com (2603:1096:604:5b::23) by OS3PR01MB8115.jpnprd01.prod.outlook.com (2603:1096:604:171::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5206.13; Tue, 3 May 2022 19:42:22 +0000 Received: from OSAPR01MB3892.jpnprd01.prod.outlook.com ([fe80::fdcb:b853:c0a7:8d58]) by OSAPR01MB3892.jpnprd01.prod.outlook.com ([fe80::fdcb:b853:c0a7:8d58%4]) with mapi id 15.20.5206.024; Tue, 3 May 2022 19:42:22 +0000 From: Alex Helms To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, alexander.helms.jy@renesas.com, michal.simek@xilinx.com Subject: [PATCH 1/2] dt-bindings: Renesas versaclock7 device tree bindings Date: Tue, 3 May 2022 12:42:00 -0700 Message-Id: <20220503194201.25714-2-alexander.helms.jy@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503194201.25714-1-alexander.helms.jy@renesas.com> References: <20220503194201.25714-1-alexander.helms.jy@renesas.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0374.namprd03.prod.outlook.com (2603:10b6:a03:3a1::19) To OSAPR01MB3892.jpnprd01.prod.outlook.com (2603:1096:604:5b::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6d9f7799-c08d-48ad-103a-08da2d3d0ac0 X-MS-TrafficTypeDiagnostic: OS3PR01MB8115:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +lLBGVofe6qH8PB69nLfthm0Z7LDHsYFcjJVa692ZftS1bTAt2yJBR8D/UhyzIC61quIvFtz0DbG4uegAivarsRYO/CMzknfKuCsTnalBwengmQBWU7ZARxb4ptPrre9uKHPFS3K32VB+FuAkPKf5p87EdZGM+b2XwQTh1WqkBEyppiEMuL9SN3zU/e/u85U8qeS44LJFOJtCsRFHeN2+eqJ3EYEndCd9OirNXV+0Cq3vCq5QrRCY0yIMnZW93+VFUQUwfwVlENpCNBCYH2ERgDF1O9lQ76a+DyEvT7D0s7i5RiiMva3e1BVeDWmU9zlRcUL9mD4FUi4xy2uIDTNqWCubjGfPIhoQRAXduaiQM0URuk8/dHRSPaFitRe7CXHCc2BY8MmQxv8uIGktMjDKqsHFABIJQQPlRILDgRZms9RNmlLokR16yy4nTkDybGMDB1RjbPM2vih+RpYKqljDxDKSTwxTxCbSVo7ZUSf1y57f9fnQSqEG3/sIwoEmexF+JWcQoLl38SfvAtdU7C+Eg16a6RCcTM+sADCnFplg/BK2JPIRgpCThGflZ24pKxJkCOPH/qNH2seFR+oyetn0FBSyRASj1gqktMqD8tmK4XgLKyGmyMpGts0ZfDmurM9qx7oUsWEEW6NwOvS21qj7ifSnK5irBRK3wqpfI1dItfrKCiL7FxKbyZkRQ7PLAMmD7d32zvrquslemnnN/4knPIj6CvKaRrP83p1cxNsikCiYpk6qyNVFu0hKgJM6AWAjNHOi01+fggf+sngVTQBmXMrKY/KnTdbq9D1baZ+RqgjUC1Io9WdNUHvrGGuHQrh2F3IgH3B/CDzAvlHvAOpvg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OSAPR01MB3892.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(186003)(36756003)(2906002)(316002)(6506007)(6666004)(1076003)(86362001)(52116002)(38100700002)(38350700002)(8936002)(103116003)(83380400001)(508600001)(5660300002)(66946007)(66556008)(66476007)(966005)(8676002)(2616005)(4326008)(6486002)(6512007)(26005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?NZidBU9tWHC27ARUzGKdyT+KPrqfkwfLhOI1CLH6+DaSoJoK2ryHfYxk2DVD?= =?us-ascii?Q?k/m9n29BGopqXNEGZFVoCb2XNA7OdHzncnRzi29X0eV3n5YSbGJSOinvcQga?= =?us-ascii?Q?Llu/zFg8LfCMJyqpsBZe3cnhvRe6AQlFuKQYGxyuhIf3mXmJ0V7YG7DStQMK?= =?us-ascii?Q?pzDwX2rl5uEPafjq4tmLEWlUmJbM4aUaxlVOSq8AnSAT949CxG4PO3IcbUKV?= =?us-ascii?Q?vqRloul6ik24X7OcXvOha8a00bOssJo+oLrTZETkw5Xd3E2qEalgCcUJmC23?= =?us-ascii?Q?SLqxoaFI9nOgCAby0MJR9bFbB9zYB6f/SJAhFXUhR5edVoS+/5RmVMCCcd1R?= =?us-ascii?Q?Rb5B9Whd4S4fpiQmTzqEwZV7IM59r6kiii80uDMLjRTLdFhQl/z7+Tza0aaj?= =?us-ascii?Q?n3YrWpd48ngJ62oM1L/e8vG6AG/dG0tDALEvtmgQD7d672pwCH2tXKaHS4AY?= =?us-ascii?Q?i6lJ6aznSkEXI4y/8qxpi7IaltQI+TxQafUqK+XL6fraFm4UoLJLgSXhwioS?= =?us-ascii?Q?n+w+UyMR1mi108vfneq3vZN5ZUsxpI2bqBd2OOD+EPACvSbVI8pqbJCe5CWA?= =?us-ascii?Q?4dqNjkDuUuLdUc/iTQPM2SoIkBz4lQ9cqPuAkhfvlA7U9CKawfRQNGbq2we2?= =?us-ascii?Q?DrKeicBJmkU5mWB2TcjOrDZkiM66UywKC5zsbjaLo4trSo9wg7Hoa440YLql?= =?us-ascii?Q?TZTN/lddCBuzxkCvvfwft0lKjzxfnhi1+DDdcE6WL3d+HT5tfmNJivmYhBlv?= =?us-ascii?Q?Y+WFn5N0tBE1t8K0Iah3p00ZH/5CstdQ2LpfAbtLNvoLUjf9AhLVEla4gaoz?= =?us-ascii?Q?QU3YNoRv7Zuz54yu8hq2wbe22L4fwcUplqWPfnfA5U8/eO62Wh83cqdVJHfb?= =?us-ascii?Q?xn3OxeVo+7bnTobBxIqI6Iliw7xdvT7SsmP7aUntSC3AnAwJPbyi+gxf4tA6?= =?us-ascii?Q?9+m0v74eeFSzuqnfWiQJOQZM3aiPV8RPKyBfJ70QSmAU5k7bHUW5BFyX9/O8?= =?us-ascii?Q?O3iAGPfr6IwN+xcCid95m8NBEBk0tQXPSfQl9WvWElL0JpvGBsoMf4IGUfSt?= =?us-ascii?Q?eSfQemmbOU3R2LE4Xx6JqmKknISZDufnTQvQPGEvO4xXBeGGXwoUoHk3heam?= =?us-ascii?Q?2GWIwTCHYmYPLU+aIcgHpYkl17Lrr/wwZbTDQRoCaacL87l1mrr0jvZxpy2X?= =?us-ascii?Q?yX+bvSRaIxJUOsWS8aWOj8wg1BGoFPd7GZAC8vB/ry0JyLON7ISUWmyqzQLj?= =?us-ascii?Q?qTWa4PR8Jk84brx9HZNUpt5T+GmcuMzKoMibjqGaqS2sHMsh9P2kzPK1qIjw?= =?us-ascii?Q?bBV5yP4iajbGE8Ck3vhU0uxPSQENuGrSK2xW5sZecGSRuUeZYXGOgWz06A01?= =?us-ascii?Q?e88z5yCR8L1S7xRKBKmeoOJokDyvBSRnzat6abu0fd0/rxBM//lIuO1QHkl+?= =?us-ascii?Q?iQybbWZv0ce3omvddgU0I80b0rSlI0bgzy7QJaKRUAX1ndDK356+o60hdywQ?= =?us-ascii?Q?zLSjaGljSfvi4DWyBamCblbhT6ocX4709w8PNcHY9/j7tkmMrH1fM/v2acbr?= =?us-ascii?Q?S8cTDZxP8y9n/Y/SJrptxPf/0fyOm2vbO1xa3P4CeomrXKbZMimuAiPV9m5O?= =?us-ascii?Q?5mJ6Xu/JWnu3wpHYg+cLUjmzL6FnvzRtCyyJtBEOAnXs77X86NO3O0DkjPel?= =?us-ascii?Q?rKiPvA9VSvi41Wf6GYQRRi1p/spxMI+jeEd/4bVxFY6aN9yL0ZzD+RrMe2em?= =?us-ascii?Q?+/1xK5o2TZtZ+0eDmbYUiutdNVNl4/m7eoy0lIrZ1Hq+53jkZ5Fp?= X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d9f7799-c08d-48ad-103a-08da2d3d0ac0 X-MS-Exchange-CrossTenant-AuthSource: OSAPR01MB3892.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2022 19:42:22.3741 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VdmNOG2cuhcr330Mq8wxhqhgUD6e8Izlp887E62QEXHm1Tbx6ug7xZlNUwzKjIRhbB4gu1mHvECGp7bvGWVU+sIVbYnOr4thcOwPFvGwKuA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS3PR01MB8115 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms Reviewed-by: Rob Herring --- .../bindings/clock/renesas,versaclock7.yaml | 64 +++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,versacl= ock7.yaml diff --git a/Documentation/devicetree/bindings/clock/renesas,versaclock7.ya= ml b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml new file mode 100644 index 000000000..cc099d9e1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Versaclock7 Programmable Clock Device Tree Bindings + +maintainers: + - Alex Helms + +description: | + Renesas Versaclock7 is a family of configurable clock generator and + jitter attenuator ICs with fractional and integer dividers. + +properties: + '#clock-cells': + const: 1 + + compatible: + enum: + - renesas,rc21008a + + reg: + maxItems: 1 + + clocks: + items: + - description: External crystal or oscillator + + clock-names: + items: + - const: xin + +required: + - '#clock-cells' + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vc7_xin: vc7_xin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <49152000>; + }; + + i2c@0 { + reg =3D <0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + vc7: vc7@9 { + compatible =3D "renesas,rc21008a"; + reg =3D <0x9>; + #clock-cells =3D <1>; + clocks =3D <&vc7_xin>; + clock-names =3D "xin"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index cd0f68d4a..8a23ea619 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16536,6 +16536,11 @@ S: Maintained F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml F: drivers/mtd/nand/raw/renesas-nand-controller.c =20 +RENESAS VERSACLOCK 7 CLOCK DRIVER +M: Alex Helms +S: Maintained +F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained base-commit: f443e374ae131c168a065ea1748feac6b2e76613 --=20 2.30.2 From nobody Sun May 10 12:55:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F1CC433EF for ; Tue, 3 May 2022 19:42:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242049AbiECTqN (ORCPT ); Tue, 3 May 2022 15:46:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242036AbiECTqC (ORCPT ); Tue, 3 May 2022 15:46:02 -0400 Received: from JPN01-OS0-obe.outbound.protection.outlook.com (mail-os0jpn01on2110.outbound.protection.outlook.com [40.107.113.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C17022B22; Tue, 3 May 2022 12:42:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OdYxe1UAdINaB04RbeGLDoPCs3at/XyqF0hsbh+TYzB4zgrPresyqyzF/zguFwtwhAuNb8Sjavx1lP92HJ3WP1Ga9BaDxT2droH6kWpCbUN63K50xOJuXZXZtPdMmQvm8mKnIkgxSyooKr3Ugj3zvOy4pGM0Mju8eWKXWM8qgp98P7iV5wxmUmgdGfa+UveWCN9bB/xffS+oJcgtba3vesQQPiFvgEPqmNobYItXqSol85upGByE6GOKIJvkgHA1RLKDSEmr7WE1IF92gRmDV5N8o9qQcHhl7KraB8faFFNNFJqLwbZGVKUGeyHYtpEyzNctE4HEf31PZifTUQU1BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+4WF/Oxdq0B2fu1+ifxNszP/KU/VH5+AXta9BxXCRts=; b=V6M9H3NabY14vMem8vHDKzALxjSj+5JR7hq3NomFvcGnQgxn9FnpXKy4o8PRqVjuf/Ahs7qcRDyoW5cKQaKgJimSMZKJ5JEZqWkqNxhItJ+6g6/z3NkPJj6+wJdv1PrG1pnbh26NrVmu9IbzZkAS74g6t+PquAxSWp1hXJBj2b/hTve5HlXKfbcx+KLBxnYSbhEsc4peDLOraMrjyYfQvKYzmI9+elm33iL1s0Iga9sKFFP4APYZV6s3OXLXIUZZYnALQqt8/cAta02GwPVjRXxzRgQyD3866Xbl+7ir/i8vyWhrCgfiCmNgpTnenzCsiZlxk1thvPYEikgI68hRTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=renesas.com; dmarc=pass action=none header.from=renesas.com; dkim=pass header.d=renesas.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=renesas.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+4WF/Oxdq0B2fu1+ifxNszP/KU/VH5+AXta9BxXCRts=; b=ScVY4yE2Ik/p0i2+TwHB1Q37vIEd6ZmYnmsLbw0C1X8iW2P7Ki8ykDkKum4G7JYq39DDxVitrCVVfcI23u3q0JTJ5zTyryhVZc1Y01a7XiGPIJ+09bjlkeraUEbJrksWbwXdq8L4eO5IGDw+BhY7RfnxTzhducwzHWHoirWhstk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=renesas.com; Received: from OSAPR01MB3892.jpnprd01.prod.outlook.com (2603:1096:604:5b::23) by OS3PR01MB8115.jpnprd01.prod.outlook.com (2603:1096:604:171::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5206.13; Tue, 3 May 2022 19:42:24 +0000 Received: from OSAPR01MB3892.jpnprd01.prod.outlook.com ([fe80::fdcb:b853:c0a7:8d58]) by OSAPR01MB3892.jpnprd01.prod.outlook.com ([fe80::fdcb:b853:c0a7:8d58%4]) with mapi id 15.20.5206.024; Tue, 3 May 2022 19:42:24 +0000 From: Alex Helms To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, alexander.helms.jy@renesas.com, michal.simek@xilinx.com Subject: [PATCH 2/2] clk: Renesas versaclock7 ccf device driver Date: Tue, 3 May 2022 12:42:01 -0700 Message-Id: <20220503194201.25714-3-alexander.helms.jy@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503194201.25714-1-alexander.helms.jy@renesas.com> References: <20220503194201.25714-1-alexander.helms.jy@renesas.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0374.namprd03.prod.outlook.com (2603:10b6:a03:3a1::19) To OSAPR01MB3892.jpnprd01.prod.outlook.com (2603:1096:604:5b::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: feea8891-53ea-4272-12ff-08da2d3d0bcb X-MS-TrafficTypeDiagnostic: OS3PR01MB8115:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bKJv6IYjntqBtWD9jgZgBoguA5BVlJ+IdDiZIB2Rwq2wfkBV2EzNyqVFJ6ElIKz0P+jUdym3hyBiar1JC7MoAV2/yo5m6/Xn0ojouRY13Tc8R+FxX3Ce//XXgTbDDTMecrk+u8PjrVoyCx4Ka7YxTSMbB6zf3GC+xBWVM5DS7hOJVFwm8994XYIcS2t1IoTNieaFsbMEaYJ2AI1AR5cQ7EDZDmUWvRbtyXXj7IbLGUvlTbtLqq4f8+08uWPBwjNUq+iycjgktlT211/sB4mLMz4vcfZPqLFIvMf6KnZRcJgqw+zhMXDG5+M2Ck2Rnsr+EHnOLQazoClvyVE84RM3xY38igljr/8FepHYKAQQG90xd2jScHmz51mdKinEApYDKk65Q4ppmwxnjM+pNbhiIegvq9uLN1Jz5JL3FEHU+1eh5EF67krbltwECFLOXrD4lgMwICKc45clmWm36LwOhjcbBkSM91W23dPaQw51iDT0DpodYdIUhpB/aQbKphglHtvK97CuwrvvOEMWGRFh47si4Sn9rWYzrLDJPofyjAjoQocACg7eZf4/nKoaVWGE9L8aJZvuWkPKn+n2N0qH86GVlRxYs5n0YHrRw7OJiH/5VQRBcWD7ApJ764ElNXPCxH/I0u7andXmfWw41GugYyy6KhIhj65Y5/TSt97AAS6QvnA0u4Ppmgr3U7cdtgYVi87UoTpsDc/6XNiXfgcLGJscoDAj6aORj07zUG9qJenZLtadj18CVBTlV5urHrpDKEtg9ZcUaLgeDyTqEM0AZxHlmG8eW4MvcQHq0209cFQ= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:OSAPR01MB3892.jpnprd01.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(4636009)(366004)(186003)(36756003)(2906002)(316002)(6506007)(6666004)(1076003)(86362001)(52116002)(38100700002)(38350700002)(30864003)(8936002)(103116003)(83380400001)(508600001)(5660300002)(66946007)(66556008)(66476007)(966005)(8676002)(2616005)(4326008)(6486002)(6512007)(26005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?z3UNmenW5wwWT8KOrPBfA+qpS3M/d9Xx4tFwLwHNVOM+nvvUnmexCb0AGo4H?= =?us-ascii?Q?HzrGrU3wfdmtloH3uRkRYslpxehAKKtLls9V4Lz96qIsmDKelP8oaHF3i9Ok?= =?us-ascii?Q?Bn95/8iZmxnKw31SaBIHMYmrQ0VBbgTQGIiJvryhdIl2eKjVQnQXrcN3exIi?= =?us-ascii?Q?KXpKhzmIwG2pe7VhrZSnJXWXNx/4+4FdGt0///02tMywGT4unj7R0EwxxJ1s?= =?us-ascii?Q?PbWcNNXbspGOaxs9/rBRfw1n+r3YtMVyYxm6ORVUGw0FG6gwcp/DAIs84sWn?= =?us-ascii?Q?NmIyUtFXLL+9cLbEPRTuRD3HSUIWFjB4MjnPwgiEEq9ZovRxF+MCwvH2Kzw5?= =?us-ascii?Q?GYAUd/HFrQYrz3bKvW8ZqoOd+wLEVEi0izK2FqyM1ds3F8T85QIwJfUS5pjB?= =?us-ascii?Q?qACXcB9CDp28PyL1ISa41GQ+3FiixhMx+wNdhn1VpNGZZhIozNBRYTrmyzsQ?= =?us-ascii?Q?0+PdnWOpNRXnIKLNZzieukWMwyfKCEzja+g3RvdWoMdlIv70ajxlbLQjXKNh?= =?us-ascii?Q?g073tVy5qfDajEHmDFlh+og7R12R8dB0KdTrEzTPoFjSv9F3Q0y7XDjGxWrZ?= =?us-ascii?Q?k/xBvBxpG4rlLS4P4TKa0z61ixIJPG9vTji+yP/SaNGHTprmo1ofczT2nvQI?= =?us-ascii?Q?y/aJgY4bPQz1pH03DXZXFtonTRTbp5rfAZRzaLO9OXVJufvK0FaskxxmKgcJ?= =?us-ascii?Q?BDgFRq7HvdZW46wIJmK1Q26ObHlF6ks9GhLfZ7miFy3JHBSaTPY3rQR12qQH?= =?us-ascii?Q?UGysBFSgBK4Aima1KozEfDWy1NgW4h3PsRaWFLeu9nP7GRG6wU740a1v4vDZ?= =?us-ascii?Q?mdLT6tw3dZM5gJzBUXfzLt6b5Gl34RfR/Ralcr4ERHHnh+wIXW3C8z8s7iHM?= =?us-ascii?Q?DoWgF1mCACh/O2VjQOoy6YwAC5NZZwOllhX752ku/SmUypQt7q9u8yhVZYPJ?= =?us-ascii?Q?U7zyrniyc6cfDE5qRhlVyWqhVpwC4wSQ5oRw9fu5RaFwqTI4hVkCMJJJfkui?= =?us-ascii?Q?f+8/uHltPdVOgN49XwKS7Pr0EnN/YX8IxxDR6tnl5p8VfEE4oux6Wiwj67ML?= =?us-ascii?Q?mHlHim6F0lN4mn2Ghj8JbPlYxoWaiwT+w1E6/ydwdDDto9yKzsnkV5qK76RX?= =?us-ascii?Q?8alqY3S6E2mpbNpXfqgioeGRz+i5hsoEafrsbbBNlJDk+/t5PkD5/VtY6uLr?= =?us-ascii?Q?bp3Umie/XLQiQLi9HJ37boFg7Qsg1tfroqOCkQFoOloLf8qwVhxpkFCNIyNI?= =?us-ascii?Q?LvDvcu/ILEaa/7eaZqipdhfxHo3aaDZDs8J44luG4wUEOdQJTaOV8Kc9XBrK?= =?us-ascii?Q?qtRtPwREuTFdyJtvgDW9akSH0g4yC5AKVm/8w+7hGWgdRTEw6q1gyQrYtM6V?= =?us-ascii?Q?XE7uMBHEUO2WGOm7T3G6Q2AO5R8iD3QDtiTE6ybQfCPA2+xl13KqVLszGXtN?= =?us-ascii?Q?bdsUBW8D7RQh80wpC0bQV3iv3LKkPMtX4arilQIIj+rWxaI568Up40hsXIWL?= =?us-ascii?Q?6zWFNZ1XzyRVBovAizuq0nPzuTVIJvoyjBJ0haqqeR2X10MYfKrO84Eryl3d?= =?us-ascii?Q?XyBmxDtA9+2gn+Aa4mFCOGz85xLM/WX6GL6Ks9G+4lKkgdR4v7FWPWeFqoZ4?= =?us-ascii?Q?Ufgvj/M9vKw8aKUgfg2k5AGFmwF4SQkApFPlmRaW8P1AtwnVGjxGOdK/n2Jv?= =?us-ascii?Q?EmH+UzuM17EWk/EGSPpZ5OY7yGp4GgJp4laZjr1PgTysSKXytQvEn0hMIm7X?= =?us-ascii?Q?eiUbZSi8lRnH/W7sf+ahKyIiLf4XcGkgBD1nuRIfdZOsYT2Kj35d?= X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: feea8891-53ea-4272-12ff-08da2d3d0bcb X-MS-Exchange-CrossTenant-AuthSource: OSAPR01MB3892.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2022 19:42:24.2646 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LrKmSgSeF4/JIh9PpKJE0vi52kiH5zTIH4Li5Rp7nEqKS7Ls0obrtC00DhM6X4x5RliwSyRQO+Rbey+hZjoSM65l3zt06F+3BDGmPDCHMMY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS3PR01MB8115 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms --- MAINTAINERS | 1 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-versaclock7.c | 1273 +++++++++++++++++++++++++++++++++ 4 files changed, 1284 insertions(+) create mode 100644 drivers/clk/clk-versaclock7.c diff --git a/MAINTAINERS b/MAINTAINERS index 8a23ea619..123e07900 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16540,6 +16540,7 @@ RENESAS VERSACLOCK 7 CLOCK DRIVER M: Alex Helms S: Maintained F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml +F: drivers/clk/clk-versaclock7.c =20 RESET CONTROLLER FRAMEWORK M: Philipp Zabel diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index d4d67fbae..efb85eada 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -351,6 +351,15 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. =20 +config COMMON_CLK_VC7 + tristate "Clock driver for Renesas Versaclock 7 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + Renesas Versaclock7 is a family of configurable clock generator + and jitter attenuator ICs with fractional and integer dividers. + config COMMON_CLK_STM32MP157 def_bool COMMON_CLK && MACH_STM32MP157 help diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630..e749ae1df 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_COMMON_CLK_TPS68470) +=3D clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) +=3D clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) +=3D clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) +=3D clk-versaclock5.o +obj-$(CONFIG_COMMON_CLK_VC7) +=3D clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) +=3D clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o =20 diff --git a/drivers/clk/clk-versaclock7.c b/drivers/clk/clk-versaclock7.c new file mode 100644 index 000000000..9f9128398 --- /dev/null +++ b/drivers/clk/clk-versaclock7.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common clock framework driver for the Versaclock7 family of timing devi= ces. + * + * Copyright (c) 2022 Renesas Electronics Corporation + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * 16-bit register address: the lower 8 bits of the register address come + * from the offset addr byte and the upper 8 bits come from the page regis= ter. + */ +#define VC7_PAGE_ADDR 0xFD +#define VC7_PAGE_WINDOW 256 +#define VC7_MAX_REG 0x364 + +/* Maximum number of banks supported by VC7 */ +#define VC7_NUM_BANKS 7 + +/* Maximum number of FODs supported by VC7 */ +#define VC7_NUM_FOD 3 + +/* Maximum number of IODs supported by VC7 */ +#define VC7_NUM_IOD 4 + +/* Maximum number of outputs supported by VC7 */ +#define VC7_NUM_OUT 12 + +/* VCO valid range is 9.5 GHz to 10.7 GHz */ +#define VC7_APLL_VCO_MIN 9500000000UL +#define VC7_APLL_VCO_MAX 10700000000UL + +/* APLL denominator is fixed at 2^27 */ +#define VC7_APLL_DENOMINATOR_BITS 27 + +/* FOD 1st stage denominator is fixed 2^34 */ +#define VC7_FOD_DENOMINATOR_BITS 34 + +/* IOD can operate between 1kHz and 650MHz */ +#define VC7_IOD_RATE_MIN 1000UL +#define VC7_IOD_RATE_MAX 650000000UL +#define VC7_IOD_MIN_DIVISOR 14 +#define VC7_IOD_MAX_DIVISOR 0x1ffffff /* 25-bit */ + +#define VC7_FOD_RATE_MIN 1000UL +#define VC7_FOD_RATE_MAX 650000000UL +#define VC7_FOD_1ST_STAGE_RATE_MIN 33000000UL /* 33 MHz */ +#define VC7_FOD_1ST_STAGE_RATE_MAX 650000000UL /* 650 MHz */ +#define VC7_FOD_1ST_INT_MAX 324 +#define VC7_FOD_2ND_INT_MIN 2 +#define VC7_FOD_2ND_INT_MAX 0x1ffff /* 17-bit */ + +/* VC7 Registers */ + +#define VC7_REG_XO_CNFG 0x2C +#define VC7_REG_XO_CNFG_COUNT 4 +#define VC7_REG_XO_IB_H_DIV_SHIFT 24 +#define VC7_REG_XO_IB_H_DIV_MASK GENMASK(28, VC7_REG_XO_IB_H_DIV_SHIFT) + +#define VC7_REG_APLL_FB_DIV_FRAC 0x120 +#define VC7_REG_APLL_FB_DIV_FRAC_COUNT 4 +#define VC7_REG_APLL_FB_DIV_FRAC_MASK GENMASK(26, 0) + +#define VC7_REG_APLL_FB_DIV_INT 0x124 +#define VC7_REG_APLL_FB_DIV_INT_COUNT 2 +#define VC7_REG_APLL_FB_DIV_INT_MASK GENMASK(9, 0) + +#define VC7_REG_APLL_CNFG 0x127 +#define VC7_REG_APLL_EN_DOUBLER BIT(0) + +#define VC7_REG_OUT_BANK_CNFG(idx) (0x280 + (0x4 * (idx))) +#define VC7_REG_OUTPUT_BANK_SRC_MASK GENMASK(2, 0) + +#define VC7_REG_FOD_INT_CNFG(idx) (0x1E0 + (0x10 * (idx))) +#define VC7_REG_FOD_INT_CNFG_COUNT 8 +#define VC7_REG_FOD_1ST_INT_MASK GENMASK(8, 0) +#define VC7_REG_FOD_2ND_INT_SHIFT 9 +#define VC7_REG_FOD_2ND_INT_MASK GENMASK(25, VC7_REG_FOD_2ND_INT_SHIFT) +#define VC7_REG_FOD_FRAC_SHIFT 26 +#define VC7_REG_FOD_FRAC_MASK GENMASK_ULL(59, VC7_REG_FOD_FRAC_SHIFT) + +#define VC7_REG_IOD_INT_CNFG(idx) (0x1C0 + (0x8 * (idx))) +#define VC7_REG_IOD_INT_CNFG_COUNT 4 +#define VC7_REG_IOD_INT_MASK GENMASK(24, 0) + +#define VC7_REG_ODRV_EN(idx) (0x240 + (0x4 * (idx))) +#define VC7_REG_OUT_DIS BIT(0) + +struct vc7_driver_data; +static const struct regmap_config vc7_regmap_config; + +/* Supported Renesas VC7 models */ +enum vc7_model { + VC7_RC21008A, +}; + +struct vc7_chip_info { + const enum vc7_model model; + const unsigned int banks[VC7_NUM_BANKS]; + const unsigned int num_banks; + const unsigned int outputs[VC7_NUM_OUT]; + const unsigned int num_outputs; +}; + +/* + * Changing the APLL frequency is currently not supported. + * The APLL will consist of an opaque block between the XO and FOD/IODs and + * its frequency will be computed based on the current state of the device. + */ +struct vc7_apll_data { + struct clk *clk; + struct vc7_driver_data *vc7; + u8 xo_ib_h_div; + u8 en_doubler; + u16 apll_fb_div_int; + u32 apll_fb_div_frac; +}; + +struct vc7_fod_data { + struct clk_hw hw; + struct vc7_driver_data *vc7; + unsigned int num; + u32 fod_1st_int; + u32 fod_2nd_int; + u64 fod_frac; +}; + +struct vc7_iod_data { + struct clk_hw hw; + struct vc7_driver_data *vc7; + unsigned int num; + u32 iod_int; +}; + +struct vc7_out_data { + struct clk_hw hw; + struct vc7_driver_data *vc7; + unsigned int num; + unsigned int out_dis; +}; + +struct vc7_driver_data { + struct i2c_client *client; + struct regmap *regmap; + const struct vc7_chip_info *chip_info; + + struct clk *pin_xin; + struct vc7_apll_data clk_apll; + struct vc7_fod_data clk_fod[VC7_NUM_FOD]; + struct vc7_iod_data clk_iod[VC7_NUM_IOD]; + struct vc7_out_data clk_out[VC7_NUM_OUT]; +}; + +struct vc7_bank_src_map { + enum vc7_bank_src_type { + VC7_FOD, + VC7_IOD, + } type; + union _divider { + struct vc7_iod_data *iod; + struct vc7_fod_data *fod; + } src; +}; + +static struct clk_hw *vc7_of_clk_get(struct of_phandle_args *clkspec, + void *data) +{ + struct vc7_driver_data *vc7 =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D vc7->chip_info->num_outputs) + return ERR_PTR(-EINVAL); + + return &vc7->clk_out[idx].hw; +} + +/* bank to output mapping, same across all variants */ +static const unsigned int output_bank_mapping[] =3D { + 0, /* Output 0 */ + 1, /* Output 1 */ + 2, /* Output 2 */ + 2, /* Output 3 */ + 3, /* Output 4 */ + 3, /* Output 5 */ + 3, /* Output 6 */ + 3, /* Output 7 */ + 4, /* Output 8 */ + 4, /* Output 9 */ + 5, /* Output 10 */ + 6 /* Output 11 */ +}; + +/** + * vc7_64_mul_64_to_128() - Multiply two u64 and return an unsigned 128-bi= t integer + * as an upper and lower part. + * + * @left: The left argument. + * @right: The right argument. + * @hi: The upper 64-bits of the 128-bit product. + * @lo: The lower 64-bits of the 128-bit product. + * + * From mul_64_64 in crypto/ecc.c:350 in the linux kernel, accessed in v5.= 17.2. + */ +static void vc7_64_mul_64_to_128(u64 left, u64 right, u64 *hi, u64 *lo) +{ + u64 a0 =3D left & 0xffffffffull; + u64 a1 =3D left >> 32; + u64 b0 =3D right & 0xffffffffull; + u64 b1 =3D right >> 32; + u64 m0 =3D a0 * b0; + u64 m1 =3D a0 * b1; + u64 m2 =3D a1 * b0; + u64 m3 =3D a1 * b1; + + m2 +=3D (m0 >> 32); + m2 +=3D m1; + + /* Overflow */ + if (m2 < m1) + m3 +=3D 0x100000000ull; + + *lo =3D (m0 & 0xffffffffull) | (m2 << 32); + *hi =3D m3 + (m2 >> 32); +} + +/** + * vc7_128_div_64_to_64() - Divides a 128-bit uint by a 64-bit divisor, re= turn a 64-bit quotient. + * + * @numhi: The uppper 64-bits of the dividend. + * @numlo: The lower 64-bits of the dividend. + * @den: The denominator (divisor). + * @r: The remainder, pass NULL if the remainder is not needed. + * + * Originally from libdivide, modified to use kernel u64/u32 types. + * + * See https://github.com/ridiculousfish/libdivide/blob/master/libdivide.h= #L471. + * + * Return: The 64-bit quotient of the division. + * + * In case of overflow of division by zero, max(u64) is returned. + */ +static u64 vc7_128_div_64_to_64(u64 numhi, u64 numlo, u64 den, u64 *r) +{ + // We work in base 2**32. + // A uint32 holds a single digit. A uint64 holds two digits. + // Our numerator is conceptually [num3, num2, num1, num0]. + // Our denominator is [den1, den0]. + const u64 b =3D ((u64)1 << 32); + + // The high and low digits of our computed quotient. + u32 q1, q0; + + // The normalization shift factor + int shift; + + // The high and low digits of our denominator (after normalizing). + // Also the low 2 digits of our numerator (after normalizing). + u32 den1, den0, num1, num0; + + // A partial remainder; + u64 rem; + + // The estimated quotient, and its corresponding remainder (unrelated to = true remainder). + u64 qhat, rhat; + + // Variables used to correct the estimated quotient. + u64 c1, c2; + + // Check for overflow and divide by 0. + if (numhi >=3D den) { + if (r) + *r =3D ~0ull; + return ~0ull; + } + + // Determine the normalization factor. We multiply den by this, so that i= ts leading digit + // is at least half b. In binary this means just shifting left by the num= ber of leading + // zeros, so that there's a 1 in the MSB. + // We also shift numer by the same amount. This cannot overflow because n= umhi < den. + // The expression (-shift & 63) is the same as (64 - shift), except it av= oids the UB of + // shifting by 64. The funny bitwise 'and' ensures that numlo does not ge= t shifted into + // numhi if shift is 0. clang 11 has an x86 codegen bug here: see LLVM bu= g 50118. + // The sequence below avoids it. + shift =3D __builtin_clzll(den); + den <<=3D shift; + numhi <<=3D shift; + numhi |=3D (numlo >> (-shift & 63)) & (-(s64)shift >> 63); + numlo <<=3D shift; + + // Extract the low digits of the numerator and both digits of the denomin= ator. + num1 =3D (u32)(numlo >> 32); + num0 =3D (u32)(numlo & 0xFFFFFFFFu); + den1 =3D (u32)(den >> 32); + den0 =3D (u32)(den & 0xFFFFFFFFu); + + // We wish to compute q1 =3D [n3 n2 n1] / [d1 d0]. + // Estimate q1 as [n3 n2] / [d1], and then correct it. + // Note while qhat may be 2 digits, q1 is always 1 digit. + qhat =3D div64_u64_rem(numhi, den1, &rhat); + c1 =3D qhat * den0; + c2 =3D rhat * b + num1; + if (c1 > c2) + qhat -=3D (c1 - c2 > den) ? 2 : 1; + q1 =3D (u32)qhat; + + // Compute the true (partial) remainder. + rem =3D numhi * b + num1 - q1 * den; + + // We wish to compute q0 =3D [rem1 rem0 n0] / [d1 d0]. + // Estimate q0 as [rem1 rem0] / [d1] and correct it. + qhat =3D div64_u64_rem(rem, den1, &rhat); + c1 =3D qhat * den0; + c2 =3D rhat * b + num0; + if (c1 > c2) + qhat -=3D (c1 - c2 > den) ? 2 : 1; + q0 =3D (u32)qhat; + + // Return remainder if requested. + if (r) + *r =3D (rem * b + num0 - q0 * den) >> shift; + return ((u64)q1 << 32) | q0; +} + +static int vc7_get_bank_clk(struct vc7_driver_data *vc7, + unsigned int bank_idx, + unsigned int output_bank_src, + struct vc7_bank_src_map *map) +{ + /* Mapping from Table 38 in datasheet */ + if (bank_idx =3D=3D 0 || bank_idx =3D=3D 1) { + switch (output_bank_src) { + case 0: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[0]; + return 0; + case 1: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[1]; + return 0; + case 4: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[0]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + default: + break; + } + } else if (bank_idx =3D=3D 2) { + switch (output_bank_src) { + case 1: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[1]; + return 0; + case 4: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[0]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + default: + break; + } + } else if (bank_idx =3D=3D 3) { + switch (output_bank_src) { + case 4: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[0]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + case 6: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[2]; + return 0; + default: + break; + } + } else if (bank_idx =3D=3D 4) { + switch (output_bank_src) { + case 0: + /* CLKIN1 not supported in this driver */ + break; + case 2: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[2]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + case 6: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[2]; + return 0; + case 7: + /* CLKIN0 not supported in this driver */ + break; + default: + break; + } + } else if (bank_idx =3D=3D 5) { + switch (output_bank_src) { + case 0: + /* CLKIN1 not supported in this driver */ + break; + case 1: + /* XIN_REFIN not supported in this driver */ + break; + case 2: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[2]; + return 0; + case 3: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[3]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + case 6: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[2]; + return 0; + case 7: + /* CLKIN0 not supported in this driver */ + break; + default: + break; + } + } else if (bank_idx =3D=3D 6) { + switch (output_bank_src) { + case 0: + /* CLKIN1 not supported in this driver */ + break; + case 2: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[2]; + return 0; + case 3: + map->type =3D VC7_IOD, + map->src.iod =3D &vc7->clk_iod[3]; + return 0; + case 5: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[1]; + return 0; + case 6: + map->type =3D VC7_FOD, + map->src.fod =3D &vc7->clk_fod[2]; + return 0; + case 7: + /* CLKIN0 not supported in this driver */ + break; + default: + break; + } + } + + pr_warn("bank_src%d =3D %d is not supported\n", bank_idx, output_bank_src= ); + return -1; +} + +static int vc7_read_apll(struct vc7_driver_data *vc7) +{ + int err; + u32 val32; + u16 val16; + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_XO_CNFG, + (u32 *)&val32, + VC7_REG_XO_CNFG_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read XO_CNFG\n"); + return err; + } + + vc7->clk_apll.xo_ib_h_div =3D (val32 & VC7_REG_XO_IB_H_DIV_MASK) + >> VC7_REG_XO_IB_H_DIV_SHIFT; + + err =3D regmap_read(vc7->regmap, + VC7_REG_APLL_CNFG, + &val32); + if (err) { + dev_err(&vc7->client->dev, "failed to read APLL_CNFG\n"); + return err; + } + + vc7->clk_apll.en_doubler =3D val32 & VC7_REG_APLL_EN_DOUBLER; + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_APLL_FB_DIV_FRAC, + (u32 *)&val32, + VC7_REG_APLL_FB_DIV_FRAC_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read APLL_FB_DIV_FRAC\n"); + return err; + } + + vc7->clk_apll.apll_fb_div_frac =3D val32 & VC7_REG_APLL_FB_DIV_FRAC_MASK; + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_APLL_FB_DIV_INT, + (u16 *)&val16, + VC7_REG_APLL_FB_DIV_INT_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read APLL_FB_DIV_INT\n"); + return err; + } + + vc7->clk_apll.apll_fb_div_int =3D val16 & VC7_REG_APLL_FB_DIV_INT_MASK; + + return 0; +} + +static int vc7_read_fod(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + u64 val; + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_FOD_INT_CNFG(idx), + (u64 *)&val, + VC7_REG_FOD_INT_CNFG_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read FOD%d\n", idx); + return err; + } + + vc7->clk_fod[idx].fod_1st_int =3D (val & VC7_REG_FOD_1ST_INT_MASK); + vc7->clk_fod[idx].fod_2nd_int =3D + (val & VC7_REG_FOD_2ND_INT_MASK) >> VC7_REG_FOD_2ND_INT_SHIFT; + vc7->clk_fod[idx].fod_frac =3D (val & VC7_REG_FOD_FRAC_MASK) + >> VC7_REG_FOD_FRAC_SHIFT; + + return 0; +} + +static int vc7_write_fod(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + u64 val; + + /* + * FOD dividers are part of an atomic group where fod_1st_int, + * fod_2nd_int, and fod_frac must be written together. The new divider + * is applied when the MSB of fod_frac is written. + */ + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_FOD_INT_CNFG(idx), + (u64 *)&val, + VC7_REG_FOD_INT_CNFG_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read FOD%d\n", idx); + return err; + } + + val =3D u64_replace_bits(val, + vc7->clk_fod[idx].fod_1st_int, + VC7_REG_FOD_1ST_INT_MASK); + val =3D u64_replace_bits(val, + vc7->clk_fod[idx].fod_2nd_int, + VC7_REG_FOD_2ND_INT_MASK); + val =3D u64_replace_bits(val, + vc7->clk_fod[idx].fod_frac, + VC7_REG_FOD_FRAC_MASK); + + err =3D regmap_bulk_write(vc7->regmap, + VC7_REG_FOD_INT_CNFG(idx), + (u64 *)&val, + sizeof(u64)); + if (err) { + dev_err(&vc7->client->dev, "failed to write FOD%d\n", idx); + return err; + } + + return 0; +} + +static int vc7_read_iod(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + u32 val; + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_IOD_INT_CNFG(idx), + (u32 *)&val, + VC7_REG_IOD_INT_CNFG_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read IOD%d\n", idx); + return err; + } + + vc7->clk_iod[idx].iod_int =3D (val & VC7_REG_IOD_INT_MASK); + + return 0; +} + +static int vc7_write_iod(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + u32 val; + + /* + * IOD divider field is atomic and all bits must be written. + * The new divider is applied when the MSB of iod_int is written. + */ + + err =3D regmap_bulk_read(vc7->regmap, + VC7_REG_IOD_INT_CNFG(idx), + (u32 *)&val, + VC7_REG_IOD_INT_CNFG_COUNT); + if (err) { + dev_err(&vc7->client->dev, "failed to read IOD%d\n", idx); + return err; + } + + val =3D u32_replace_bits(val, + vc7->clk_iod[idx].iod_int, + VC7_REG_IOD_INT_MASK); + + err =3D regmap_bulk_write(vc7->regmap, + VC7_REG_IOD_INT_CNFG(idx), + (u32 *)&val, + sizeof(u32)); + if (err) { + dev_err(&vc7->client->dev, "failed to write IOD%d\n", idx); + return err; + } + + return 0; +} + +static int vc7_read_output(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + unsigned int val; + + err =3D regmap_read(vc7->regmap, + VC7_REG_ODRV_EN(idx), + &val); + if (err) { + dev_err(&vc7->client->dev, "failed to read ODRV_EN[%d]\n", idx); + return err; + } + + vc7->clk_out[idx].out_dis =3D val & VC7_REG_OUT_DIS; + + return 0; +} + +static int vc7_write_output(struct vc7_driver_data *vc7, unsigned int idx) +{ + int err; + + err =3D regmap_write_bits(vc7->regmap, + VC7_REG_ODRV_EN(idx), + VC7_REG_OUT_DIS, + vc7->clk_out[idx].out_dis); + + if (err) { + dev_err(&vc7->client->dev, "failed to write ODRV_EN[%d]\n", idx); + return err; + } + + return 0; +} + +static unsigned long vc7_get_apll_rate(struct vc7_driver_data *vc7) +{ + int err; + unsigned long xtal_rate; + u64 refin_div, apll_rate; + + xtal_rate =3D clk_get_rate(vc7->pin_xin); + err =3D vc7_read_apll(vc7); + if (err) { + dev_err(&vc7->client->dev, "unable to read apll\n"); + return err; + } + + /* 0 is bypassed, 1 is reserved */ + if (vc7->clk_apll.xo_ib_h_div < 2) + refin_div =3D xtal_rate; + else + refin_div =3D div64_u64(xtal_rate, vc7->clk_apll.xo_ib_h_div); + + if (vc7->clk_apll.en_doubler) + refin_div *=3D 2; + + /* divider =3D int + (frac / 2^27) */ + apll_rate =3D (refin_div * vc7->clk_apll.apll_fb_div_int) + + ((refin_div * vc7->clk_apll.apll_fb_div_frac) >> VC7_APLL_DENOMINATO= R_BITS); + + pr_debug("%s - xo_ib_h_div: %u, apll_fb_div_int: %u, apll_fb_div_frac: %u= \n", + __func__, vc7->clk_apll.xo_ib_h_div, vc7->clk_apll.apll_fb_div_int, + vc7->clk_apll.apll_fb_div_frac); + pr_debug("%s - refin_div: %llu, apll rate: %llu\n", + __func__, refin_div, apll_rate); + + return apll_rate; +} + +static void vc7_calc_iod_divider(unsigned long rate, unsigned long parent_= rate, + u32 *divider) +{ + *divider =3D DIV_ROUND_UP(parent_rate, rate); + if (*divider < VC7_IOD_MIN_DIVISOR) + *divider =3D VC7_IOD_MIN_DIVISOR; + if (*divider > VC7_IOD_MAX_DIVISOR) + *divider =3D VC7_IOD_MAX_DIVISOR; +} + +static void vc7_calc_fod_1st_stage(unsigned long rate, unsigned long paren= t_rate, + u32 *div_int, u64 *div_frac) +{ + u64 rem; + + *div_int =3D (u32)div64_u64_rem(parent_rate, rate, &rem); + *div_frac =3D div64_u64(rem << VC7_FOD_DENOMINATOR_BITS, rate); +} + +static unsigned long vc7_calc_fod_1st_stage_rate(unsigned long parent_rate, + u32 fod_1st_int, u64 fod_frac) +{ + u64 numer, denom, hi, lo, divisor; + + numer =3D fod_frac; + denom =3D BIT_ULL(VC7_FOD_DENOMINATOR_BITS); + + if (fod_frac) { + vc7_64_mul_64_to_128(parent_rate, denom, &hi, &lo); + divisor =3D ((u64)fod_1st_int * denom) + numer; + return vc7_128_div_64_to_64(hi, lo, divisor, NULL); + } + + return div64_u64(parent_rate, fod_1st_int); +} + +static unsigned long vc7_calc_fod_2nd_stage_rate(unsigned long parent_rate, + u32 fod_1st_int, u32 fod_2nd_int, u64 fod_frac) +{ + unsigned long fod_1st_stage_rate; + + fod_1st_stage_rate =3D vc7_calc_fod_1st_stage_rate(parent_rate, fod_1st_i= nt, fod_frac); + + if (fod_2nd_int < 2) + return fod_1st_stage_rate; + + /* + * There is a div-by-2 preceding the 2nd stage integer divider + * (not shown on block diagram) so the actual 2nd stage integer + * divisor is 2 * N. + */ + return div64_u64(fod_1st_stage_rate >> 1, fod_2nd_int); +} + +static void vc7_calc_fod_divider(unsigned long rate, unsigned long parent_= rate, + u32 *fod_1st_int, u32 *fod_2nd_int, u64 *fod_frac) +{ + unsigned int allow_frac, i, best_frac_i; + unsigned long first_stage_rate; + + vc7_calc_fod_1st_stage(rate, parent_rate, fod_1st_int, fod_frac); + first_stage_rate =3D vc7_calc_fod_1st_stage_rate(parent_rate, *fod_1st_in= t, *fod_frac); + + *fod_2nd_int =3D 0; + + /* Do we need the second stage integer divider? */ + if (first_stage_rate < VC7_FOD_1ST_STAGE_RATE_MIN) { + allow_frac =3D 0; + best_frac_i =3D VC7_FOD_2ND_INT_MIN; + + for (i =3D VC7_FOD_2ND_INT_MIN; i <=3D VC7_FOD_2ND_INT_MAX; i++) { + /* + * 1) There is a div-by-2 preceding the 2nd stage integer divider + * (not shown on block diagram) so the actual 2nd stage integer + * divisor is 2 * N. + * 2) Attempt to find an integer solution first. This means stepping + * through each 2nd stage integer and recalculating the 1st stage + * until the 1st stage frequency is out of bounds. If no integer + * solution is found, use the best fractional solution. + */ + vc7_calc_fod_1st_stage(parent_rate, rate * 2 * i, fod_1st_int, fod_frac= ); + first_stage_rate =3D vc7_calc_fod_1st_stage_rate(parent_rate, + *fod_1st_int, + *fod_frac); + + /* Remember the first viable fractional solution */ + if (best_frac_i =3D=3D VC7_FOD_2ND_INT_MIN && + first_stage_rate > VC7_FOD_1ST_STAGE_RATE_MIN) { + best_frac_i =3D i; + } + + /* Is the divider viable? Prefer integer solutions over fractional. */ + if (*fod_1st_int < VC7_FOD_1ST_INT_MAX && + first_stage_rate >=3D VC7_FOD_1ST_STAGE_RATE_MIN && + (allow_frac || *fod_frac =3D=3D 0)) { + *fod_2nd_int =3D i; + break; + } + + /* Ran out of divisors or the 1st stage frequency is out of range */ + if (i >=3D VC7_FOD_2ND_INT_MAX || + first_stage_rate > VC7_FOD_1ST_STAGE_RATE_MAX) { + allow_frac =3D 1; + i =3D best_frac_i; + + /* Restore the best frac and rerun the loop for the last time */ + if (best_frac_i !=3D VC7_FOD_2ND_INT_MIN) + i--; + + continue; + } + } + } +} + +static unsigned long vc7_fod_recalc_rate(struct clk_hw *hw, unsigned long = parent_rate) +{ + struct vc7_fod_data *fod =3D container_of(hw, struct vc7_fod_data, hw); + struct vc7_driver_data *vc7 =3D fod->vc7; + int err; + unsigned long fod_rate; + + err =3D vc7_read_fod(vc7, fod->num); + if (err) { + dev_err(&vc7->client->dev, "error reading registers for %s\n", + clk_hw_get_name(hw)); + return err; + } + + pr_debug("%s - %s: parent_rate: %lu\n", __func__, clk_hw_get_name(hw), pa= rent_rate); + + fod_rate =3D vc7_calc_fod_2nd_stage_rate(parent_rate, fod->fod_1st_int, + fod->fod_2nd_int, fod->fod_frac); + + pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", + __func__, clk_hw_get_name(hw), + fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); + pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); + + return fod_rate; +} + +static long vc7_fod_round_rate(struct clk_hw *hw, unsigned long rate, unsi= gned long *parent_rate) +{ + struct vc7_fod_data *fod =3D container_of(hw, struct vc7_fod_data, hw); + unsigned long fod_rate; + + pr_debug("%s - %s: requested rate: %lu, parent_rate: %lu\n", + __func__, clk_hw_get_name(hw), rate, *parent_rate); + + vc7_calc_fod_divider(rate, *parent_rate, + &fod->fod_1st_int, &fod->fod_2nd_int, &fod->fod_frac); + fod_rate =3D vc7_calc_fod_2nd_stage_rate(*parent_rate, fod->fod_1st_int, + fod->fod_2nd_int, fod->fod_frac); + + pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", + __func__, clk_hw_get_name(hw), + fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); + pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); + + return fod_rate; +} + +static int vc7_fod_set_rate(struct clk_hw *hw, unsigned long rate, unsigne= d long parent_rate) +{ + struct vc7_fod_data *fod =3D container_of(hw, struct vc7_fod_data, hw); + struct vc7_driver_data *vc7 =3D fod->vc7; + unsigned long fod_rate; + + pr_debug("%s - %s: rate: %lu, parent_rate: %lu\n", + __func__, clk_hw_get_name(hw), rate, parent_rate); + + if (rate < VC7_FOD_RATE_MIN || rate > VC7_FOD_RATE_MAX) { + dev_err(&vc7->client->dev, + "requested frequency %lu Hz for %s is out of range\n", + rate, clk_hw_get_name(hw)); + return -EINVAL; + } + + vc7_write_fod(vc7, fod->num); + + fod_rate =3D vc7_calc_fod_2nd_stage_rate(parent_rate, fod->fod_1st_int, + fod->fod_2nd_int, fod->fod_frac); + + pr_debug("%s - %s: fod_1st_int: %u, fod_2nd_int: %u, fod_frac: %llu\n", + __func__, clk_hw_get_name(hw), + fod->fod_1st_int, fod->fod_2nd_int, fod->fod_frac); + pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); + + return 0; +} + +static const struct clk_ops vc7_fod_ops =3D { + .recalc_rate =3D vc7_fod_recalc_rate, + .round_rate =3D vc7_fod_round_rate, + .set_rate =3D vc7_fod_set_rate, +}; + +static unsigned long vc7_iod_recalc_rate(struct clk_hw *hw, unsigned long = parent_rate) +{ + struct vc7_iod_data *iod =3D container_of(hw, struct vc7_iod_data, hw); + struct vc7_driver_data *vc7 =3D iod->vc7; + int err; + unsigned long iod_rate; + + err =3D vc7_read_iod(vc7, iod->num); + if (err) { + dev_err(&vc7->client->dev, "error reading registers for %s\n", + clk_hw_get_name(hw)); + return err; + } + + iod_rate =3D div64_u64(parent_rate, iod->iod_int); + + pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->io= d_int); + pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), iod_rate); + + return iod_rate; +} + +static long vc7_iod_round_rate(struct clk_hw *hw, unsigned long rate, unsi= gned long *parent_rate) +{ + struct vc7_iod_data *iod =3D container_of(hw, struct vc7_iod_data, hw); + unsigned long iod_rate; + + pr_debug("%s - %s: requested rate: %lu, parent_rate: %lu\n", + __func__, clk_hw_get_name(hw), rate, *parent_rate); + + vc7_calc_iod_divider(rate, *parent_rate, &iod->iod_int); + iod_rate =3D div64_u64(*parent_rate, iod->iod_int); + + pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->io= d_int); + pr_debug("%s - %s rate: %ld\n", __func__, clk_hw_get_name(hw), iod_rate); + + return iod_rate; +} + +static int vc7_iod_set_rate(struct clk_hw *hw, unsigned long rate, unsigne= d long parent_rate) +{ + struct vc7_iod_data *iod =3D container_of(hw, struct vc7_iod_data, hw); + struct vc7_driver_data *vc7 =3D iod->vc7; + unsigned long iod_rate; + + pr_debug("%s - %s: rate: %lu, parent_rate: %lu\n", + __func__, clk_hw_get_name(hw), rate, parent_rate); + + if (rate < VC7_IOD_RATE_MIN || rate > VC7_IOD_RATE_MAX) { + dev_err(&vc7->client->dev, + "requested frequency %lu Hz for %s is out of range\n", + rate, clk_hw_get_name(hw)); + return -EINVAL; + } + + vc7_write_iod(vc7, iod->num); + + iod_rate =3D div64_u64(parent_rate, iod->iod_int); + + pr_debug("%s - %s: iod_int: %u\n", __func__, clk_hw_get_name(hw), iod->io= d_int); + pr_debug("%s - %s rate: %ld\n", __func__, clk_hw_get_name(hw), iod_rate); + + return 0; +} + +static const struct clk_ops vc7_iod_ops =3D { + .recalc_rate =3D vc7_iod_recalc_rate, + .round_rate =3D vc7_iod_round_rate, + .set_rate =3D vc7_iod_set_rate, +}; + +static int vc7_clk_out_prepare(struct clk_hw *hw) +{ + struct vc7_out_data *out =3D container_of(hw, struct vc7_out_data, hw); + struct vc7_driver_data *vc7 =3D out->vc7; + int err; + + out->out_dis =3D 0; + + err =3D vc7_write_output(vc7, out->num); + if (err) { + dev_err(&vc7->client->dev, "error writing registers for %s\n", + clk_hw_get_name(hw)); + return err; + } + + pr_debug("%s - %s: clk prepared\n", __func__, clk_hw_get_name(hw)); + + return 0; +} + +static void vc7_clk_out_unprepare(struct clk_hw *hw) +{ + struct vc7_out_data *out =3D container_of(hw, struct vc7_out_data, hw); + struct vc7_driver_data *vc7 =3D out->vc7; + int err; + + out->out_dis =3D 1; + + err =3D vc7_write_output(vc7, out->num); + if (err) { + dev_err(&vc7->client->dev, "error writing registers for %s\n", + clk_hw_get_name(hw)); + return; + } + + pr_debug("%s - %s: clk unprepared\n", __func__, clk_hw_get_name(hw)); +} + +static int vc7_clk_out_is_enabled(struct clk_hw *hw) +{ + struct vc7_out_data *out =3D container_of(hw, struct vc7_out_data, hw); + struct vc7_driver_data *vc7 =3D out->vc7; + int err, is_enabled; + + err =3D vc7_read_output(vc7, out->num); + if (err) { + dev_err(&vc7->client->dev, "error reading registers for %s\n", + clk_hw_get_name(hw)); + return err; + } + + is_enabled =3D !out->out_dis; + + pr_debug("%s - %s: is_enabled=3D%d\n", __func__, clk_hw_get_name(hw), is_= enabled); + + return is_enabled; +} + +static const struct clk_ops vc7_clk_out_ops =3D { + .prepare =3D vc7_clk_out_prepare, + .unprepare =3D vc7_clk_out_unprepare, + .is_enabled =3D vc7_clk_out_is_enabled, +}; + +static int vc7_probe(struct i2c_client *client) +{ + struct vc7_driver_data *vc7; + struct clk_init_data clk_init; + struct vc7_bank_src_map bank_src_map; + const char *apll_name; + const char *parent_names[1]; + unsigned int i, val, bank_idx, output_idx; + unsigned long apll_rate; + int ret; + + vc7 =3D devm_kzalloc(&client->dev, sizeof(*vc7), GFP_KERNEL); + if (!vc7) + return -ENOMEM; + + i2c_set_clientdata(client, vc7); + vc7->client =3D client; + vc7->chip_info =3D of_device_get_match_data(&client->dev); + + vc7->pin_xin =3D devm_clk_get(&client->dev, "xin"); + if (PTR_ERR(vc7->pin_xin) =3D=3D -EPROBE_DEFER) { + return dev_err_probe(&client->dev, -EPROBE_DEFER, + "xin not specified\n"); + } + + vc7->regmap =3D devm_regmap_init_i2c(client, &vc7_regmap_config); + if (IS_ERR(vc7->regmap)) { + return dev_err_probe(&client->dev, PTR_ERR(vc7->regmap), + "failed to allocate register map\n"); + } + + /* Register APLL */ + apll_rate =3D vc7_get_apll_rate(vc7); + apll_name =3D kasprintf(GFP_KERNEL, "%pOFn_apll", client->dev.of_node); + vc7->clk_apll.clk =3D clk_register_fixed_rate(&client->dev, apll_name, + __clk_get_name(vc7->pin_xin), + 0, apll_rate); + kfree(apll_name); /* ccf made a copy of the name */ + if (IS_ERR(vc7->clk_apll.clk)) { + return dev_err_probe(&client->dev, PTR_ERR(vc7->clk_apll.clk), + "failed to register apll\n"); + } + + /* Register FODs */ + for (i =3D 0; i < VC7_NUM_FOD; i++) { + memset(&clk_init, 0, sizeof(clk_init)); + clk_init.name =3D kasprintf(GFP_KERNEL, "%pOFn_fod%d", client->dev.of_no= de, i); + clk_init.ops =3D &vc7_fod_ops; + clk_init.parent_names =3D parent_names; + parent_names[0] =3D __clk_get_name(vc7->clk_apll.clk); + clk_init.num_parents =3D 1; + vc7->clk_fod[i].num =3D i; + vc7->clk_fod[i].vc7 =3D vc7; + vc7->clk_fod[i].hw.init =3D &clk_init; + ret =3D devm_clk_hw_register(&client->dev, &vc7->clk_fod[i].hw); + if (ret) + goto err_clk_register; + kfree(clk_init.name); /* ccf made a copy of the name */ + } + + /* Register IODs */ + for (i =3D 0; i < VC7_NUM_IOD; i++) { + memset(&clk_init, 0, sizeof(clk_init)); + clk_init.name =3D kasprintf(GFP_KERNEL, "%pOFn_iod%d", client->dev.of_no= de, i); + clk_init.ops =3D &vc7_iod_ops; + clk_init.parent_names =3D parent_names; + parent_names[0] =3D __clk_get_name(vc7->clk_apll.clk); + clk_init.num_parents =3D 1; + vc7->clk_iod[i].num =3D i; + vc7->clk_iod[i].vc7 =3D vc7; + vc7->clk_iod[i].hw.init =3D &clk_init; + ret =3D devm_clk_hw_register(&client->dev, &vc7->clk_iod[i].hw); + if (ret) + goto err_clk_register; + kfree(clk_init.name); /* ccf made a copy of the name */ + } + + /* Register outputs */ + for (i =3D 0; i < vc7->chip_info->num_outputs; i++) { + /* + * This driver does not support remapping FOD/IOD to banks. + * The device state is read and the driver is setup to match + * the device's existing mapping. + */ + output_idx =3D vc7->chip_info->outputs[i]; + bank_idx =3D output_bank_mapping[output_idx]; + + regmap_read(vc7->regmap, VC7_REG_OUT_BANK_CNFG(bank_idx), &val); + val &=3D VC7_REG_OUTPUT_BANK_SRC_MASK; + + memset(&bank_src_map, 0, sizeof(bank_src_map)); + ret =3D vc7_get_bank_clk(vc7, bank_idx, val, &bank_src_map); + if (ret) { + dev_err_probe(&client->dev, ret, + "unable to register output %d\n", output_idx); + return ret; + } + + switch (bank_src_map.type) { + case VC7_FOD: + parent_names[0] =3D clk_hw_get_name(&bank_src_map.src.fod->hw); + break; + case VC7_IOD: + parent_names[0] =3D clk_hw_get_name(&bank_src_map.src.iod->hw); + break; + } + + memset(&clk_init, 0, sizeof(clk_init)); + clk_init.name =3D kasprintf(GFP_KERNEL, "%pOFn_out%d", + client->dev.of_node, output_idx); + clk_init.ops =3D &vc7_clk_out_ops; + clk_init.flags =3D CLK_SET_RATE_PARENT; + clk_init.parent_names =3D parent_names; + clk_init.num_parents =3D 1; + vc7->clk_out[output_idx].num =3D output_idx; + vc7->clk_out[output_idx].vc7 =3D vc7; + vc7->clk_out[output_idx].hw.init =3D &clk_init; + ret =3D devm_clk_hw_register(&client->dev, &vc7->clk_out[output_idx].hw); + if (ret) + goto err_clk_register; + kfree(clk_init.name); /* ccf made a copy of the name */ + } + + ret =3D of_clk_add_hw_provider(client->dev.of_node, vc7_of_clk_get, vc7); + if (ret) { + dev_err_probe(&client->dev, ret, "unable to add clk provider\n"); + goto err_clk; + } + + return ret; + +err_clk_register: + dev_err_probe(&client->dev, ret, + "unable to register %s\n", clk_init.name); + kfree(clk_init.name); /* ccf made a copy of the name */ +err_clk: + clk_unregister_fixed_rate(vc7->clk_apll.clk); + return ret; +} + +static int vc7_remove(struct i2c_client *client) +{ + struct vc7_driver_data *vc7 =3D i2c_get_clientdata(client); + + of_clk_del_provider(client->dev.of_node); + clk_unregister_fixed_rate(vc7->clk_apll.clk); + + return 0; +} + +static bool vc7_volatile_reg(struct device *dev, unsigned int reg) +{ + if (reg =3D=3D VC7_PAGE_ADDR) + return false; + + return true; +} + +static const struct vc7_chip_info vc7_rc21008a_info =3D { + .model =3D VC7_RC21008A, + .banks =3D {1, 2, 3, 4, 5, 6}, + .num_banks =3D 6, + .outputs =3D {1, 2, 3, 6, 7, 8, 10, 11}, + .num_outputs =3D 8, +}; + +static struct regmap_range_cfg vc7_range_cfg[] =3D { +{ + .range_min =3D 0, + .range_max =3D VC7_MAX_REG, + .selector_reg =3D VC7_PAGE_ADDR, + .selector_mask =3D 0xFF, + .selector_shift =3D 0, + .window_start =3D 0, + .window_len =3D VC7_PAGE_WINDOW, +}}; + +static const struct regmap_config vc7_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D VC7_MAX_REG, + .ranges =3D vc7_range_cfg, + .num_ranges =3D ARRAY_SIZE(vc7_range_cfg), + .volatile_reg =3D vc7_volatile_reg, + .cache_type =3D REGCACHE_RBTREE, + .can_multi_write =3D true, + .reg_format_endian =3D REGMAP_ENDIAN_LITTLE, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, +}; + +static const struct i2c_device_id vc7_i2c_id[] =3D { + { "rc21008a", VC7_RC21008A }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, vc7_i2c_id); + +static const struct of_device_id vc7_of_match[] =3D { + { .compatible =3D "renesas,rc21008a", .data =3D &vc7_rc21008a_info }, + {}, +}; +MODULE_DEVICE_TABLE(of, vc7_of_match); + +static struct i2c_driver vc7_i2c_driver =3D { + .driver =3D { + .name =3D "vc7", + .of_match_table =3D vc7_of_match, + }, + .probe_new =3D vc7_probe, + .remove =3D vc7_remove, + .id_table =3D vc7_i2c_id, +}; +module_i2c_driver(vc7_i2c_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Alex Helms