From nobody Sun Sep 22 03:33:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9230AC433EF for ; Tue, 3 May 2022 14:14:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236855AbiECOSY (ORCPT ); Tue, 3 May 2022 10:18:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236823AbiECOSU (ORCPT ); Tue, 3 May 2022 10:18:20 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AD9C1D31D; Tue, 3 May 2022 07:14:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 212C21F434F5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651587286; bh=B/lWFQk3lVUU0hXgygkG1qi0I0fP+5nA3QdY/qxIP3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R1HVBvgJXydgovzNB6lsCOGgxwi2iNXDiVfrHuKH0JUlfN8J8kc+InrHrIjuNKjxu xRqSX4FSxpZ4Ew45Of5uwtEEebkUIgTw7VBvtlRxb0Hn545Sznaw9jMk5eUANhnmcX MAphBWp/B7EjUlNZU44UVBKQcyDP+SgwIAgTQHLYkvehncZ6oynA0hta2VdhOHE/fY EsyA+/9L6BwSTDJ9mg1JkifkAyO6KJJgOfLvtrLhyHRBeEjqXS1EaXLZMrj1UTdu7W CnlU67kUesL368u/mCuKcAIkYV+WBNRHsNRk2JJztAB+dBOmDl6uBJqRLA7nuEkKWa HRJDfbsZ20yVQ== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, matthias.bgg@gmail.com, chun-jie.chen@mediatek.com, angelogioacchino.delregno@collabora.com, weiyi.lu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, nfraprado@collabora.com Subject: [PATCH v2 1/2] dt-bindings: power: Add MediaTek Helio X10 MT6795 power domains Date: Tue, 3 May 2022 16:14:40 +0200 Message-Id: <20220503141441.125852-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503141441.125852-1-angelogioacchino.delregno@collabora.com> References: <20220503141441.125852-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add power domains dt-bindings for MediaTek Helio X10 (MT6795). Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../power/mediatek,power-controller.yaml | 2 ++ include/dt-bindings/power/mt6795-power.h | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/dt-bindings/power/mt6795-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 135c6f722091..b448101fac43 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -23,6 +23,7 @@ properties: =20 compatible: enum: + - mediatek,mt6795-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller @@ -62,6 +63,7 @@ patternProperties: reg: description: | Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt6795-power.h" - for MT8167 type= power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type= power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type= power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type= power domain. diff --git a/include/dt-bindings/power/mt6795-power.h b/include/dt-bindings= /power/mt6795-power.h new file mode 100644 index 000000000000..b0fc26cb1da4 --- /dev/null +++ b/include/dt-bindings/power/mt6795-power.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef _DT_BINDINGS_POWER_MT6795_POWER_H +#define _DT_BINDINGS_POWER_MT6795_POWER_H + +#define MT6795_POWER_DOMAIN_MM 0 +#define MT6795_POWER_DOMAIN_VDEC 1 +#define MT6795_POWER_DOMAIN_VENC 2 +#define MT6795_POWER_DOMAIN_ISP 3 +#define MT6795_POWER_DOMAIN_MJC 4 +#define MT6795_POWER_DOMAIN_AUDIO 5 +#define MT6795_POWER_DOMAIN_MFG_ASYNC 6 +#define MT6795_POWER_DOMAIN_MFG_2D 7 +#define MT6795_POWER_DOMAIN_MFG 8 +#define MT6795_POWER_DOMAIN_MODEM 9 + +#endif /* _DT_BINDINGS_POWER_MT6795_POWER_H */ --=20 2.35.1 From nobody Sun Sep 22 03:33:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EC98C433EF for ; Tue, 3 May 2022 14:14:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbiECOS1 (ORCPT ); Tue, 3 May 2022 10:18:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236835AbiECOSV (ORCPT ); Tue, 3 May 2022 10:18:21 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0AA8192B5; Tue, 3 May 2022 07:14:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 027491F43549 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651587287; bh=Vzt5rJ5w7RADVz/xg7c0ik/5e8mPzC+52IMY2R0fGcU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G6yBvaUFOtq2v5zmB5Z+4pdtwSex6+dHxIdEZrcLqxGga+4XL1AIF+fl+rZ/d+eAl qTP6097PFgYVBcu6+wC/g1/r4ZBLftyWr3N0RSGZyq0K2/OTXTbaovJWPoiKi9GnjI XHc3YgavRqfrGGyQdE/HDgre0kA3Iszglg96hVcjl+ANeTLQyR8eSJeRJwtr3oGmwo Bn9qG/LhrsL0tvHPDVP+nglNqX00jMqFlWT0eQPUbx+rwSHGP9of7J+Fk1RosrQC13 hWk4ZmcMKXYvC7T98XJvBSaKGcDsJgqTnT4NiUVZqIx+B925ZNr6TMS3vCh6svtFD7 vYrlCGdmP0uSQ== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, matthias.bgg@gmail.com, chun-jie.chen@mediatek.com, angelogioacchino.delregno@collabora.com, weiyi.lu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, nfraprado@collabora.com Subject: [PATCH v2 2/2] soc: mediatek: pm-domains: Add support for Helio X10 MT6795 Date: Tue, 3 May 2022 16:14:41 +0200 Message-Id: <20220503141441.125852-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503141441.125852-1-angelogioacchino.delregno@collabora.com> References: <20220503141441.125852-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pm-domains (mtcmos) data for MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt6795-pm-domains.h | 112 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 117 insertions(+) create mode 100644 drivers/soc/mediatek/mt6795-pm-domains.h diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediate= k/mt6795-pm-domains.h new file mode 100644 index 000000000000..ef07c9dfdd9b --- /dev/null +++ b/drivers/soc/mediatek/mt6795-pm-domains.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT6795 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt6795[] =3D { + [MT6795_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D PWR_STATUS_VDEC, + .ctl_offs =3D SPM_VDE_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + }, + [MT6795_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D SPM_VEN_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_ISP] =3D { + .name =3D "isp", + .sta_mask =3D PWR_STATUS_ISP, + .ctl_offs =3D SPM_ISP_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + }, + [MT6795_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D SPM_DIS_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_infracfg =3D { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), + }, + }, + [MT6795_POWER_DOMAIN_MJC] =3D { + .name =3D "mjc", + .sta_mask =3D BIT(20), + .ctl_offs =3D 0x298, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D SPM_AUDIO_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_MFG_ASYNC] =3D { + .name =3D "mfg_async", + .sta_mask =3D PWR_STATUS_MFG_ASYNC, + .ctl_offs =3D SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D 0, + }, + [MT6795_POWER_DOMAIN_MFG_2D] =3D { + .name =3D "mfg_2d", + .sta_mask =3D PWR_STATUS_MFG_2D, + .ctl_offs =3D SPM_MFG_2D_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + }, + [MT6795_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D SPM_MFG_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(13, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 16), + .bp_infracfg =3D { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + }, + }, +}; + +static const struct scpsys_soc_data mt6795_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt6795, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt6795), +}; + +#endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 5ced254b082b..4da53488c381 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -16,6 +16,7 @@ #include #include =20 +#include "mt6795-pm-domains.h" #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" @@ -555,6 +556,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsy= s) } =20 static const struct of_device_id scpsys_of_match[] =3D { + { + .compatible =3D "mediatek,mt6795-power-controller", + .data =3D &mt6795_scpsys_data, + }, { .compatible =3D "mediatek,mt8167-power-controller", .data =3D &mt8167_scpsys_data, --=20 2.35.1