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Peter Anvin" Subject: [PATCH 1/2] x86/pat: fix x86_has_pat_wp() Date: Tue, 3 May 2022 15:22:06 +0200 Message-Id: <20220503132207.17234-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220503132207.17234-1-jgross@suse.com> References: <20220503132207.17234-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1651584159304100001 Content-Type: text/plain; charset="utf-8" x86_has_pat_wp() is using a wrong test, as it relies on the normal PAT configuration used by the kernel. In case the PAT MSR has been setup by another entity (e.g. BIOS or Xen hypervisor) it might return false even if the PAT configuration is allowing WP mappings. Fixes: 1f6f655e01ad ("x86/mm: Add a x86_has_pat_wp() helper") Signed-off-by: Juergen Gross --- arch/x86/mm/init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index d8cfce221275..71e182ebced3 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -80,7 +80,8 @@ static uint8_t __pte2cachemode_tbl[8] =3D { /* Check that the write-protect PAT entry is set for write-protect */ bool x86_has_pat_wp(void) { - return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] =3D=3D _PAGE_CACHE_MODE_W= P; + return __pte2cachemode_tbl[__cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]] =3D= =3D + _PAGE_CACHE_MODE_WP; } =20 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) --=20 2.35.3 From nobody Sun May 10 13:25:35 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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Tue, 03 May 2022 13:22:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0a0e3f69-cae4-11ec-a406-831a346695d4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1651584131; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vpkV8V5Y+6Vb55bRfQcavzTocu4t1BaNWLiM7KsOY1Y=; b=ubKL3UxTpmVXRWOdBpBxP1Blc7iCSFjpprMuVtEqjUkNxvt5KgAL1kIcTNjkGyUG/j5v7g eP8pHFW6Rm0suxVOYcYDsv/lL+qGJmUY9KnmCMOK0w391MnS/4uG7jTU1+tHyDmy49tmTD f4U0Tn/Uxnm7o0c9V2tpCWb8OLMoFfk= From: Juergen Gross To: xen-devel@lists.xenproject.org, x86@kernel.org, linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jbeulich@suse.com, Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH 2/2] x86/pat: add functions to query specific cache mode availability Date: Tue, 3 May 2022 15:22:07 +0200 Message-Id: <20220503132207.17234-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220503132207.17234-1-jgross@suse.com> References: <20220503132207.17234-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1651584154380100001 Content-Type: text/plain; charset="utf-8" Some drivers are using pat_enabled() in order to test availability of special caching modes (WC and UC-). This will lead to false negatives in case the system was booted e.g. with the "nopat" variant and the BIOS did setup the PAT MSR supporting the queried mode, or if the system is running as a Xen PV guest. Add test functions for those caching modes instead and use them at the appropriate places. For symmetry reasons export the already existing x86_has_pat_wp() for modules, too. Fixes: bdd8b6c98239 ("drm/i915: replace X86_FEATURE_PAT with pat_enabled()") Fixes: ae749c7ab475 ("PCI: Add arch_can_pci_mmap_wc() macro") Signed-off-by: Juergen Gross --- arch/x86/include/asm/memtype.h | 2 ++ arch/x86/include/asm/pci.h | 2 +- arch/x86/mm/init.c | 25 +++++++++++++++++++++--- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 8 ++++---- 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/memtype.h b/arch/x86/include/asm/memtype.h index 9ca760e430b9..d00e0be854d4 100644 --- a/arch/x86/include/asm/memtype.h +++ b/arch/x86/include/asm/memtype.h @@ -25,6 +25,8 @@ extern void memtype_free_io(resource_size_t start, resour= ce_size_t end); extern bool pat_pfn_immune_to_uc_mtrr(unsigned long pfn); =20 bool x86_has_pat_wp(void); +bool x86_has_pat_wc(void); +bool x86_has_pat_uc_minus(void); enum page_cache_mode pgprot2cachemode(pgprot_t pgprot); =20 #endif /* _ASM_X86_MEMTYPE_H */ diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index f3fd5928bcbb..a5742268dec1 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -94,7 +94,7 @@ int pcibios_set_irq_routing(struct pci_dev *dev, int pin,= int irq); =20 =20 #define HAVE_PCI_MMAP -#define arch_can_pci_mmap_wc() pat_enabled() +#define arch_can_pci_mmap_wc() x86_has_pat_wc() #define ARCH_GENERIC_PCI_MMAP_RESOURCE =20 #ifdef CONFIG_PCI diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 71e182ebced3..b6431f714dc2 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -77,12 +77,31 @@ static uint8_t __pte2cachemode_tbl[8] =3D { [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =3D _PAGE_CACHE_MODE_UC, }; =20 -/* Check that the write-protect PAT entry is set for write-protect */ +static bool x86_has_pat_mode(unsigned int mode) +{ + return __pte2cachemode_tbl[__cachemode2pte_tbl[mode]] =3D=3D mode; +} + +/* Check that PAT supports write-protect */ bool x86_has_pat_wp(void) { - return __pte2cachemode_tbl[__cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]] =3D= =3D - _PAGE_CACHE_MODE_WP; + return x86_has_pat_mode(_PAGE_CACHE_MODE_WP); +} +EXPORT_SYMBOL_GPL(x86_has_pat_wp); + +/* Check that PAT supports WC */ +bool x86_has_pat_wc(void) +{ + return x86_has_pat_mode(_PAGE_CACHE_MODE_WC); +} +EXPORT_SYMBOL_GPL(x86_has_pat_wc); + +/* Check that PAT supports UC- */ +bool x86_has_pat_uc_minus(void) +{ + return x86_has_pat_mode(_PAGE_CACHE_MODE_UC_MINUS); } +EXPORT_SYMBOL_GPL(x86_has_pat_uc_minus); =20 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i91= 5/gem/i915_gem_mman.c index 0c5c43852e24..f43ecf3f63eb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -76,7 +76,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, if (args->flags & ~(I915_MMAP_WC)) return -EINVAL; =20 - if (args->flags & I915_MMAP_WC && !pat_enabled()) + if (args->flags & I915_MMAP_WC && !x86_has_pat_wc()) return -ENODEV; =20 obj =3D i915_gem_object_lookup(file, args->handle); @@ -757,7 +757,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file, =20 if (HAS_LMEM(to_i915(dev))) mmap_type =3D I915_MMAP_TYPE_FIXED; - else if (pat_enabled()) + else if (x86_has_pat_wc()) mmap_type =3D I915_MMAP_TYPE_WC; else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt)) return -ENODEV; @@ -813,7 +813,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void= *data, break; =20 case I915_MMAP_OFFSET_WC: - if (!pat_enabled()) + if (!x86_has_pat_wc()) return -ENODEV; type =3D I915_MMAP_TYPE_WC; break; @@ -823,7 +823,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void= *data, break; =20 case I915_MMAP_OFFSET_UC: - if (!pat_enabled()) + if (!x86_has_pat_uc_minus()) return -ENODEV; type =3D I915_MMAP_TYPE_UC; break; --=20 2.35.3 From nobody Sun May 10 13:25:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2557C433EF for ; Wed, 13 Jul 2022 10:52:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234846AbiGMKwQ (ORCPT ); Wed, 13 Jul 2022 06:52:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbiGMKwO (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 230ec83d4299b30c51a1c133b4f2a669972cc08a Gitweb: https://git.kernel.org/tip/230ec83d4299b30c51a1c133b4f2a6699= 72cc08a Author: Juergen Gross AuthorDate: Fri, 08 Jul 2022 15:14:56 +02:00 Committer: Borislav Petkov CommitterDate: Wed, 13 Jul 2022 12:44:04 +02:00 x86/pat: Fix x86_has_pat_wp() x86_has_pat_wp() is using a wrong test, as it relies on the normal PAT configuration used by the kernel. In case the PAT MSR has been setup by another entity (e.g. Xen hypervisor) it might return false even if the PAT configuration is allowing WP mappings. This due to the fact that when running as Xen PV guest the PAT MSR is setup by the hypervisor and cannot be changed by the guest. This results in the WP related entry to be at a different position when running as Xen PV guest compared to the bare metal or fully virtualized case. The correct way to test for WP support is: 1. Get the PTE protection bits needed to select WP mode by reading __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP] (depending on the PAT MSR setting this might return protection bits for a stronger mode, e.g. UC-) 2. Translate those bits back into the real cache mode selected by those PTE bits by reading __pte2cachemode_tbl[__pte2cm_idx(prot)] 3. Test for the cache mode to be _PAGE_CACHE_MODE_WP Fixes: f88a68facd9a ("x86/mm: Extend early_memremap() support with addition= al attrs") Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov Cc: # 4.14 Link: https://lore.kernel.org/r/20220503132207.17234-1-jgross@suse.com --- arch/x86/mm/init.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index d8cfce2..57ba550 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -77,10 +77,20 @@ static uint8_t __pte2cachemode_tbl[8] =3D { [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =3D _PAGE_CACHE_MODE_UC, }; =20 -/* Check that the write-protect PAT entry is set for write-protect */ +/* + * Check that the write-protect PAT entry is set for write-protect. + * To do this without making assumptions how PAT has been set up (Xen has + * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache + * mode via the __cachemode2pte_tbl[] into protection bits (those protecti= on + * bits will select a cache mode of WP or better), and then translate the + * protection bits back into the cache mode using __pte2cm_idx() and the + * __pte2cachemode_tbl[] array. This will return the really used cache mod= e. + */ bool x86_has_pat_wp(void) { - return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] =3D=3D _PAGE_CACHE_MODE_W= P; + uint16_t prot =3D __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; + + return __pte2cachemode_tbl[__pte2cm_idx(prot)] =3D=3D _PAGE_CACHE_MODE_WP; } =20 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) From nobody Sun May 10 13:25:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02AE8C43334 for ; Wed, 13 Jul 2022 10:45:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235695AbiGMKpQ (ORCPT ); Wed, 13 Jul 2022 06:45:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235223AbiGMKpM (ORCPT ); Wed, 13 Jul 2022 06:45:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C63B9F990A; Wed, 13 Jul 2022 03:45:10 -0700 (PDT) Date: Wed, 13 Jul 2022 10:45:06 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657709108; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1/THw7b/dbCSKOAhofrOGXHOh63A6XAgjMRnWLsvrJA=; b=SWRHQGrFhvX1JSx0tpSAfdznl8nLJM/Pt/acFI3bc7rikKSU/F+ZuCRKdi80iHrrIBYtb2 Xv7x07Ck9C3SDJDOw9pI6n0NixRsuyhj/1Q4OcGNvy2WGRvE9IG/BiL2KR2TNJu5doCFLb sgAL7vj37zTlfO3ouUt7WWNLKVosqWfs4IcDXOrzYftqRZ2wUpkUAHdf6U/88GL6BtrzEO +gXwcgdHB62VCoZbfMjaFCFyS9U5vK7f5EQXMLsxWz+sM7fe67qQipqEcC3AXOQgoM8ajc PcFWA2TeKe2/JhJAoxXN6hDspUNnQgDaOrPY6CrwpGCl44XMt26e5cR07mzHpg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657709108; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1/THw7b/dbCSKOAhofrOGXHOh63A6XAgjMRnWLsvrJA=; b=rT44xZSnfADOpOp06QXPTXhS17NuL63Tm7ajRHypv8VKr+jXQR6qTZnDnW/bRrSY5po16y wuWaIqr+umZBkDDQ== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/pat: Fix x86_has_pat_wp() Cc: Juergen Gross , Borislav Petkov , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220503132207.17234-1-jgross@suse.com> References: <20220503132207.17234-1-jgross@suse.com> MIME-Version: 1.0 Message-ID: <165770910660.15455.10226651626540518739.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: f0592491eba2e42cc84d7831750b84cfc0150dde Gitweb: https://git.kernel.org/tip/f0592491eba2e42cc84d7831750b84cfc= 0150dde Author: Juergen Gross AuthorDate: Fri, 08 Jul 2022 15:14:56 +02:00 Committer: Borislav Petkov CommitterDate: Wed, 13 Jul 2022 12:21:03 +02:00 x86/pat: Fix x86_has_pat_wp() x86_has_pat_wp() is using a wrong test, as it relies on the normal PAT configuration used by the kernel. In case the PAT MSR has been setup by another entity (e.g. Xen hypervisor) it might return false even if the PAT configuration is allowing WP mappings. This due to the fact that when running as Xen PV guest the PAT MSR is setup by the hypervisor and cannot be changed by the guest. This results in the WP related entry to be at a different position when running as Xen PV guest compared to the bare metal or fully virtualized case. The correct way to test for WP support is: 1. Get the PTE protection bits needed to select WP mode by reading __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP] (depending on the PAT MSR setting this might return protection bits for a stronger mode, e.g. UC-) 2. Translate those bits back into the real cache mode selected by those PTE bits by reading __pte2cachemode_tbl[__pte2cm_idx(prot)] 3. Test for the cache mode to be _PAGE_CACHE_MODE_WP Fixes: f88a68facd9a ("x86/mm: Extend early_memremap() support with addition= al attrs") Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov Cc: # 4.14 Link: https://lore.kernel.org/r/20220503132207.17234-1-jgross@suse.com --- arch/x86/mm/init.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index d8cfce2..57ba550 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -77,10 +77,20 @@ static uint8_t __pte2cachemode_tbl[8] =3D { [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =3D _PAGE_CACHE_MODE_UC, }; =20 -/* Check that the write-protect PAT entry is set for write-protect */ +/* + * Check that the write-protect PAT entry is set for write-protect. + * To do this without making assumptions how PAT has been set up (Xen has + * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache + * mode via the __cachemode2pte_tbl[] into protection bits (those protecti= on + * bits will select a cache mode of WP or better), and then translate the + * protection bits back into the cache mode using __pte2cm_idx() and the + * __pte2cachemode_tbl[] array. This will return the really used cache mod= e. + */ bool x86_has_pat_wp(void) { - return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] =3D=3D _PAGE_CACHE_MODE_W= P; + uint16_t prot =3D __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; + + return __pte2cachemode_tbl[__pte2cm_idx(prot)] =3D=3D _PAGE_CACHE_MODE_WP; } =20 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) From nobody Sun May 10 13:25:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECD2C43334 for ; Mon, 11 Jul 2022 10:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbiGKKgk (ORCPT ); Mon, 11 Jul 2022 06:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229680AbiGKKgR (ORCPT ); Mon, 11 Jul 2022 06:36:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D54ADC1BD; Mon, 11 Jul 2022 02:46:40 -0700 (PDT) Date: Mon, 11 Jul 2022 09:46:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657532798; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZLMKvNlLuZyHt1XbXuDEYOvJvwJl6HGEaIuqT7eYV64=; b=4gandr0iHmpgVnfH1palqXTkSxKGcN12aR4K1CyTNtSGaffyCb+dWp7K8wk0vpTt+xJoyx rXKcRn0N2lUF23d/YUqsCiprvXThwDYU1WGY6lhIBD0A1i9UUSz0oMJ8cvpk25nDgu2kRA zkOVt8z3It5ksiJ/P6cL5wVXKPXJd3zA52DVBlZvXHAuXr38ZXslGvMNSMlxnhSGs5Zu2P wYIM+NA2FhU32A+q5gV/mLWcgsDnjvwra1c9tMRXPQ7GlMk5qrwaXpsQN0U2q/JksD/GY5 BhezqHTLXDaHhPt2+MZUk5UKaDogpbeSzq132OA8d35Jk76uE75Lfz+IW4ZUzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657532798; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZLMKvNlLuZyHt1XbXuDEYOvJvwJl6HGEaIuqT7eYV64=; b=RF99lBPVxYAunLo6oCARmlvWP/D0ksFo3M2Af/xw810Muw767HmtHXRvRFeItLgWBYqID3 0iULR2jC/7TQrJDw== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/pat: Fix x86_has_pat_wp() Cc: Juergen Gross , Borislav Petkov , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220503132207.17234-1-jgross@suse.com> References: <20220503132207.17234-1-jgross@suse.com> MIME-Version: 1.0 Message-ID: <165753279712.15455.2555694789382546026.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: da4600c76da7d787db04ce059b1f176da8a8d375 Gitweb: https://git.kernel.org/tip/da4600c76da7d787db04ce059b1f176da= 8a8d375 Author: Juergen Gross AuthorDate: Fri, 08 Jul 2022 15:14:56 +02:00 Committer: Borislav Petkov CommitterDate: Mon, 11 Jul 2022 11:37:03 +02:00 x86/pat: Fix x86_has_pat_wp() x86_has_pat_wp() is using a wrong test, as it relies on the normal PAT configuration used by the kernel. In case the PAT MSR has been setup by another entity (e.g. Xen hypervisor) it might return false even if the PAT configuration is allowing WP mappings. This due to the fact that when running as Xen PV guest the PAT MSR is setup by the hypervisor and cannot be changed by the guest. This results in the WP related entry to be at a different position when running as Xen PV guest compared to the bare metal or fully virtualized case. The correct way to test for WP support is: 1. Get the PTE protection bits needed to select WP mode by reading __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP] (depending on the PAT MSR setting this might return protection bits for a stronger mode, e.g. UC-) 2. Translate those bits back into the real cache mode selected by those PTE bits by reading __pte2cachemode_tbl[__pte2cm_idx(prot)] 3. Test for the cache mode to be _PAGE_CACHE_MODE_WP Fixes: f88a68facd9a ("x86/mm: Extend early_memremap() support with addition= al attrs") Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov Cc: # 4.14 Link: https://lore.kernel.org/r/20220503132207.17234-1-jgross@suse.com --- arch/x86/mm/init.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index d8cfce2..57ba550 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -77,10 +77,20 @@ static uint8_t __pte2cachemode_tbl[8] =3D { [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] =3D _PAGE_CACHE_MODE_UC, }; =20 -/* Check that the write-protect PAT entry is set for write-protect */ +/* + * Check that the write-protect PAT entry is set for write-protect. + * To do this without making assumptions how PAT has been set up (Xen has + * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache + * mode via the __cachemode2pte_tbl[] into protection bits (those protecti= on + * bits will select a cache mode of WP or better), and then translate the + * protection bits back into the cache mode using __pte2cm_idx() and the + * __pte2cachemode_tbl[] array. This will return the really used cache mod= e. + */ bool x86_has_pat_wp(void) { - return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] =3D=3D _PAGE_CACHE_MODE_W= P; + uint16_t prot =3D __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; + + return __pte2cachemode_tbl[__pte2cm_idx(prot)] =3D=3D _PAGE_CACHE_MODE_WP; } =20 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)