From nobody Sun May 10 13:30:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73EA5C433EF for ; Tue, 3 May 2022 10:57:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234485AbiECLBI (ORCPT ); Tue, 3 May 2022 07:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234581AbiECLAH (ORCPT ); Tue, 3 May 2022 07:00:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC6031C907; Tue, 3 May 2022 03:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651575377; x=1683111377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=JMfILJt9Qdwbtxcn7LDS0ssDPoXBmd8C5LPlUEheFFI=; b=e/u0b6GBiWe+LQu2FlM8D7uNCEvtZfbonoQh2ZghsEa2BX7gWYHPwOUR FXGiX0gY/oXbAsIpuBKUZT5H3G/gsFN4oY6WOXXPds6oiWbTf7PWAN3eH co81BCzz+PlaHrYO7X6W8QblyqIYwZCh/VXUPqH5dTNx/EJtirCMk1117 aoi7bwOp4/0g0/0mXWLxYjcY6CIWy1tVRghGNYgi+spjWdwoRMKyEz4Uz a5ruJgO9DEonA1mzoFUKCUp7Cjbw0jPaehCRPi86GRJw4c7HJyICGXigX ZPIQGK0gSVkitAYMxi27ONkjibWBiFXEkMn9RSR/QVNuNSFs0PFMCdR5/ A==; X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="162535319" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2022 03:56:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 3 May 2022 03:56:17 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 3 May 2022 03:56:12 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH 1/4] dt-bindings: mfd: atmel,flexcom: Convert to json-schema Date: Tue, 3 May 2022 16:25:25 +0530 Message-ID: <20220503105528.12824-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> References: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 68 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ----------------- 2 files changed, 68 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Doc= umentation/devicetree/bindings/mfd/atmel,flexcom.yaml new file mode 100644 index 000000000000..62dea9b891d8 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device tree bindings for Atmel Flexcom (Flexible Serial Communicati= on Unit) + +maintainers: + - Rob Herring + +description: | + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + enum: + - atmel,sama5d2-flexcom + + reg: + minItems: 1 + items: + - description: Flexcom registers + + clocks: + maxItems: 1 + + "#address-cells": true + + "#size-cells": true + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + minItems: 3 + maxItems: 3 + + atmel,flexcom-mode: + description: + One of the values. UART, I2C, SPI. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + flx0: flexcom@f8034000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8034000 0x200>; + clocks =3D <&flx0_clk>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8034000 0x800>; + atmel,flexcom-mode =3D <2>; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Docu= mentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 692300117c64..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Un= it) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is ch= osen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as on= e for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible =3D "atmel,sama5d2-flexcom"; - reg =3D <0xf8034000 0x200>; - clocks =3D <&flx0_clk>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0x0 0xf8034000 0x800>; - atmel,flexcom-mode =3D <2>; - - spi@400 { - compatible =3D "atmel,at91rm9200-spi"; - reg =3D <0x400 0x200>; - interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_flx0_default>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&flx0_clk>; - clock-names =3D "spi_clk"; - atmel,fifo-size =3D <32>; - - mtd_dataflash@0 { - compatible =3D "atmel,at25f512b"; - reg =3D <0>; - spi-max-frequency =3D <20000000>; - }; - }; -}; --=20 2.17.1 From nobody Sun May 10 13:30:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA07C433EF for ; Tue, 3 May 2022 10:57:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234417AbiECLAy (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="162535325" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2022 03:56:23 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 3 May 2022 03:56:23 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 3 May 2022 03:56:19 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH 2/4] dt-bindings: mfd: atmel,flexcom: Add lan966 compatible string and mux properties Date: Tue, 3 May 2022 16:25:26 +0530 Message-ID: <20220503105528.12824-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> References: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add lan966 flexcom compatible string and flexcom mux device tree properties Signed-off-by: Kavyasree Kotagiri --- .../devicetree/bindings/mfd/atmel,flexcom.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Doc= umentation/devicetree/bindings/mfd/atmel,flexcom.yaml index 62dea9b891d8..3e056857c44a 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan966-flexcom =20 reg: minItems: 1 @@ -45,6 +46,19 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] =20 + # The following optional mux properties are only for lan966 flexcoms + mux-controls: + minItems: 1 + description: Phandle to the mux controller to map flexcom chip-select + to flexcom shared pin. + + mux-control-names: + description: String to label the mux controller. + minItems: 1 + items: + - const: cs0 + - const: cs1 + required: - compatible - reg @@ -64,5 +78,7 @@ examples: #size-cells =3D <1>; ranges =3D <0x0 0xf8034000 0x800>; atmel,flexcom-mode =3D <2>; + mux-controls =3D <&mux 0>; + mux-control-names =3D "cs0"; }; ... --=20 2.17.1 From nobody Sun May 10 13:30:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6F89C433F5 for ; Tue, 3 May 2022 10:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234717AbiECLAg (ORCPT ); Tue, 3 May 2022 07:00:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234417AbiECLAY (ORCPT ); Tue, 3 May 2022 07:00:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11174275F9; Tue, 3 May 2022 03:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651575391; x=1683111391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=SRrXglg6r6VWu9S1ahzrarbkehQWcyMubV3bZWXG/sk=; b=n9x2ClDZ1kLDchFN9S+gak5/ooRIOhAV0No3vljj/Y0H4JqP3JXsvgrA F+HCVpEoNrnXMOyju5N7ugE7uxff6xsLWrApPXU8krft5roHo1JIW9rBo rxTm9SUmcOcOCTOlYCAzESNSiP5tyZGGyAu7ySkVl2y7uaePw0qD13/mE Yv+X425EceYxqcIgfL3DmarbiXlx+5yDwocAMn2GxKgl/HSJKbyS1dRnt bI3J1q/bPu5ypdxaE75bylMtiDZPV6lE54tVtTgeAOMMXI9GSFpy73mlZ kfrnDxmX3V9C7zPvoe4tfGG6X0Oy6JtwrvwdeJq8d/IAWF85shOyToSCK w==; X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="162127862" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2022 03:56:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 3 May 2022 03:56:30 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 3 May 2022 03:56:25 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH 3/4] dt-bindings: mux: Add lan966 flexcom mux controller Date: Tue, 3 May 2022 16:25:27 +0530 Message-ID: <20220503105528.12824-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> References: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds DT bindings documentation for lan966 flexcom mux controller. Signed-off-by: Kavyasree Kotagiri --- .../mux/microchip,lan966-flx-mux.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,lan966-= flx-mux.yaml diff --git a/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux= .yaml b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml new file mode 100644 index 000000000000..8b20f531781a --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,lan966-flx-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: microchip Lan966 Flexcom multiplexer bindings + +maintainers: + - Kavyasree Kotagiri + +description: |+ + The Microchip Lan966 have 5 Flexcoms. Each flexcom has 2 chip-selects + when operating in USART and SPI modes. + Each chip select of each flexcom can be mapped to 21 flexcom shared pins. + Define register offset and pin number to map a flexcom chip-select + to flexcom shared pin. + +properties: + compatible: + enum: + - microchip,lan966-flx-mux + + reg: + maxItems: 1 + + '#mux-control-cells': + const: 1 + + mux-offset-pin: + description: an array of register offset and flexcom shared pin(0-20). + +required: + - compatible + - '#mux-control-cells' + - mux-offset-pin + +additionalProperties: false + +examples: + - | + mux: mux-controller@e2004168 { + compatible =3D "microchip,lan966-flx-mux"; + reg =3D <0xe2004168 0x8>; + #mux-control-cells =3D <1>; + mux-offset-pin =3D + <0x18 9>; /* 0: flx3 cs0 offset, pin-9 */ + }; + + flx3 { + atmel,flexcom-mode =3D <2>; + mux-controls =3D <&mux 0>; + mux-control-names =3D "cs0"; + }; +... --=20 2.17.1 From nobody Sun May 10 13:30:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EF3AC433F5 for ; Tue, 3 May 2022 10:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbiECLAp (ORCPT ); Tue, 3 May 2022 07:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234642AbiECLAZ (ORCPT ); Tue, 3 May 2022 07:00:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D409B33374; Tue, 3 May 2022 03:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651575404; x=1683111404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PMOy70RBNnBmgt8xSvufyb66sxT3XFCpnTYpkreXFjM=; b=moQ/4bz49L+DRDwRlPY/aU6VmgfgfcoHdBVzoyYC4ufHSuA9IzmLkyJW 7znKrylz4+EUxfUbGSyPUIDkeOW1qvCGLUulb83p0nlzwgzBugFR9yjPZ iCMU8iVrDGEhxvvRkxZmvppD8AMKGKmNLxXVdsQwUnp5gW6SmbYkIpzwt u/bN/A3gf1APOGUCuXlhq9mMWsiKEj+7ZFD8W2OZLlsK5JaMlJlc3LfKf RxjEUtOt5fJivA7KzqDpwa4DM81xGQgfOziNHR9AciQK9VV3b95TW6jOG W1gvrKK9RqOC4oFGhiR6j+XJnYqRl44Oo7aQydu+OH6NgPwJupy8LMuCj w==; X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="171751051" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 May 2022 03:56:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 3 May 2022 03:56:44 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 3 May 2022 03:56:39 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH 4/4] mux: lan966: Add support for flexcom mux controller Date: Tue, 3 May 2022 16:25:28 +0530 Message-ID: <20220503105528.12824-5-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> References: <20220503105528.12824-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAN966 SoC have 5 flexcoms. Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri Reported-by: kernel test robot --- arch/arm/mach-at91/Kconfig | 2 + drivers/mfd/atmel-flexcom.c | 55 ++++++++++++++++- drivers/mux/Kconfig | 12 ++++ drivers/mux/Makefile | 2 + drivers/mux/lan966-flx.c | 116 ++++++++++++++++++++++++++++++++++++ 5 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 drivers/mux/lan966-flx.c diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 279810381256..26fb0f4e1b79 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -74,6 +74,8 @@ config SOC_LAN966 select DW_APB_TIMER_OF select ARM_GIC select MEMORY + select MULTIPLEXER + select MUX_LAN966 help This enables support for ARMv7 based Microchip LAN966 SoC family. =20 diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 33caa4fba6af..cf3dac383f30 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 /* I/O register offsets */ #define FLEX_MR 0x0 /* Mode Register */ @@ -28,6 +29,10 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) =20 +struct atmel_flex_caps { + bool has_flx_mux; +}; + struct atmel_flexcom { void __iomem *base; u32 opmode; @@ -37,6 +42,7 @@ struct atmel_flexcom { static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +82,60 @@ static int atmel_flexcom_probe(struct platform_device *= pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); =20 + caps =3D of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + return -EINVAL; + } + + /* Flexcom Mux */ + if (caps->has_flx_mux && of_property_read_bool(np, "mux-controls")) { + struct mux_control *flx_mux; + struct of_phandle_args args; + int i, count; + + flx_mux =3D devm_mux_control_get(&pdev->dev, NULL); + if (IS_ERR(flx_mux)) + return PTR_ERR(flx_mux); + + count =3D of_property_count_strings(np, "mux-control-names"); + for (i =3D 0; i < count; i++) { + err =3D of_parse_phandle_with_fixed_args(np, "mux-controls", 1, i, &arg= s); + if (err) + break; + + err =3D mux_control_select(flx_mux, args.args[0]); + if (!err) { + mux_control_deselect(flx_mux); + } else { + dev_err(&pdev->dev, "Failed to select FLEXCOM mux\n"); + return err; + } + } + } + clk_disable_unprepare(ddata->clk); =20 return devm_of_platform_populate(&pdev->dev); } =20 +static const struct atmel_flex_caps atmel_flexcom_caps =3D {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps =3D { + .has_flx_mux =3D true, +}; + static const struct of_device_id atmel_flexcom_of_match[] =3D { - { .compatible =3D "atmel,sama5d2-flexcom" }, + { + .compatible =3D "atmel,sama5d2-flexcom", + .data =3D &atmel_flexcom_caps, + }, + + { + .compatible =3D "microchip,lan966-flexcom", + .data =3D &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index e5c571fd232c..ea09f474bc2f 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -45,6 +45,18 @@ config MUX_GPIO To compile the driver as a module, choose M here: the module will be called mux-gpio. =20 +config MUX_LAN966 + tristate "LAN966 Flexcom multiplexer" + depends on OF || COMPILE_TEST + help + Lan966 Flexcom Multiplexer controller. + + The driver supports mapping 2 chip-selects of each of the lan966 + flexcoms to 21 flexcom shared pins. + + To compile the driver as a module, choose M here: the module will + be called mux-lan966. + config MUX_MMIO tristate "MMIO/Regmap register bitfield-controlled Multiplexer" depends on OF || COMPILE_TEST diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index 6e9fa47daf56..53a9840d96fa 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -7,10 +7,12 @@ mux-core-objs :=3D core.o mux-adg792a-objs :=3D adg792a.o mux-adgs1408-objs :=3D adgs1408.o mux-gpio-objs :=3D gpio.o +mux-lan966-objs :=3D lan966-flx.o mux-mmio-objs :=3D mmio.o =20 obj-$(CONFIG_MULTIPLEXER) +=3D mux-core.o obj-$(CONFIG_MUX_ADG792A) +=3D mux-adg792a.o obj-$(CONFIG_MUX_ADGS1408) +=3D mux-adgs1408.o obj-$(CONFIG_MUX_GPIO) +=3D mux-gpio.o +obj-$(CONFIG_MUX_LAN966) +=3D mux-lan966.o obj-$(CONFIG_MUX_MMIO) +=3D mux-mmio.o diff --git a/drivers/mux/lan966-flx.c b/drivers/mux/lan966-flx.c new file mode 100644 index 000000000000..5d078a159fcd --- /dev/null +++ b/drivers/mux/lan966-flx.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LAN966 Flexcom MUX driver + * + * Copyright (c) Microchip Inc. + * + * Author: Kavyasree Kotagiri + */ + +#include +#include +#include +#include +#include +#include +#include + +#define FLEX_SHRD_MASK 0x1FFFFF +#define LAN966_MAX_CS 21 + +static void __iomem *flx_shared_base; +struct mux_lan966x { + u32 offset; + u32 ss_pin; +}; + +static int mux_lan966x_set(struct mux_control *mux, int state) +{ + struct mux_lan966x *mux_lan966x =3D mux_chip_priv(mux->chip); + u32 val; + + val =3D ~(1 << mux_lan966x[state].ss_pin) & FLEX_SHRD_MASK; + writel(val, flx_shared_base + mux_lan966x[state].offset); + + return 0; +} + +static const struct mux_control_ops mux_lan966x_ops =3D { + .set =3D mux_lan966x_set, +}; + +static const struct of_device_id mux_lan966x_dt_ids[] =3D { + { .compatible =3D "microchip,lan966-flx-mux", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mux_lan966x_dt_ids); + +static int mux_lan966x_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct mux_lan966x *mux_lan966x; + struct mux_chip *mux_chip; + int ret, num_fields, i; + + ret =3D of_property_count_u32_elems(np, "mux-offset-pin"); + if (ret =3D=3D 0 || ret % 2) + ret =3D -EINVAL; + if (ret < 0) + return dev_err_probe(dev, ret, + "mux-offset-pin property missing or invalid"); + num_fields =3D ret / 2; + + mux_chip =3D devm_mux_chip_alloc(dev, num_fields, sizeof(*mux_lan966x)); + if (IS_ERR(mux_chip)) + return dev_err_probe(dev, PTR_ERR(mux_chip), + "failed to allocate mux_chips\n"); + + mux_lan966x =3D mux_chip_priv(mux_chip); + + flx_shared_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(flx_shared_base)) + return dev_err_probe(dev, PTR_ERR(flx_shared_base), + "failed to get flexcom shared base address\n"); + + for (i =3D 0; i < num_fields; i++) { + struct mux_control *mux =3D &mux_chip->mux[i]; + u32 offset, shared_pin; + + ret =3D of_property_read_u32_index(np, "mux-offset-pin", + 2 * i, &offset); + if (ret =3D=3D 0) + ret =3D of_property_read_u32_index(np, "mux-offset-pin", + 2 * i + 1, + &shared_pin); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to read mux-offset-pin property: %d", i); + + if (shared_pin >=3D LAN966_MAX_CS) + return -EINVAL; + + mux_lan966x[i].offset =3D offset; + mux_lan966x[i].ss_pin =3D shared_pin; + + mux->states =3D LAN966_MAX_CS; + } + + mux_chip->ops =3D &mux_lan966x_ops; + + ret =3D devm_mux_chip_register(dev, mux_chip); + if (ret < 0) + return ret; + + return 0; +} + +static struct platform_driver mux_lan966x_driver =3D { + .driver =3D { + .name =3D "lan966-mux", + .of_match_table =3D of_match_ptr(mux_lan966x_dt_ids), + }, + .probe =3D mux_lan966x_probe, +}; + +module_platform_driver(mux_lan966x_driver); --=20 2.17.1