From nobody Sun Sep 22 05:42:56 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C753BC433EF for ; Tue, 3 May 2022 10:55:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234515AbiECK6n (ORCPT ); Tue, 3 May 2022 06:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234517AbiECK6f (ORCPT ); Tue, 3 May 2022 06:58:35 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B669B387BA; Tue, 3 May 2022 03:54:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 75BBB1F43E42 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651575284; bh=Vzt5rJ5w7RADVz/xg7c0ik/5e8mPzC+52IMY2R0fGcU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AXAvYxaJ2WqoLiScU2zK8GtNyfvNOCc0H86ip/W7ijj6NBN0iT939GlVAah0ZYQJI U26VT4lIyEGKJ9VUNRvp1niEdNeY7wqj1NW9hyh0F+W5U5tEx6biJDA0bD1Ekq6Upr 8/MgV1J2CATa4EWfJCu9Qm4u+EI5J7uY0H8TtQ4RCSZn46XfIGSbKCYBl0QVNYX0AS 0ARqd2bjFYN1iSf7iZcWdrBpQf1XP6nvmSK9zSR0n5p4VU5cdFxeptzSFElJVSeNOi LHhgSYZEs6lUIfyXTwksuTR6SuzuEC0E2UArhM3kgzpd8e73MpysVLwui+/pXOtWBA 0TguOZty6Cgpg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, chun-jie.chen@mediatek.com, angelogioacchino.delregno@collabora.com, weiyi.lu@mediatek.com, mbrugger@suse.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, nfraprado@collabora.com Subject: [PATCH 2/2] soc: mediatek: pm-domains: Add support for Helio X10 MT6795 Date: Tue, 3 May 2022 12:54:36 +0200 Message-Id: <20220503105436.54901-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503105436.54901-1-angelogioacchino.delregno@collabora.com> References: <20220503105436.54901-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pm-domains (mtcmos) data for MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt6795-pm-domains.h | 112 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 117 insertions(+) create mode 100644 drivers/soc/mediatek/mt6795-pm-domains.h diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediate= k/mt6795-pm-domains.h new file mode 100644 index 000000000000..ef07c9dfdd9b --- /dev/null +++ b/drivers/soc/mediatek/mt6795-pm-domains.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT6795 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt6795[] =3D { + [MT6795_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D PWR_STATUS_VDEC, + .ctl_offs =3D SPM_VDE_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + }, + [MT6795_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D SPM_VEN_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_ISP] =3D { + .name =3D "isp", + .sta_mask =3D PWR_STATUS_ISP, + .ctl_offs =3D SPM_ISP_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + }, + [MT6795_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D SPM_DIS_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_infracfg =3D { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), + }, + }, + [MT6795_POWER_DOMAIN_MJC] =3D { + .name =3D "mjc", + .sta_mask =3D BIT(20), + .ctl_offs =3D 0x298, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D SPM_AUDIO_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + }, + [MT6795_POWER_DOMAIN_MFG_ASYNC] =3D { + .name =3D "mfg_async", + .sta_mask =3D PWR_STATUS_MFG_ASYNC, + .ctl_offs =3D SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D 0, + }, + [MT6795_POWER_DOMAIN_MFG_2D] =3D { + .name =3D "mfg_2d", + .sta_mask =3D PWR_STATUS_MFG_2D, + .ctl_offs =3D SPM_MFG_2D_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + }, + [MT6795_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D SPM_MFG_PWR_CON, + .pwr_sta_offs =3D SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, + .sram_pdn_bits =3D GENMASK(13, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 16), + .bp_infracfg =3D { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + }, + }, +}; + +static const struct scpsys_soc_data mt6795_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt6795, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt6795), +}; + +#endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 5ced254b082b..4da53488c381 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -16,6 +16,7 @@ #include #include =20 +#include "mt6795-pm-domains.h" #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" @@ -555,6 +556,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsy= s) } =20 static const struct of_device_id scpsys_of_match[] =3D { + { + .compatible =3D "mediatek,mt6795-power-controller", + .data =3D &mt6795_scpsys_data, + }, { .compatible =3D "mediatek,mt8167-power-controller", .data =3D &mt8167_scpsys_data, --=20 2.35.1