From nobody Sun Sep 22 05:28:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75601C433F5 for ; Tue, 3 May 2022 09:40:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233772AbiECJnk (ORCPT ); Tue, 3 May 2022 05:43:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233554AbiECJmq (ORCPT ); Tue, 3 May 2022 05:42:46 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67A2536B6B; Tue, 3 May 2022 02:39:09 -0700 (PDT) X-UUID: 7a3d8b886ab8486b94f51888c6285369-20220503 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ef8dd6ac-2182-4702-b0c4-8ea5fd782b4d,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:95e4872f-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 7a3d8b886ab8486b94f51888c6285369-20220503 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 157331159; Tue, 03 May 2022 17:39:01 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 3 May 2022 17:39:00 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 May 2022 17:38:59 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 3 May 2022 17:38:59 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v6 09/16] clk: mediatek: reset: Change return type for clock reset register function Date: Tue, 3 May 2022 17:38:49 +0800 Message-ID: <20220503093856.22250-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220503093856.22250-1-rex-bc.chen@mediatek.com> References: <20220503093856.22250-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To deal with error handling, we change the function return type from void to int for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 15 +++++++++------ drivers/clk/mediatek/reset.h | 6 ++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 89e617ea6393..b9718f0f9d16 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -110,8 +110,8 @@ static int reset_xlate(struct reset_controller_dev *rcd= ev, return data->desc->rst_idx_map[reset_spec->args[0]]; } =20 -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc) +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc) { struct regmap *regmap; const struct reset_control_ops *rcops =3D NULL; @@ -120,7 +120,7 @@ void mtk_register_reset_controller(struct device_node *= np, =20 if (!desc) { pr_err("mtk clock reset desc is NULL\n"); - return; + return -EINVAL; } =20 switch (desc->version) { @@ -132,18 +132,18 @@ void mtk_register_reset_controller(struct device_node= *np, break; default: pr_err("Unknown reset version %d\n", desc->version); - return; + return -EINVAL; } =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return -EINVAL; } =20 data =3D kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return -ENOMEM; =20 data->desc =3D desc; data->regmap =3D regmap; @@ -163,7 +163,10 @@ void mtk_register_reset_controller(struct device_node = *np, if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); + return ret; } + + return 0; } =20 MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 47635d964c69..cc67934c69e2 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -56,8 +56,10 @@ struct mtk_clk_rst_data { * mtk_register_reset_controller - Register MediaTek clock reset controller * @np: Pointer to device node. * @desc: Constant pointer to description of clock reset. + * + * Return: 0 on success and errorno otherwise. */ -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc); +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc); =20 #endif /* __DRV_CLK_MTK_RESET_H */ --=20 2.18.0