From nobody Sun Sep 22 06:23:55 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F2B3C433EF for ; Tue, 3 May 2022 07:22:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232161AbiECHZt (ORCPT ); Tue, 3 May 2022 03:25:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232077AbiECHX0 (ORCPT ); Tue, 3 May 2022 03:23:26 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFF483A5F4; Tue, 3 May 2022 00:19:26 -0700 (PDT) X-UUID: 0112c0afcc7a455abc47a92f955fb830-20220503 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:0b93050f-e0cf-40d3-900d-ef5c73afc162,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:d1d64ac7-85ee-4ac1-ac05-bd3f1e72e732,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 0112c0afcc7a455abc47a92f955fb830-20220503 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 880158939; Tue, 03 May 2022 15:19:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 3 May 2022 15:19:18 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 May 2022 15:19:17 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , Matthias Brugger , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , Hsin-Yi Wang , , , , , , AngeloGioacchino Del Regno , , , , Subject: [PATCH v7 34/36] iommu/mediatek: Backup/restore regsiters for multi banks Date: Tue, 3 May 2022 15:14:25 +0800 Message-ID: <20220503071427.2285-35-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220503071427.2285-1-yong.wu@mediatek.com> References: <20220503071427.2285-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Each bank has some independent registers. thus backup/restore them for each a bank when suspend and resume. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 46 ++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 400dea33aea1..d3e8773b4c47 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -173,11 +173,12 @@ struct mtk_iommu_suspend_reg { u32 misc_ctrl; u32 dcm_dis; u32 ctrl_reg; - u32 int_control0; - u32 int_main_control; - u32 ivrp_paddr; u32 vld_pa_rng; u32 wr_len_ctrl; + + u32 int_control[MTK_IOMMU_BANK_MAX]; + u32 int_main_control[MTK_IOMMU_BANK_MAX]; + u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; }; =20 struct mtk_iommu_plat_data { @@ -1302,16 +1303,23 @@ static int __maybe_unused mtk_iommu_runtime_suspend= (struct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - void __iomem *base =3D data->bank[0].base; + void __iomem *base; + int i =3D 0; =20 + base =3D data->bank[i].base; reg->wr_len_ctrl =3D readl_relaxed(base + REG_MMU_WR_LEN_CTRL); reg->misc_ctrl =3D readl_relaxed(base + REG_MMU_MISC_CTRL); reg->dcm_dis =3D readl_relaxed(base + REG_MMU_DCM_DIS); reg->ctrl_reg =3D readl_relaxed(base + REG_MMU_CTRL_REG); - reg->int_control0 =3D readl_relaxed(base + REG_MMU_INT_CONTROL0); - reg->int_main_control =3D readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); - reg->ivrp_paddr =3D readl_relaxed(base + REG_MMU_IVRP_PADDR); reg->vld_pa_rng =3D readl_relaxed(base + REG_MMU_VLD_PA_RNG); + do { + if (!data->plat_data->banks_enable[i]) + continue; + base =3D data->bank[i].base; + reg->int_control[i] =3D readl_relaxed(base + REG_MMU_INT_CONTROL0); + reg->int_main_control[i] =3D readl_relaxed(base + REG_MMU_INT_MAIN_CONTR= OL); + reg->ivrp_paddr[i] =3D readl_relaxed(base + REG_MMU_IVRP_PADDR); + } while (++i < data->plat_data->banks_num); clk_disable_unprepare(data->bclk); return 0; } @@ -1320,9 +1328,9 @@ static int __maybe_unused mtk_iommu_runtime_resume(st= ruct device *dev) { struct mtk_iommu_data *data =3D dev_get_drvdata(dev); struct mtk_iommu_suspend_reg *reg =3D &data->reg; - struct mtk_iommu_domain *m4u_dom =3D data->bank[0].m4u_dom; - void __iomem *base =3D data->bank[0].base; - int ret; + struct mtk_iommu_domain *m4u_dom; + void __iomem *base; + int ret, i =3D 0; =20 ret =3D clk_prepare_enable(data->bclk); if (ret) { @@ -1334,18 +1342,26 @@ static int __maybe_unused mtk_iommu_runtime_resume(= struct device *dev) * Uppon first resume, only enable the clk and return, since the values o= f the * registers are not yet set. */ - if (!m4u_dom) + if (!reg->wr_len_ctrl) return 0; =20 + base =3D data->bank[i].base; writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); - writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); - writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); - writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_P= T_BASE_ADDR); + do { + m4u_dom =3D data->bank[i].m4u_dom; + if (!data->plat_data->banks_enable[i] || !m4u_dom) + continue; + base =3D data->bank[i].base; + writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); + writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL= ); + writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, + base + REG_MMU_PT_BASE_ADDR); + } while (++i < data->plat_data->banks_num); =20 /* * Users may allocate dma buffer before they call pm_runtime_get, --=20 2.18.0