From nobody Sun Sep 22 07:51:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0A78C433F5 for ; Tue, 3 May 2022 07:18:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiECHWI (ORCPT ); Tue, 3 May 2022 03:22:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232101AbiECHVY (ORCPT ); Tue, 3 May 2022 03:21:24 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7E1275C2; Tue, 3 May 2022 00:17:50 -0700 (PDT) X-UUID: ef99227b3dee4f2e9ec9598419df0aa0-20220503 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:76422ba2-1682-48b4-a88f-9e9e464646c9,OB:60,L OB:20,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ha m,ACTION:release,TS:80 X-CID-INFO: VERSION:1.1.4,REQID:76422ba2-1682-48b4-a88f-9e9e464646c9,OB:60,LOB :20,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3 D,ACTION:quarantine,TS:80 X-CID-META: VersionHash:faefae9,CLOUDID:2ec54ac7-85ee-4ac1-ac05-bd3f1e72e732,C OID:d2f05428c351,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: ef99227b3dee4f2e9ec9598419df0aa0-20220503 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1931376981; Tue, 03 May 2022 15:17:35 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 3 May 2022 15:17:33 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 May 2022 15:17:32 +0800 From: Yong Wu To: Joerg Roedel , Rob Herring , "Matthias Brugger" , Will Deacon CC: Robin Murphy , Krzysztof Kozlowski , Tomasz Figa , , , , , , Hsin-Yi Wang , , , , , , "AngeloGioacchino Del Regno" , , , , Subject: [PATCH v7 20/36] iommu/mediatek: Add a PM_CLK_AO flag for infra iommu Date: Tue, 3 May 2022 15:14:11 +0800 Message-ID: <20220503071427.2285-21-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220503071427.2285-1-yong.wu@mediatek.com> References: <20220503071427.2285-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The power/clock of infra iommu is always on, and it doesn't have the device link with the master devices, then the infra iommu device's PM status is not active, thus we add A PM_CLK_AO flag for infra iommu. The tlb operation is a bit not clear here, there are 2 special cases. Comment them in the code. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0121d71c315f..cd89c109e8c4 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -130,6 +130,8 @@ #define MTK_IOMMU_TYPE_MM (0x0 << 13) #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) #define MTK_IOMMU_TYPE_MASK (0x3 << 13) +/* PM and clock always on. e.g. infra iommu */ +#define PM_CLK_AO BIT(15) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -235,13 +237,33 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned l= ong iova, size_t size, struct mtk_iommu_data *data) { struct list_head *head =3D data->hw_list; + bool check_pm_status; unsigned long flags; int ret; u32 tmp; =20 for_each_m4u(data, head) { - if (pm_runtime_get_if_in_use(data->dev) <=3D 0) - continue; + /* + * To avoid resume the iommu device frequently when the iommu device + * is not active, it doesn't always call pm_runtime_get here, then tlb + * flush depends on the tlb flush all in the runtime resume. + * + * There are 2 special cases: + * + * Case1: The iommu dev doesn't have power domain but has bclk. This case + * should also avoid the tlb flush while the dev is not active to mute + * the tlb timeout log. like mt8173. + * + * Case2: The power/clock of infra iommu is always on, and it doesn't + * have the device link with the master devices. This case should avoid + * the PM status check. + */ + check_pm_status =3D !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); + + if (check_pm_status) { + if (pm_runtime_get_if_in_use(data->dev) <=3D 0) + continue; + } =20 spin_lock_irqsave(&data->tlb_lock, flags); writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, @@ -268,7 +290,8 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned lon= g iova, size_t size, mtk_iommu_tlb_flush_all(data); } =20 - pm_runtime_put(data->dev); + if (check_pm_status) + pm_runtime_put(data->dev); } } =20 --=20 2.18.0