From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36225C433F5 for ; Tue, 3 May 2022 06:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229540AbiECGFn (ORCPT ); Tue, 3 May 2022 02:05:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229507AbiECGFm (ORCPT ); Tue, 3 May 2022 02:05:42 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC3A833352 for ; Mon, 2 May 2022 23:02:10 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id a11-20020a170902900b00b0015ebbae6dd9so25292plp.6 for ; Mon, 02 May 2022 23:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=t8sqG9N3bDSFcIV4nihap+Y9twMBMAx1j91yk1oqLR8=; b=fDfjA+1/0+LcqwDGcxHKZd8ionRfBRzNlkOTN7GRUfD8g3bhg8pDQ5uyFL8oq7q6Na EoyIu/iVkG0pujF0nu4inS7G6gI1qyWrLNt7VR+u977NM57eXHKDfc+HHstuIZ/YOlTO GDC+ESrL/7lSn7TicirueSi7FRTx9SrqRNpNOXTXE81cHJxUvheeDwap8zbAEewVk7Xw S2PH5S+5ZjTC3WxCod8/AhC56Ae2bRRJVtADxwVKVzmvIc3DU+qMsrZBlBycKcX9nxTb E7GoavZ31OG/uySeQKncbOYShr/2vP/MMsRpnPaocTB96ijBYhHMvKQGff29TkVMYTkX vPuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=t8sqG9N3bDSFcIV4nihap+Y9twMBMAx1j91yk1oqLR8=; b=Y0Ec+bouIw5EI4DeOi+Wfhc4Ce+mr+JC4F9YXZCrlFNsXKSbIxDO3fUI3rA7tLy5HW qAdTL8EAsRLJhyVtqf6ILmVJTg0SN7IgaoTSyJZH2PBLFCn0YVPD89cLkjwCFHjKpY/p Pe1kfjt7FUTv90BKCls2Xdre8WH3qEQhnVEJiFh0dGK5V6OcCUSmefIBhnswuy5a4ckO l5n0n26Nk+ce8g0rPVPnZe9kDDoFdXluY/xT0PW8ArpvQ837UFSSh8KZOSLxtP02L2tq uC7ZrnfzVgSAoGt229v8GCfpmNBDdTRjODLv1NXop6Jben9+k1vW73lml+NfoVomlABF wDkg== X-Gm-Message-State: AOAM533bSTbVKpdF23pLP/CKl0AGyVNaPGxekFSNSR8emRSUBTElRWx+ o9y+B61olQfgOzJclqPxoz84jKIr8FM= X-Google-Smtp-Source: ABdhPJz/UUNAbn5Z/ZnAPcvJcY0XAWJIASeAIpwVIjQ/WB9rW/6OA1St42zCrG6ilBD1/lLbFfGTrlWn5xg= X-Received: from oupton3.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:21eb]) (user=oupton job=sendgmr) by 2002:a63:6c42:0:b0:3ab:7c9c:1faf with SMTP id h63-20020a636c42000000b003ab7c9c1fafmr12960528pgc.518.1651557730161; Mon, 02 May 2022 23:02:10 -0700 (PDT) Date: Tue, 3 May 2022 06:01:59 +0000 In-Reply-To: <20220503060205.2823727-1-oupton@google.com> Message-Id: <20220503060205.2823727-2-oupton@google.com> Mime-Version: 1.0 References: <20220503060205.2823727-1-oupton@google.com> X-Mailer: git-send-email 2.36.0.464.gb9c8b46e94-goog Subject: [PATCH v4 1/7] KVM: arm64: Return a bool from emulate_cp() From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com, Oliver Upton Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM indicates success/failure in several ways, but generally an integer is used when conditionally bouncing to userspace is involved. That is not the case from emulate_cp(); just use a bool instead. No functional change intended. Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7b45c040cc27..36895c163eae 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2246,27 +2246,27 @@ static void perform_access(struct kvm_vcpu *vcpu, * @table: array of trap descriptors * @num: size of the trap descriptor array * - * Return 0 if the access has been handled, and -1 if not. + * Return true if the access has been handled, false if not. */ -static int emulate_cp(struct kvm_vcpu *vcpu, - struct sys_reg_params *params, - const struct sys_reg_desc *table, - size_t num) +static bool emulate_cp(struct kvm_vcpu *vcpu, + struct sys_reg_params *params, + const struct sys_reg_desc *table, + size_t num) { const struct sys_reg_desc *r; =20 if (!table) - return -1; /* Not handled */ + return false; /* Not handled */ =20 r =3D find_reg(params, table, num); =20 if (r) { perform_access(vcpu, params, r); - return 0; + return true; } =20 /* Not handled */ - return -1; + return false; } =20 static void unhandled_cp_access(struct kvm_vcpu *vcpu, @@ -2330,7 +2330,7 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, * potential register operation in the case of a read and return * with success. */ - if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { + if (emulate_cp(vcpu, ¶ms, global, nr_global)) { /* Split up the value between registers for the read side */ if (!params.is_write) { vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); @@ -2365,7 +2365,7 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, params.Op1 =3D (esr >> 14) & 0x7; params.Op2 =3D (esr >> 17) & 0x7; =20 - if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { + if (emulate_cp(vcpu, ¶ms, global, nr_global)) { if (!params.is_write) vcpu_set_reg(vcpu, Rt, params.regval); return 1; --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F99EC433F5 for ; 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charset="utf-8" emulate_sys_reg() returns 1 unconditionally, even though a a system register access can fail. Furthermore, kvm_handle_sys_reg() writes to Rt for every register read, regardless of if it actually succeeded. Though this pattern is safe (as params.regval is initialized with the current value of Rt) it is a bit ugly. Indicate failure if the register access could not be emulated and only write to Rt on success. Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 36895c163eae..f0a076e5cc1c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2401,7 +2401,14 @@ static bool is_imp_def_sys_reg(struct sys_reg_params= *params) return params->Op0 =3D=3D 3 && (params->CRn & 0b1011) =3D=3D 0b1011; } =20 -static int emulate_sys_reg(struct kvm_vcpu *vcpu, +/** + * emulate_sys_reg - Emulate a guest access to an AArch64 system register + * @vcpu: The VCPU pointer + * @params: Decoded system register parameters + * + * Return: true if the system register access was successful, false otherw= ise. + */ +static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params) { const struct sys_reg_desc *r; @@ -2410,7 +2417,10 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu, =20 if (likely(r)) { perform_access(vcpu, params, r); - } else if (is_imp_def_sys_reg(params)) { + return true; + } + + if (is_imp_def_sys_reg(params)) { kvm_inject_undefined(vcpu); } else { print_sys_reg_msg(params, @@ -2418,7 +2428,7 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); kvm_inject_undefined(vcpu); } - return 1; + return false; } =20 /** @@ -2446,18 +2456,18 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) struct sys_reg_params params; unsigned long esr =3D kvm_vcpu_get_esr(vcpu); int Rt =3D kvm_vcpu_sys_get_rt(vcpu); - int ret; =20 trace_kvm_handle_sys_reg(esr); =20 params =3D esr_sys64_to_params(esr); params.regval =3D vcpu_get_reg(vcpu, Rt); =20 - ret =3D emulate_sys_reg(vcpu, ¶ms); + if (!emulate_sys_reg(vcpu, ¶ms)) + return 1; =20 if (!params.is_write) vcpu_set_reg(vcpu, Rt, params.regval); - return ret; + return 1; } =20 /*************************************************************************= ***** --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 577D5C433F5 for ; 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charset="utf-8" KVM currently does not trap ID register accesses from an AArch32 EL1. This is painful for a couple of reasons. Certain unimplemented features are visible to AArch32 EL1, as we limit PMU to version 3 and the debug architecture to v8.0. Additionally, we attempt to paper over heterogeneous systems by using register values that are safe system-wide. All this hard work is completely sidestepped because KVM does not set TID3 for AArch32 guests. Fix up handling of CP15 feature registers by simply rerouting to their AArch64 aliases. Punt setting HCR_EL2.TID3 to a later change, as we need to fix up the oddball CP10 feature registers still. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 86 ++++++++++++++++++++++++++++++++------- arch/arm64/kvm/sys_regs.h | 7 ++++ 2 files changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f0a076e5cc1c..f403ea47b8a3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2344,34 +2344,73 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, return 1; } =20 +static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *= params); + +/** + * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access = where + * CRn=3D0, which corresponds to the AArch32 feature + * registers. + * @vcpu: the vCPU pointer + * @params: the system register access parameters. + * + * Our cp15 system register tables do not enumerate the AArch32 feature + * registers. Conveniently, our AArch64 table does, and the AArch32 system + * register encoding can be trivially remapped into the AArch64 for the fe= ature + * registers: Append op0=3D3, leaving op1, CRn, CRm, and op2 the same. + * + * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit + * System registers with (coproc=3D0b1111, CRn=3D=3Dc0)", read accesses fr= om this + * range are either UNKNOWN or RES0. Rerouting remains architectural as we + * treat undefined registers in this range as RAZ. + */ +static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu, + struct sys_reg_params *params) +{ + int Rt =3D kvm_vcpu_sys_get_rt(vcpu); + + /* Treat impossible writes to RO registers as UNDEFINED */ + if (params->is_write) { + unhandled_cp_access(vcpu, params); + return 1; + } + + params->Op0 =3D 3; + + /* + * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32. + * Avoid conflicting with future expansion of AArch64 feature registers + * and simply treat them as RAZ here. + */ + if (params->CRm > 3) + params->regval =3D 0; + else if (!emulate_sys_reg(vcpu, params)) + return 1; + + vcpu_set_reg(vcpu, Rt, params->regval); + return 1; +} + /** * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access * @vcpu: The VCPU pointer * @run: The kvm_run struct */ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, + struct sys_reg_params *params, const struct sys_reg_desc *global, size_t nr_global) { - struct sys_reg_params params; - u32 esr =3D kvm_vcpu_get_esr(vcpu); int Rt =3D kvm_vcpu_sys_get_rt(vcpu); =20 - params.CRm =3D (esr >> 1) & 0xf; - params.regval =3D vcpu_get_reg(vcpu, Rt); - params.is_write =3D ((esr & 1) =3D=3D 0); - params.CRn =3D (esr >> 10) & 0xf; - params.Op0 =3D 0; - params.Op1 =3D (esr >> 14) & 0x7; - params.Op2 =3D (esr >> 17) & 0x7; + params->regval =3D vcpu_get_reg(vcpu, Rt); =20 - if (emulate_cp(vcpu, ¶ms, global, nr_global)) { - if (!params.is_write) - vcpu_set_reg(vcpu, Rt, params.regval); + if (emulate_cp(vcpu, params, global, nr_global)) { + if (!params->is_write) + vcpu_set_reg(vcpu, Rt, params->regval); return 1; } =20 - unhandled_cp_access(vcpu, ¶ms); + unhandled_cp_access(vcpu, params); return 1; } =20 @@ -2382,7 +2421,20 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) =20 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) { - return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); + struct sys_reg_params params; + + params =3D esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); + + /* + * Certain AArch32 ID registers are handled by rerouting to the AArch64 + * system register table. Registers in the ID range where CRm=3D0 are + * excluded from this scheme as they do not trivially map into AArch64 + * system register encodings. + */ + if (params.Op1 =3D=3D 0 && params.CRn =3D=3D 0 && params.CRm) + return kvm_emulate_cp15_id_reg(vcpu, ¶ms); + + return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); } =20 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) @@ -2392,7 +2444,11 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) =20 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) { - return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); + struct sys_reg_params params; + + params =3D esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu)); + + return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs)); } =20 static bool is_imp_def_sys_reg(struct sys_reg_params *params) diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index cc0cc95a0280..0d31a12b640c 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -35,6 +35,13 @@ struct sys_reg_params { .Op2 =3D ((esr) >> 17) & 0x7, \ .is_write =3D !((esr) & 1) }) =20 +#define esr_cp1x_32_to_params(esr) \ + ((struct sys_reg_params){ .Op1 =3D ((esr) >> 14) & 0x7, \ + .CRn =3D ((esr) >> 10) & 0xf, \ + .CRm =3D ((esr) >> 1) & 0xf, \ + .Op2 =3D ((esr) >> 17) & 0x7, \ + .is_write =3D !((esr) & 1) }) + struct sys_reg_desc { /* Sysreg string for debug */ const char *name; --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17013C433EF for ; Tue, 3 May 2022 06:02:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229617AbiECGGG (ORCPT ); Tue, 3 May 2022 02:06:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229559AbiECGFq (ORCPT ); Tue, 3 May 2022 02:05:46 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BEBA3334C for ; Mon, 2 May 2022 23:02:15 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id y17-20020a637d11000000b003ab06870074so7989087pgc.15 for ; Mon, 02 May 2022 23:02:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=kNIvmW+UQg4kyqFomsH3U0dCsHh4hH7Ihe0URim/gjs=; b=b8rMBUdg4rhRlWUVQAGU8hwTTgclcE+ZuT0I+HoyfNsYte5xd4WZREks7dSJU2hZMi W4nw4EmMJxc4L57f/GjA40yADNMoW/qKH/AkbNYA8gLS+qld7+pQcxsef2BeWecupjTd dXe+QrmXQEaFf793D6cRph4IQPhYTGEWOXVq3xNVWZ0yP1wcpHCOQsKJ04G2wiWyPbCt gX7KU4MCAOaZjeajKEHSt+YZNLVh2LTypdUfaeGYcMiBoSE7k+/dupBHNZWtdPPoxICl gj5s/tyxhC4ZfQMYwMtfRP+bfcTXubHDdnOnOc0Z2il9yqGfAj+XikS3UMysgF9YCBTx rsgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=kNIvmW+UQg4kyqFomsH3U0dCsHh4hH7Ihe0URim/gjs=; b=6g9AfavbbX1m2kQzItV9DSqulcf0yeEOrIIp1txL9X0V6jPWyj7a5qmlfBDf5+B0/J N7zPsbXRuOI8EE8x7DE5UQbFfapMPO1oeQL3KLy0HdmWwyZshhHUbjHX5cNU55KBSOJ4 wsd7pw3hcV9424KHR9l1EmVJ34TPyveaDR8Xu7lOMpSsOMwllXYps92diXE1WtHIBDPl GP3f3BIUSs1+sD2g99Wih/HR6uqZDukYmj10mA86wmAOgjxYnIuN32z7n4iqmDMvHcaE Gpt63lOnmiGLEeQoMmiY3LaiArrhrWQpmE+9C5HKY8w4+9owrmGeC7DtURHbdFltr6zB g/Lg== X-Gm-Message-State: AOAM530k0A2lxusAK3swcHu6e/spLbG4dBGWAoefYNGwQX8vP6Ee2Bam TtGvCYQQFYgPh0B+fv8MOUS8SynjW14= X-Google-Smtp-Source: ABdhPJwhlUbmJ/c+5cel5YbXwoabm+ZFEQDGUQzmk+0Grk7pE6oPCjZRhL0uNrGXFbrQzfvJ7uRjCYQnx/8= X-Received: from oupton3.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:21eb]) (user=oupton job=sendgmr) by 2002:a17:90a:5407:b0:1bf:43ce:f11b with SMTP id z7-20020a17090a540700b001bf43cef11bmr3031142pjh.31.1651557734948; Mon, 02 May 2022 23:02:14 -0700 (PDT) Date: Tue, 3 May 2022 06:02:02 +0000 In-Reply-To: <20220503060205.2823727-1-oupton@google.com> Message-Id: <20220503060205.2823727-5-oupton@google.com> Mime-Version: 1.0 References: <20220503060205.2823727-1-oupton@google.com> X-Mailer: git-send-email 2.36.0.464.gb9c8b46e94-goog Subject: [PATCH v4 4/7] KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com, Oliver Upton Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to enable HCR_EL2.TID3 for AArch32 guests KVM needs to handle traps where ESR_EL2.EC=3D0x8, which corresponds to an attempted VMRS access from an ID group register. Specifically, the MVFR{0-2} registers are accessed this way from AArch32. Conveniently, these registers are architecturally mapped to MVFR{0-2}_EL1 in AArch64. Furthermore, KVM already handles reads to these aliases in AArch64. Plumb VMRS read traps through to the general AArch64 system register handler. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/handle_exit.c | 1 + arch/arm64/kvm/sys_regs.c | 71 +++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 94a27a7520f4..05081b9b7369 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -683,6 +683,7 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); =20 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); =20 diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 97fe14aab1a3..5088a86ace5b 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -167,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] =3D { [ESR_ELx_EC_CP15_64] =3D kvm_handle_cp15_64, [ESR_ELx_EC_CP14_MR] =3D kvm_handle_cp14_32, [ESR_ELx_EC_CP14_LS] =3D kvm_handle_cp14_load_store, + [ESR_ELx_EC_CP10_ID] =3D kvm_handle_cp10_id, [ESR_ELx_EC_CP14_64] =3D kvm_handle_cp14_64, [ESR_ELx_EC_HVC32] =3D handle_hvc, [ESR_ELx_EC_SMC32] =3D handle_smc, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f403ea47b8a3..586b292ca94f 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2346,6 +2346,77 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, =20 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *= params); =20 +/* + * The CP10 ID registers are architecturally mapped to AArch64 feature + * registers. Abuse that fact so we can rely on the AArch64 handler for ac= cesses + * from AArch32. + */ +static bool kvm_esr_cp10_id_to_sys64(u32 esr, struct sys_reg_params *param= s) +{ + u8 reg_id =3D (esr >> 10) & 0xf; + bool valid; + + params->is_write =3D ((esr & 1) =3D=3D 0); + params->Op0 =3D 3; + params->Op1 =3D 0; + params->CRn =3D 0; + params->CRm =3D 3; + + /* CP10 ID registers are read-only */ + valid =3D !params->is_write; + + switch (reg_id) { + /* MVFR0 */ + case 0b0111: + params->Op2 =3D 0; + break; + /* MVFR1 */ + case 0b0110: + params->Op2 =3D 1; + break; + /* MVFR2 */ + case 0b0101: + params->Op2 =3D 2; + break; + default: + valid =3D false; + } + + if (valid) + return true; + + kvm_pr_unimpl("Unhandled cp10 register %s: %u\n", + params->is_write ? "write" : "read", reg_id); + return false; +} + +/** + * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media = and + * VFP Register' from AArch32. + * @vcpu: The vCPU pointer + * + * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 regis= ters. + * Work out the correct AArch64 system register encoding and reroute to the + * AArch64 system register emulation. + */ +int kvm_handle_cp10_id(struct kvm_vcpu *vcpu) +{ + int Rt =3D kvm_vcpu_sys_get_rt(vcpu); + u32 esr =3D kvm_vcpu_get_esr(vcpu); + struct sys_reg_params params; + + /* UNDEF on any unhandled register access */ + if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) { + kvm_inject_undefined(vcpu); + return 1; + } + + if (emulate_sys_reg(vcpu, ¶ms)) + vcpu_set_reg(vcpu, Rt, params.regval); + + return 1; +} + /** * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access = where * CRn=3D0, which corresponds to the AArch32 feature --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F92C433F5 for ; Tue, 3 May 2022 06:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229741AbiECGGT (ORCPT ); Tue, 3 May 2022 02:06:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbiECGFs (ORCPT ); Tue, 3 May 2022 02:05:48 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDC683388B for ; Mon, 2 May 2022 23:02:16 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id 15-20020aa7920f000000b0050cf449957fso9037563pfo.9 for ; Mon, 02 May 2022 23:02:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=szYmrqPYm2+NRRnt6PLMcdW9lpIQNg8jUIBDaOx8F6c=; b=V0Ff2JHN/1ixKrZ4eXGKn+a1zJeLIYlGYLahoOCZr8dElnZtvoleLd1AUljKq2Go9d rH4xnD+d0QINZ8krn4kU/t4Al1gAUsxZeaOoqF4H59F5jNmYCo6PfQ/j996ln7nA7iu8 pcY1n42K41AdqbRiqGlMilri6fmVwnRuNxSSChGk4LLAFC+zWHSxjezK72kFqeIKYTCR qEjEjFBkaHLm853u2Nu+XOemUA5hy7bvcgJzwKdVriGETjug41pMjNR07Ya9twKoO51H 4xtYqUYCWtZr+UavK1Se7ZAlRTGAHQ3RkVEeWKw8se1PuhyA07Pf+d7OgRKMC7GNtttW Ntug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=szYmrqPYm2+NRRnt6PLMcdW9lpIQNg8jUIBDaOx8F6c=; b=OWp6oLXYZda9+Dq6h4TUqz6/cNv755/JMEwVvTtPcrQ7pTX2OfMI1WJvay3Zwi0xZ/ zREu6zpl2iYiSJ8gc6+uugsgLzK0Q5pLL0gl1ILvD6Drc5nvd7uXeGCJlwLKsjPcr1FI IBFdw6D5Wjg26kenhP5Ce5j4i0sSIHwYfhv/ENxLPNU97g54R6iA6mfll7bRiA1i4KHD PE8zV1nF4ODuIgRd48DI/JAdSSws+1wHcm6OgttrxI3qD7noJbg31EUrqvpOaI9S+vS4 G2v6RpFsxCZMO4odMcQmGQf8DU9SZMxDX5aZLVm82qkEGCNvXI5M/IC5x6fI2a9e11Qw Q4CQ== X-Gm-Message-State: AOAM5329wez4moyXOBGYlpvKVXHKAB3MzVYNvfWN6nCml7e3l9uaAfLL 7xeF5PK/sfacF4J+3GHbArB+MXr8jXg= X-Google-Smtp-Source: ABdhPJzb2TkawwG87rw4pGRJ8PwWuWWZ0LiwEjnIjgPb3w5iW4PoKAlHdEQUIZdxC52BhyeVWcl2kMFzdMo= X-Received: from oupton3.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:21eb]) (user=oupton job=sendgmr) by 2002:a05:6a00:1496:b0:50d:9f76:ec7b with SMTP id v22-20020a056a00149600b0050d9f76ec7bmr14700869pfu.58.1651557736423; Mon, 02 May 2022 23:02:16 -0700 (PDT) Date: Tue, 3 May 2022 06:02:03 +0000 In-Reply-To: <20220503060205.2823727-1-oupton@google.com> Message-Id: <20220503060205.2823727-6-oupton@google.com> Mime-Version: 1.0 References: <20220503060205.2823727-1-oupton@google.com> X-Mailer: git-send-email 2.36.0.464.gb9c8b46e94-goog Subject: [PATCH v4 5/7] KVM: arm64: Start trapping ID registers for 32 bit guests From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com, Oliver Upton Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To date KVM has not trapped ID register accesses from AArch32, meaning that guests get an unconstrained view of what hardware supports. This can be a serious problem because we try to base the guest's feature registers on values that are safe system-wide. Furthermore, KVM does not implement the latest ISA in the PMU and Debug architecture, so we constrain these fields to supported values. Since KVM now correctly handles CP15 and CP10 register traps, we no longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead emulate reads with their safe values. Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 7 ------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 1767ded83888..b5de102928d8 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -80,11 +80,12 @@ * FMO: Override CPSR.F and enable signaling with VF * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory + * TID3: Trap EL1 reads of group 3 ID registers */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index f71358271b71..07812680fcaf 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -87,13 +87,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) =20 if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_RW; - else - /* - * TID3: trap feature register accesses that we virtualise. - * For now this is conditional, since no AArch32 feature regs - * are currently virtualised. - */ - vcpu->arch.hcr_el2 |=3D HCR_TID3; =20 if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || vcpu_el1_is_32bit(vcpu)) --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01A41C433EF for ; Tue, 3 May 2022 06:02:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229828AbiECGGK (ORCPT ); Tue, 3 May 2022 02:06:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229587AbiECGFv (ORCPT ); Tue, 3 May 2022 02:05:51 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE38D3336C for ; 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Mon, 02 May 2022 23:02:17 -0700 (PDT) Date: Tue, 3 May 2022 06:02:04 +0000 In-Reply-To: <20220503060205.2823727-1-oupton@google.com> Message-Id: <20220503060205.2823727-7-oupton@google.com> Mime-Version: 1.0 References: <20220503060205.2823727-1-oupton@google.com> X-Mailer: git-send-email 2.36.0.464.gb9c8b46e94-goog Subject: [PATCH v4 6/7] KVM/arm64: Hide AArch32 PMU registers when not available From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com, Oliver Upton Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexandru Elisei commit 11663111cd49 ("KVM: arm64: Hide PMU registers from userspace when not available") hid the AArch64 PMU registers from userspace and guest when the PMU VCPU feature was not set. Do the same when the PMU registers are accessed by an AArch32 guest. While we're at it, rename the previously unused AA32_ZEROHIGH to AA32_DIRECT to match the behavior of get_access_mask(). Now that KVM emulates ID_DFR0 and hides the PMU from the guest when the feature is not set, it is safe to inject to inject an undefined exception when the PMU is not present, as that corresponds to the architected behaviour. Signed-off-by: Alexandru Elisei [Oliver - Add AA32_DIRECT to match the zero value of the enum] Signed-off-by: Oliver Upton --- arch/arm64/kvm/sys_regs.c | 60 ++++++++++++++++++++------------------- arch/arm64/kvm/sys_regs.h | 2 +- 2 files changed, 32 insertions(+), 30 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 586b292ca94f..f3235eafdadc 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2014,20 +2014,22 @@ static const struct sys_reg_desc cp14_64_regs[] =3D= { { Op1( 0), CRm( 2), .access =3D trap_raz_wi }, }; =20 +#define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \ + AA32(_map), \ + Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \ + .visibility =3D pmu_visibility + /* Macro to expand the PMEVCNTRn register */ #define PMU_PMEVCNTR(n) \ - /* PMEVCNTRn */ \ - { Op1(0), CRn(0b1110), \ - CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ - access_pmu_evcntr } + { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ + (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ + .access =3D access_pmu_evcntr } =20 /* Macro to expand the PMEVTYPERn register */ #define PMU_PMEVTYPER(n) \ - /* PMEVTYPERn */ \ - { Op1(0), CRn(0b1110), \ - CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ - access_pmu_evtyper } - + { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \ + (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \ + .access =3D access_pmu_evtyper } /* * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, * depending on the way they are accessed (as a 32bit or a 64bit @@ -2067,25 +2069,25 @@ static const struct sys_reg_desc cp15_regs[] =3D { { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, =20 /* PMU */ - { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, - { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, - { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, - { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, - { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, - { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, - { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, - { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, - { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, - { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, - { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, - { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, - { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, - { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, - { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, - { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid }, - { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access =3D access_pmcr }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access =3D access_pmcnten }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access =3D access_pmcnten }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access =3D access_pmovs }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access =3D access_pmswinc }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access =3D access_pmselr }, + { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access =3D access_pmceid }, + { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access =3D access_pmceid }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access =3D access_pmu_evcntr }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access =3D access_pmu_evtyper }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access =3D access_pmu_evcntr }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access =3D access_pmuserenr }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access =3D access_pminten }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access =3D access_pminten }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access =3D access_pmovs }, + { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access =3D access_pmceid }, + { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access =3D access_pmceid }, /* PMMIR */ - { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi }, + { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access =3D trap_raz_wi }, =20 /* PRRR/MAIR0 */ { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR= _EL1 }, @@ -2170,7 +2172,7 @@ static const struct sys_reg_desc cp15_regs[] =3D { PMU_PMEVTYPER(29), PMU_PMEVTYPER(30), /* PMCCFILTR */ - { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, + { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access =3D access_pmu_evtyper = }, =20 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, @@ -2179,7 +2181,7 @@ static const struct sys_reg_desc cp15_regs[] =3D { =20 static const struct sys_reg_desc cp15_64_regs[] =3D { { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, - { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, + { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access =3D access_pmu_evcntr }, { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index 0d31a12b640c..aee8ea054f0d 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -47,7 +47,7 @@ struct sys_reg_desc { const char *name; =20 enum { - AA32_ZEROHIGH, + AA32_DIRECT, AA32_LO, AA32_HI, } aarch32_map; --=20 2.36.0.464.gb9c8b46e94-goog From nobody Sun May 10 14:12:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 108B0C433EF for ; Tue, 3 May 2022 06:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229752AbiECGGY (ORCPT ); Tue, 3 May 2022 02:06:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbiECGFx (ORCPT ); Tue, 3 May 2022 02:05:53 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3699033A35 for ; Mon, 2 May 2022 23:02:20 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id j187-20020a638bc4000000b003c1922b0f1bso5927761pge.3 for ; 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Mon, 02 May 2022 23:02:19 -0700 (PDT) Date: Tue, 3 May 2022 06:02:05 +0000 In-Reply-To: <20220503060205.2823727-1-oupton@google.com> Message-Id: <20220503060205.2823727-8-oupton@google.com> Mime-Version: 1.0 References: <20220503060205.2823727-1-oupton@google.com> X-Mailer: git-send-email 2.36.0.464.gb9c8b46e94-goog Subject: [PATCH v4 7/7] Revert "KVM/arm64: Don't emulate a PMU for 32-bit guests if feature not set" From: Oliver Upton To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com, Oliver Upton Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This reverts commit 8f6379e207e7d834065a080f407a60d67349d961. The original change was not problematic but chose nonarchitected PMU register behavior over a NULL deref as KVM failed to hide the PMU in the ID_DFR0. Since KVM now provides a sane value for ID_DFR0 and UNDEFs the guest for unsupported accesses, drop the unneeded checks in PMU register handlers. Signed-off-by: Oliver Upton --- arch/arm64/kvm/pmu-emul.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 3dc990ac4f44..78fdc443adc7 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -177,9 +177,6 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u6= 4 select_idx) struct kvm_pmu *pmu =3D &vcpu->arch.pmu; struct kvm_pmc *pmc =3D &pmu->pmc[select_idx]; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return 0; - counter =3D kvm_pmu_get_pair_counter_value(vcpu, pmc); =20 if (kvm_pmu_pmc_is_chained(pmc) && @@ -201,9 +198,6 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u= 64 select_idx, u64 val) { u64 reg; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - reg =3D (select_idx =3D=3D ARMV8_PMU_CYCLE_IDX) ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx; __vcpu_sys_reg(vcpu, reg) +=3D (s64)val - kvm_pmu_get_counter_value(vcpu,= select_idx); @@ -328,9 +322,6 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu,= u64 val) struct kvm_pmu *pmu =3D &vcpu->arch.pmu; struct kvm_pmc *pmc; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val) return; =20 @@ -366,7 +357,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu= , u64 val) struct kvm_pmu *pmu =3D &vcpu->arch.pmu; struct kvm_pmc *pmc; =20 - if (!kvm_vcpu_has_pmu(vcpu) || !val) + if (!val) return; =20 for (i =3D 0; i < ARMV8_PMU_MAX_COUNTERS; i++) { @@ -536,9 +527,6 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, = u64 val) struct kvm_pmu *pmu =3D &vcpu->arch.pmu; int i; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) return; =20 @@ -588,9 +576,6 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) { int i; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - if (val & ARMV8_PMU_PMCR_E) { kvm_pmu_enable_counter_mask(vcpu, __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); @@ -754,9 +739,6 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vc= pu, u64 data, { u64 reg, mask; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - mask =3D ARMV8_PMU_EVTYPE_MASK; mask &=3D ~ARMV8_PMU_EVTYPE_EVENT; mask |=3D kvm_pmu_event_mask(vcpu->kvm); @@ -845,9 +827,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmce= id1) u64 val, mask =3D 0; int base, i, nr_events; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return 0; - if (!pmceid1) { val =3D read_sysreg(pmceid0_el0); base =3D 0; --=20 2.36.0.464.gb9c8b46e94-goog