From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76F8AC433FE for ; Mon, 2 May 2022 06:06:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383441AbiEBGKK (ORCPT ); Mon, 2 May 2022 02:10:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357937AbiEBGJy (ORCPT ); Mon, 2 May 2022 02:09:54 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F614E3A4 for ; Sun, 1 May 2022 23:06:26 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d15so11739636plh.2 for ; Sun, 01 May 2022 23:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mhwiSz4nUEKxyVPxPgnud7ZLMUjJ9Xi44F8SQGqayAg=; b=iLxrj/+HHvqwp534r7ex2+ODCsXS4sjzqe6oSlMHEPI5j7BJ0SgUCZ2YqSjT8+Y6LL dGy71rI2xipA03Dgt7LqaR0sxzqCq+Ld/k7q1aX7AoCA2zY/kFr0iBjXGyfnlJ7BhHPy kmbHhCkFOiFkpVa/sjLPi1RyKF9uFwrrltT4nonpOXnYyqXuxj+e0R+SD8SglSoE72bJ kGalj/TjjopC0cL0UXLfZ+6nedHm4Z7jKHk4yWMXxqHQfjxZ0GDToprso+80r3mN8ZNA GSf+qKjsr72rDkWOeTQhQFx/pDSITjbIuPi0q7C5LV7SuCF7rqO7xg1KNgAQxrdL4Yi/ rhAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mhwiSz4nUEKxyVPxPgnud7ZLMUjJ9Xi44F8SQGqayAg=; b=jpZlY26+shJgmmKZNNBA6TDMfQfLNxjwcSH0Kyfc1CK/YWYL3kMuBvHeCqKt9HZdKs 8bNdosdRY6b1pn4cbBPKOb6wQ8Y0TEjexRSiKDMd3/HCA2uwLvJ49i1GXjABNIwvhPzF JEbdiyLDY/II8m53p0MR8jlQqMRuQw5y2xPHeQQjQDBtlavrIHE7B7AeropgDIQz/QFp 7KX+9WYOzVmQZy4PAGnyD/727nwKamf45T12d0OlBE2V4LwBUlYGli+QJB7DVJDGhfjM 3Zn7OuF17K0lnL+unLics21UFdf6MzT/pG3ivnRjEriMPgTWTUCHyJQju3qiJmBgqnTC Lu7g== X-Gm-Message-State: AOAM530GIoB3QSodQsAYNOnBe7+/tUo0b/jALHwVwAW+mDR56Q6mWogp kfeTXTPsxJNPmjIXhi95lOse X-Google-Smtp-Source: ABdhPJxG6HMx0DWdiaCr+PhNjaS2SLQj3j4gb1NoZlCahr2ddBju081kXD1bYo3hD052lZVaZwue5Q== X-Received: by 2002:a17:90b:4a02:b0:1dc:4710:c1fe with SMTP id kk2-20020a17090b4a0200b001dc4710c1femr6729696pjb.208.1651471585900; Sun, 01 May 2022 23:06:25 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:25 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/8] PCI: endpoint: Pass EPF device ID to the probe function Date: Mon, 2 May 2022 11:36:04 +0530 Message-Id: <20220502060611.58987-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the EPF probe function doesn't get the device ID argument needed to correctly identify the device table ID of the EPF device. When multiple entries are added to the "struct pci_epf_device_id" table, the probe function needs to identify the correct one. And the only way to do so is by storing the correct device ID in "struct pci_epf" during "pci_epf_match_id()" and passing that to probe(). Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-ntb.c | 3 ++- drivers/pci/endpoint/functions/pci-epf-test.c | 2 +- drivers/pci/endpoint/pci-epf-core.c | 8 +++++--- include/linux/pci-epf.h | 4 +++- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/end= point/functions/pci-epf-ntb.c index 9a00448c7e61..980b4ecf19a2 100644 --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c @@ -2075,11 +2075,12 @@ static struct config_group *epf_ntb_add_cfs(struct = pci_epf *epf, /** * epf_ntb_probe() - Probe NTB function driver * @epf: NTB endpoint function device + * @id: NTB endpoint function device ID * * Probe NTB function driver when endpoint function bus detects a NTB * endpoint function. */ -static int epf_ntb_probe(struct pci_epf *epf) +static int epf_ntb_probe(struct pci_epf *epf, const struct pci_epf_device_= id *id) { struct epf_ntb *ntb; struct device *dev; diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/en= dpoint/functions/pci-epf-test.c index 5b833f00e980..f82b52e07621 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -901,7 +901,7 @@ static const struct pci_epf_device_id pci_epf_test_ids[= ] =3D { {}, }; =20 -static int pci_epf_test_probe(struct pci_epf *epf) +static int pci_epf_test_probe(struct pci_epf *epf, const struct pci_epf_de= vice_id *id) { struct pci_epf_test *epf_test; struct device *dev =3D &epf->dev; diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci= -epf-core.c index 9ed556936f48..0882ac829e95 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -494,11 +494,13 @@ static const struct device_type pci_epf_type =3D { }; =20 static int -pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf = *epf) +pci_epf_match_id(const struct pci_epf_device_id *id, struct pci_epf *epf) { while (id->name[0]) { - if (strcmp(epf->name, id->name) =3D=3D 0) + if (strcmp(epf->name, id->name) =3D=3D 0) { + epf->id =3D id; return true; + } id++; } =20 @@ -526,7 +528,7 @@ static int pci_epf_device_probe(struct device *dev) =20 epf->driver =3D driver; =20 - return driver->probe(epf); + return driver->probe(epf, epf->id); } =20 static void pci_epf_device_remove(struct device *dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 009a07147c61..0c94cc1513bc 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -84,7 +84,7 @@ struct pci_epf_ops { * @id_table: identifies EPF devices for probing */ struct pci_epf_driver { - int (*probe)(struct pci_epf *epf); + int (*probe)(struct pci_epf *epf, const struct pci_epf_device_id *id); void (*remove)(struct pci_epf *epf); =20 struct device_driver driver; @@ -126,6 +126,7 @@ struct pci_epf_bar { * @epc: the EPC device to which this EPF device is bound * @epf_pf: the physical EPF device to which this virtual EPF device is bo= und * @driver: the EPF driver to which this EPF device is bound + * @id: Pointer to the EPF device ID * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc * @nb: notifier block to notify EPF of any EPC events (like linkup) * @lock: mutex to protect pci_epf_ops @@ -153,6 +154,7 @@ struct pci_epf { struct pci_epc *epc; struct pci_epf *epf_pf; struct pci_epf_driver *driver; + const struct pci_epf_device_id *id; struct list_head list; struct notifier_block nb; /* mutex to protect against concurrent access of pci_epf_ops */ --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF6EAC4332F for ; Mon, 2 May 2022 06:06:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383452AbiEBGKP (ORCPT ); Mon, 2 May 2022 02:10:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357975AbiEBGJ6 (ORCPT ); Mon, 2 May 2022 02:09:58 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 849C34EA3F for ; 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charset="utf-8" When the EPC is started or stopped multiple times from configfs, just emit a once time warning and return. There is no need to call the EPC start/stop functions in those cases. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-ep-cfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-e= p-cfs.c index d4850bdd837f..2cfd5fd2794c 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -178,6 +178,9 @@ static ssize_t pci_epc_start_store(struct config_item *= item, const char *page, if (kstrtobool(page, &start) < 0) return -EINVAL; =20 + if (WARN_ON_ONCE(start =3D=3D epc_group->start)) + return 0; + if (!start) { pci_epc_stop(epc); epc_group->start =3D 0; --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 718A1C433F5 for ; Mon, 2 May 2022 06:07:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383463AbiEBGK0 (ORCPT ); Mon, 2 May 2022 02:10:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383426AbiEBGKD (ORCPT ); Mon, 2 May 2022 02:10:03 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37CE54E3A5 for ; Sun, 1 May 2022 23:06:34 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id qe3-20020a17090b4f8300b001dc24e4da73so3367072pjb.1 for ; Sun, 01 May 2022 23:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2LFzmNO7TCPQPtgoHwZk5k2/uRSVZZGRTm5zpsoWJbc=; b=d9NwqnU/0ESwjiYm54qTQDSlOQVbQkLaT/oxMr01WT1sLQSn/nIsYnfDVUIJGmHQFc uDLyfb/6sbStsBgP++Bzpcd/uRNJ0Ek5MCO3JAd0BEvmVNkUN9XbglURygJo93dTIFJ4 D32OsAIgBvYgtFqbMBKZ4ZeAMFmCSjpOvZ8VBxf4PFUOz942bR1c5frVwFcZS0o4uexz 1IDhD8bmckcDWTiDnGJa6yNaThbzees8/IMhpavLgoMecGPPkYNJX6IfiIz9AGSGN8jG ZxpzCb5OmLRR6SMVXtQ5Es8sbIDKAk5vb8qZnjTFKHXlxu20vmw0FY5kdwjLlju9ykH8 WKuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2LFzmNO7TCPQPtgoHwZk5k2/uRSVZZGRTm5zpsoWJbc=; b=huxsKEOdxInvMgANPBxG1HuO0i+eLv1RTM8ziJWLgwc6KZeVO2nR8FHBA9WGqyA3HC dqavtP7twjVGpzgWk0XWd+1IZouys+hCYbLpoyrDWxq7j1H5PBq5tQ79sggKGIrwoM9S yJzZ1hRFDJ91y2Ys3rRc7ix7uiaKOYeoWIs2FPLHcGCVJUovz4qJ/dHJYs3ZHKKSOmjk 8vtoYNCz8cOazyeu9LjXro4eTTZoqlybFagy5FZf0YXF+peDb9gI92nmwEjgxbEEVNUB oUYGiDKajWSp5yl8BPdWMYvvFdHCKCLX1rfeC5ggO0CgrSUSFNj6uUDSZ0thQA7mV2Hw zGig== X-Gm-Message-State: AOAM53148IZGImwR035YOrMDvIW0NSk2FBfP9SfYnJunS2h4fZpjj7Bw 4xXq8n5bQ3j/BsVtpxJDLf3i X-Google-Smtp-Source: ABdhPJx8v44BYBTieqJIya4Js5QwL5B5LYV+aXWIrs6lmDjOrWlDALn06JJenvBb1Bv7Ni9twVRZMw== X-Received: by 2002:a17:902:d508:b0:15e:a12e:8089 with SMTP id b8-20020a170902d50800b0015ea12e8089mr4637149plg.137.1651471593731; Sun, 01 May 2022 23:06:33 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:33 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/8] PCI: endpoint: Add an API for unregistering the EPF notifier Date: Mon, 2 May 2022 11:36:06 +0530 Message-Id: <20220502060611.58987-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add "pci_epc_unregister_notifier()" to unregister the notifier added between EPC and EPF. Signed-off-by: Manivannan Sadhasivam --- include/linux/pci-epc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index a48778e1a4ee..c414a08bfd67 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -198,6 +198,12 @@ pci_epc_register_notifier(struct pci_epc *epc, struct = notifier_block *nb) return atomic_notifier_chain_register(&epc->notifier, nb); } =20 +static inline int +pci_epc_unregister_notifier(struct pci_epc *epc, struct notifier_block *nb) +{ + return atomic_notifier_chain_unregister(&epc->notifier, nb); +} + struct pci_epc * __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EE6AC433F5 for ; Mon, 2 May 2022 06:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383473AbiEBGKf (ORCPT ); Mon, 2 May 2022 02:10:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383431AbiEBGKF (ORCPT ); Mon, 2 May 2022 02:10:05 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 698A14EF4B for ; Sun, 1 May 2022 23:06:37 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id p12so11598379pfn.0 for ; Sun, 01 May 2022 23:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FL4JimMUhmY1BeTMTK+TnPmU576KVxmETjweuyLuCOo=; b=OFXE66pE/ktWSt/5voVeEhMhzzjJ3ORO0W5OjxJds9qw+k7j2EG9ORxSHmD5i8yEm5 nC9O4KPZiYx+rv4InxZiPdWLN2X4hDs0DhNp1k2iT/ZeAFpAmYyTDJIBCYb9udtNrq+G xPCzCRXZ2b+LgvRYHNkcR98uDFeQdjZNhZ9q7kZSRWU2Z0MDzV3ZeYTHPoWoNpv7+fQs cky8tLry5aLxOdICsNscsAYGlpDeRdlIcFXEG11VuGjhzJ9+YMFlhmiwe7E7yb13rf+H 4HE25MLXBrJ52iZQPuL9A9rrp+85ZdIa9POCM2WQQBOBUr8zfcQh0BR8L4/uAdM8Mxz6 4TuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FL4JimMUhmY1BeTMTK+TnPmU576KVxmETjweuyLuCOo=; b=k7+T8pUf5MWu4MODgKGKcWPSlAoAP9mE+jnw/OKFclXVLRHUzcwfXWNgUNRUbdXCCt V6+1cd5i/EIHhjc+u6R7r1nauH0pEXvFhbLVCcnn5BycBOxotBKvBe6j8N+3g1+z2+w3 PfjWNZiXXVxHtl6xpuR3WwERAnRgWkh+Q+x0CDZCNq0UlYeH6AT3Rp6dcJSuxfeW5WuQ JhGHLrYMAZ9k8mUrNxQrIad2i+5KCHTXVMhPV+gujUlbj6M82JZpA+pg8YpzFGvvYpa3 hOLfjghi2AUyU3/ALv1ZZhiXhWhYPNn7Gg7peKAjxeFbCeTVXNrHgetJVlO/L3Pe5WDL NdJQ== X-Gm-Message-State: AOAM530ABmz1GuK/nAi2NRkqbn2q5ejJgvGbajbRyaFnbiWUMfs8dr/7 /VGymxq4o+qF2MYUTo3UR9sv X-Google-Smtp-Source: ABdhPJxb6iPxT001JHILmsfK5SvyQcjtft+sZmMyKCsyzDQDauyPZCbU2PiXuVxii4Sz+RFpxlBhLQ== X-Received: by 2002:a62:e518:0:b0:4fa:9333:ddbd with SMTP id n24-20020a62e518000000b004fa9333ddbdmr10156182pff.11.1651471596890; Sun, 01 May 2022 23:06:36 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:36 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 4/8] PCI: endpoint: Add linkdown notifier support Date: Mon, 2 May 2022 11:36:07 +0530 Message-Id: <20220502060611.58987-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to notify the EPF device about the linkdown event from the EPC device. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 17 +++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index 3bc9273d0a08..8401c2750c9e 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -697,6 +697,23 @@ void pci_epc_linkup(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_linkup); =20 +/** + * pci_epc_linkdown() - Notify the EPF device that EPC device has dropped = the + * connection with the Root Complex. + * @epc: the EPC device which has dropped the link with the host + * + * Invoke to Notify the EPF device that the EPC device has dropped the + * connection with the Root Complex. + */ +void pci_epc_linkdown(struct pci_epc *epc) +{ + if (!epc || IS_ERR(epc)) + return; + + atomic_notifier_call_chain(&epc->notifier, LINK_DOWN, NULL); +} +EXPORT_SYMBOL_GPL(pci_epc_linkdown); + /** * pci_epc_init_notify() - Notify the EPF device that EPC device's core * initialization is completed. diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c414a08bfd67..d346ab9ae061 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -215,6 +215,7 @@ void pci_epc_destroy(struct pci_epc *epc); int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); void pci_epc_linkup(struct pci_epc *epc); +void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 0c94cc1513bc..b1fcd88d0b1f 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -20,6 +20,7 @@ enum pci_epc_interface_type; enum pci_notify_event { CORE_INIT, LINK_UP, + LINK_DOWN, }; =20 enum pci_barno { --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E19E5C433EF for ; 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Sun, 01 May 2022 23:06:39 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/8] PCI: endpoint: Add BME notifier support Date: Mon, 2 May 2022 11:36:08 +0530 Message-Id: <20220502060611.58987-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to notify the EPF device about the Bus Master Enable (BME) event received by the EPC device from the Root complex. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 17 +++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index 8401c2750c9e..6120d99bff73 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -731,6 +731,23 @@ void pci_epc_init_notify(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_init_notify); =20 +/** + * pci_epc_bme_notify() - Notify the EPF device that the EPC device has re= ceived + * the BME event from the Root complex + * @epc: the EPC device that received the BME event + * + * Invoke to Notify the EPF device that the EPC device has received the Bus + * Master Enable (BME) event from the Root complex + */ +void pci_epc_bme_notify(struct pci_epc *epc) +{ + if (!epc || IS_ERR(epc)) + return; + + atomic_notifier_call_chain(&epc->notifier, BME, NULL); +} +EXPORT_SYMBOL_GPL(pci_epc_bme_notify); + /** * pci_epc_destroy() - destroy the EPC device * @epc: the EPC device that has to be destroyed diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index d346ab9ae061..8454610df4c3 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -217,6 +217,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf= *epf, void pci_epc_linkup(struct pci_epc *epc); void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); +void pci_epc_bme_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index b1fcd88d0b1f..e03c57129ed5 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -21,6 +21,7 @@ enum pci_notify_event { CORE_INIT, LINK_UP, LINK_DOWN, + BME, }; =20 enum pci_barno { --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55600C433F5 for ; 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Sun, 01 May 2022 23:06:42 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 6/8] PCI: qcom-ep: Add support for Link down notification Date: Mon, 2 May 2022 11:36:09 +0530 Message-Id: <20220502060611.58987-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to pass Link down notification to Endpoint function driver so that the LINK_DOWN event can be processed by the function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 6ce8eddf3a37..9fb6e960f73d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -497,6 +497,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int i= rq, void *data) if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_DOWN; + pci_epc_linkdown(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_ENABLED; --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9505CC433EF for ; Mon, 2 May 2022 06:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383524AbiEBGLD (ORCPT ); Mon, 2 May 2022 02:11:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383426AbiEBGK3 (ORCPT ); Mon, 2 May 2022 02:10:29 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67D3F4F9D5 for ; Sun, 1 May 2022 23:06:47 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id 77so1429129pgb.13 for ; Sun, 01 May 2022 23:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFFLVggrg1ac+VShl7a/O0crU97cZXxJdc7Qv9e6jpo=; b=MRG6uDZiye2a9VzfSOg9GkFQs5ay31pWHHk2FPZGRApfAdH62jlvIoWohPApjbKOHo /O+QVPZE6sLqVffHfG++1ce3NAmeEPvzmU1uGkire2ZaqAQ3LWQoKIw72nQuFTEqzx69 ngOHLqxqDiNyZtIxUseAHw7OkafI+h7eAX8Z9eIlJ2sJtHK1BBmUfCKh8uEp/me5Qt3J 7nOkWE5zs6At7golyrghSvRk0or71dM3Ti4DAobUWQyIaSW/E4CVdl4vfwEd6ekDTtf4 dxqrBIFlQnGhoW3qddIXKiz1GeFexibRJzIPI0A3lREsvkO+eV0cVdqbKMOH7ITG7wNB 2aJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TFFLVggrg1ac+VShl7a/O0crU97cZXxJdc7Qv9e6jpo=; b=w7/ZSeHJ11wlORpjJIQjQ/dzoWGGaIAeHKtANZMujFJYL5JlejNj7wwHeP4KyHDTtI 40JqW13puBaKbI5iSPsHV/2SziWvUfNfaM4k3GZGhQFVbmO1bfpS1QvG89JB4IuxCimp 4nH0QWBujclE7vc7FdNAIzgE5QbtFGWB+KzDD3mYpjR78nNOkXWjTz3tbyd2duhI4QYA sMK8GRBvKQSPNnGoBLMhbF0mmg4taZGklF8DlRuLV52H6pbVAoSjvNPnllSds6kzb4g7 A3GRnlLg0k6f6FGLHAMKH49cOsqGRaylYH9HCFsa6B93fQb5wQ/QyGuuFEmK37GJms+6 Pf2Q== X-Gm-Message-State: AOAM530SinuaR62YN/6wTHRRebE60bRnJrSpMyzwtjo9eCZVlZLr+BF3 1oVUp4sJps6LhPLTpilPk1hJQCXzhaDb X-Google-Smtp-Source: ABdhPJw9w/hA1X1uXcsqpbETEhCfGo2yjeVJzZGsedrGj0r7LUsHume70kvxejv+Sc5Z/teqJIEhUA== X-Received: by 2002:a63:d04a:0:b0:3c1:65f2:5d09 with SMTP id s10-20020a63d04a000000b003c165f25d09mr8574707pgi.201.1651471606339; Sun, 01 May 2022 23:06:46 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:46 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 7/8] PCI: qcom-ep: Add support for BME notification Date: Mon, 2 May 2022 11:36:10 +0530 Message-Id: <20220502060611.58987-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to pass BME (Bus Master Enable) notification to Endpoint function driver so that the BME event can be processed by the function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 9fb6e960f73d..67ec52ad87bd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -501,6 +501,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int i= rq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_ENABLED; + pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); val =3D readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); --=20 2.25.1 From nobody Sun May 10 15:09:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B7AC433EF for ; Mon, 2 May 2022 06:07:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383532AbiEBGLM (ORCPT ); Mon, 2 May 2022 02:11:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383491AbiEBGKi (ORCPT ); Mon, 2 May 2022 02:10:38 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0271F515A1 for ; Sun, 1 May 2022 23:06:50 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 77so1429207pgb.13 for ; Sun, 01 May 2022 23:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qL3Xk4i7o3UQDTmWTBFhAVM3P0U5Z5danFVnlmhWQU8=; b=CtDYa+9rPrahTWxdPX13retvUVvs4Vrobf4PgFMToLII8bMacFJj+QQrgX4vZYBfdy nlJIuJYDDq7BnkZeI8YvZbnNrAl8w50yyKALZQpOmzzCSv6qbcXiC0fpXWl5dkWM/kaf Cf/aKhdFLkEtyWCj2qDSzdqupsB5KiWZf7tTUUQKj0/X+Zx46xSDnyivPzGxuQRBB0oD vPiCE8BMrPLV+4aysNAAeMgg3p+GJ8egDF3UmXe4XLTWB+N/4/LQF1GymPpYfA28Jewn eTgb9jj/nTKB/9HnLl6SYwCOoX3Rkl9LsGQff8ZdN0tXosL74xU4qjUIv+D9w1Omr+Ug IJGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qL3Xk4i7o3UQDTmWTBFhAVM3P0U5Z5danFVnlmhWQU8=; b=jCyQsp7KGAB34owohfF0SK0+QpNT1IDaPo+n5qyMJVcpWe0qB2hU1e0O1uf5aPctzo KI70UKMZqndkt9CAjCeK06dTSprP5OqkznYkz3+Q2h/IHCiqEoJ3WMg/uSJoCxCUS3e/ U4xpDYbffAYobGO/LUOsEl6VUDkhWJOc0AiG8+7Yr1I/H7UyfzdNdts9YpuYpCJB44iA MQ5nWUUTB3R4RDJSm4lI/MwxWwYSgpte1UNr8jsfZjKc3wtt2u0zBJP/LljmMuLEsIyJ Rkhp50bLL1eA2vHEDqstsBmUMTLrhZUAJe+JgTTz0naKI976aEkjYZ61HuLb52sZCWUU BE9w== X-Gm-Message-State: AOAM533IgG8ZFae+COhpnMHMyCUTQola5uRj6rwng9qX3AknI7apesk0 xpMZwaraqE0jTdnXCSVEQ4wt X-Google-Smtp-Source: ABdhPJxskezcORxtvqy4ATQjhlEIvBxEON3WMDr/MmKeG4ZkcnLMaygsynDRGW7NqqhQ371q9Pyu5Q== X-Received: by 2002:a62:33c2:0:b0:50d:a588:daab with SMTP id z185-20020a6233c2000000b0050da588daabmr9610562pfz.31.1651471609629; Sun, 01 May 2022 23:06:49 -0700 (PDT) Received: from localhost.localdomain ([27.111.75.99]) by smtp.gmail.com with ESMTPSA id h3-20020a62b403000000b0050dc7628181sm3933826pfn.91.2022.05.01.23.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 23:06:49 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, kw@linux.com, bhelgaas@google.com, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 8/8] PCI: endpoint: Add PCI Endpoint function driver for MHI bus Date: Mon, 2 May 2022 11:36:11 +0530 Message-Id: <20220502060611.58987-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> References: <20220502060611.58987-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCI Endpoint driver for the Qualcomm MHI (Modem Host Interface) bus. The driver implements the MHI function over PCI in the endpoint device such as SDX55 modem. The MHI endpoint function driver acts as a controller driver for the MHI Endpoint stack and carries out all PCI related activities like mapping the host memory using iATU, triggering MSIs etc... Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/Kconfig | 10 + drivers/pci/endpoint/functions/Makefile | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 436 +++++++++++++++++++ 3 files changed, 447 insertions(+) create mode 100644 drivers/pci/endpoint/functions/pci-epf-mhi.c diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/= functions/Kconfig index 5f1242ca2f4e..93497fb70e31 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -25,3 +25,13 @@ config PCI_EPF_NTB device tree. =20 If in doubt, say "N" to disable Endpoint NTB driver. + +config PCI_EPF_MHI + tristate "PCI Endpoint driver for MHI bus" + depends on PCI_ENDPOINT && MHI_BUS_EP + help + Enable this configuration option to enable the PCI Endpoint + driver for Modem Host Interface (MHI) bus found in Qualcomm + modems such as SDX55. + + If in doubt, say "N" to disable Endpoint driver for MHI bus. diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint= /functions/Makefile index 96ab932a537a..eee99b2e9103 100644 --- a/drivers/pci/endpoint/functions/Makefile +++ b/drivers/pci/endpoint/functions/Makefile @@ -5,3 +5,4 @@ =20 obj-$(CONFIG_PCI_EPF_TEST) +=3D pci-epf-test.o obj-$(CONFIG_PCI_EPF_NTB) +=3D pci-epf-ntb.o +obj-$(CONFIG_PCI_EPF_MHI) +=3D pci-epf-mhi.o diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c new file mode 100644 index 000000000000..a8119841a252 --- /dev/null +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI EPF driver for MHI Endpoint devices + * + * Copyright (C) 2022 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include + +#define MHI_VERSION_1_0 0x01000000 + +struct pci_epf_mhi_ep_info { + const struct mhi_ep_cntrl_config *config; + struct pci_epf_header *epf_header; + enum pci_barno bar_num; + u32 epf_flags; + u32 msi_count; + u32 mru; +}; + +#define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \ + { \ + .num =3D ch_num, \ + .name =3D ch_name, \ + .dir =3D DMA_TO_DEVICE, \ + } + +#define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \ + { \ + .num =3D ch_num, \ + .name =3D ch_name, \ + .dir =3D DMA_FROM_DEVICE, \ + } + +static const struct mhi_ep_channel_config mhi_v1_channels[] =3D { + MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"), + MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"), + MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"), + MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"), + MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"), + MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"), + MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"), + MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"), + MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"), + MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"), + MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"), + MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"), + MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"), + MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"), + MHI_EP_CHANNEL_CONFIG_UL(36, "IP_SW0"), + MHI_EP_CHANNEL_CONFIG_DL(37, "IP_SW0"), +}; + +static const struct mhi_ep_cntrl_config mhi_v1_config =3D { + .max_channels =3D 128, + .num_channels =3D ARRAY_SIZE(mhi_v1_channels), + .ch_cfg =3D mhi_v1_channels, + .mhi_version =3D MHI_VERSION_1_0, +}; + +static struct pci_epf_header sdx55_header =3D { + .vendorid =3D PCI_VENDOR_ID_QCOM, + .deviceid =3D 0x0306, + .baseclass_code =3D PCI_BASE_CLASS_COMMUNICATION, + .subclass_code =3D PCI_CLASS_COMMUNICATION_MODEM & 0xff, + .interrupt_pin =3D PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sdx55_info =3D { + .config =3D &mhi_v1_config, + .epf_header =3D &sdx55_header, + .bar_num =3D BAR_0, + .epf_flags =3D PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count =3D 32, + .mru =3D 0x8000, +}; + +struct pci_epf_mhi { + const struct pci_epf_mhi_ep_info *info; + struct mhi_ep_cntrl mhi_cntrl; + struct pci_epf *epf; + struct mutex lock; + void __iomem *mmio; + resource_size_t mmio_phys; + enum pci_notify_event event; + u32 mmio_size; + int irq; + bool mhi_registered; +}; + +static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_a= ddr, + phys_addr_t *phys_ptr, void __iomem **virt, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(mhi_cntrl, struct pci_epf_mh= i, mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf_mhi->epf->epc; + size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + void __iomem *virt_addr; + phys_addr_t phys_addr; + int ret; + + virt_addr =3D pci_epc_mem_alloc_addr(epc, &phys_addr, size + offset); + if (!virt_addr) + return -ENOMEM; + + ret =3D pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr, pci= _addr - offset, size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, phys_addr, virt_addr, size + offset); + + return ret; + } + + *phys_ptr =3D phys_addr + offset; + *virt =3D virt_addr + offset; + + return 0; +} + +static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci= _addr, + phys_addr_t phys_addr, void __iomem *virt_addr, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(mhi_cntrl, struct pci_epf_mh= i, mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr - offset); + pci_epc_mem_free_addr(epc, phys_addr - offset, virt_addr - offset, size += offset); +} + +void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(mhi_cntrl, struct pci_epf_mh= i, mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + + /* + * Vector is incremented by 1 here as the DWC core will decrement it befo= re + * writing to iATU. + */ + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, vect= or + 1); +} + +int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, v= oid __iomem *to, + size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(mhi_cntrl, struct pci_epf_mh= i, mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf_mhi->epf->epc; + void __iomem *tre_buf; + phys_addr_t tre_phys; + size_t offset =3D from % 0x1000; + int ret; + + mutex_lock(&epf_mhi->lock); + + tre_buf =3D pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); + if (!tre_buf) { + mutex_unlock(&epf_mhi->lock); + return -ENOMEM; + } + + ret =3D pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, from= - offset, + size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_fromio(to, tre_buf + offset, size); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, void __iomem= *from, u64 to, + size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(mhi_cntrl, struct pci_epf_mh= i, mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf_mhi->epf->epc; + void __iomem *tre_buf; + phys_addr_t tre_phys; + size_t offset =3D to % 0x1000; + int ret; + + mutex_lock(&epf_mhi->lock); + + tre_buf =3D pci_epc_mem_alloc_addr(epc, &tre_phys, size + offset); + if (!tre_buf) { + mutex_unlock(&epf_mhi->lock); + return -ENOMEM; + } + + ret =3D pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, tre_phys, to -= offset, + size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_toio(tre_buf + offset, from, size); + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, tre_phys); + pci_epc_mem_free_addr(epc, tre_phys, tre_buf, size + offset); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +static int pci_epf_mhi_notifier(struct notifier_block *nb, unsigned long v= al, void *data) +{ + struct pci_epf *epf =3D container_of(nb, struct pci_epf, nb); + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; + struct pci_epf_bar *epf_bar =3D &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + struct pci_epc *epc =3D epf->epc; + struct device *dev =3D &epf->dev; + int ret; + + switch (val) { + case CORE_INIT: + epf_bar->phys_addr =3D epf_mhi->mmio_phys; + epf_bar->size =3D epf_mhi->mmio_size; + epf_bar->barno =3D info->bar_num; + epf_bar->flags =3D info->epf_flags; + ret =3D pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "Failed to set BAR: %d\n", ret); + return NOTIFY_BAD; + } + + ret =3D pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, + order_base_2(info->msi_count)); + if (ret) { + dev_err(dev, "Failed to set MSI configuration: %d\n", ret); + return NOTIFY_BAD; + } + + ret =3D pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, epf->head= er); + if (ret) { + dev_err(dev, "Failed to set Configuration header: %d\n", ret); + return NOTIFY_BAD; + } + + break; + case LINK_UP: + mhi_cntrl->mmio =3D epf_mhi->mmio; + mhi_cntrl->irq =3D epf_mhi->irq; + mhi_cntrl->mru =3D info->mru; + + /* Assign the struct dev of PCI EP as MHI controller device */ + mhi_cntrl->cntrl_dev =3D epc->dev.parent; + mhi_cntrl->raise_irq =3D pci_epf_mhi_raise_irq; + mhi_cntrl->alloc_map =3D pci_epf_mhi_alloc_map; + mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; + mhi_cntrl->read_from_host =3D pci_epf_mhi_read_from_host; + mhi_cntrl->write_to_host =3D pci_epf_mhi_write_to_host; + + /* Register the MHI EP controller */ + ret =3D mhi_ep_register_controller(mhi_cntrl, info->config); + if (ret) { + dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); + return NOTIFY_BAD; + } + + epf_mhi->mhi_registered =3D true; + break; + case LINK_DOWN: + if (epf_mhi->mhi_registered) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered =3D false; + } + + break; + case BME: + /* Power up the MHI EP stack if link is up and stack is in power down st= ate */ + if (!mhi_cntrl->enabled && epf_mhi->mhi_registered) { + ret =3D mhi_ep_power_up(mhi_cntrl); + if (ret) { + dev_err(dev, "Failed to power up MHI EP: %d\n", ret); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered =3D false; + return NOTIFY_BAD; + } + } + + break; + default: + dev_err(&epf->dev, "Invalid MHI EP notifier event: %d\n", epf_mhi->event= ); + return NOTIFY_BAD; + } + + return NOTIFY_OK; +} + +static int pci_epf_mhi_bind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + struct pci_epc *epc =3D epf->epc; + struct platform_device *pdev =3D to_platform_device(epc->dev.parent); + struct device *dev =3D &epf->dev; + struct resource *res; + int ret; + + if (WARN_ON_ONCE(!epc)) + return -EINVAL; + + /* Get MMIO base address from Endpoint controller */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); + epf_mhi->mmio_phys =3D res->start; + epf_mhi->mmio_size =3D resource_size(res); + + epf_mhi->mmio =3D ioremap_wc(epf_mhi->mmio_phys, epf_mhi->mmio_size); + if (IS_ERR(epf_mhi->mmio)) + return PTR_ERR(epf_mhi->mmio); + + ret =3D platform_get_irq_byname(pdev, "doorbell"); + if (ret < 0) { + dev_err(dev, "Failed to get Doorbell IRQ\n"); + iounmap(epf_mhi->mmio); + return ret; + } + + epf_mhi->irq =3D ret; + + epf->nb.notifier_call =3D pci_epf_mhi_notifier; + pci_epc_register_notifier(epc, &epf->nb); + + return 0; +} + +static void pci_epf_mhi_unbind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; + struct pci_epf_bar *epf_bar =3D &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + struct pci_epc *epc =3D epf->epc; + + pci_epc_unregister_notifier(epc, &epf->nb); + + /* + * Forcefully power down the MHI EP stack. Only way to bring the MHI EP s= tack + * back to working state after successive bind is by getting BME from hos= t. + */ + if (epf_mhi->mhi_registered) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + epf_mhi->mhi_registered =3D false; + } + + iounmap(epf_mhi->mmio); + pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); +} + +static int pci_epf_mhi_probe(struct pci_epf *epf, const struct pci_epf_dev= ice_id *id) +{ + struct pci_epf_mhi_ep_info *info =3D (struct pci_epf_mhi_ep_info *) id->d= river_data; + struct pci_epf_mhi *epf_mhi; + struct device *dev =3D &epf->dev; + + epf_mhi =3D devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL); + if (!epf_mhi) + return -ENOMEM; + + epf->header =3D info->epf_header; + epf_mhi->info =3D info; + epf_mhi->epf =3D epf; + + mutex_init(&epf_mhi->lock); + + epf_set_drvdata(epf, epf_mhi); + + return 0; +} + +static const struct pci_epf_device_id pci_epf_mhi_ids[] =3D { + { + .name =3D "sdx55", .driver_data =3D (kernel_ulong_t) &sdx55_info, + }, + {}, +}; + +static struct pci_epf_ops pci_epf_mhi_ops =3D { + .unbind =3D pci_epf_mhi_unbind, + .bind =3D pci_epf_mhi_bind, +}; + +static struct pci_epf_driver pci_epf_mhi_driver =3D { + .driver.name =3D "pci_epf_mhi", + .probe =3D pci_epf_mhi_probe, + .id_table =3D pci_epf_mhi_ids, + .ops =3D &pci_epf_mhi_ops, + .owner =3D THIS_MODULE, +}; + +static int __init pci_epf_mhi_init(void) +{ + return pci_epf_register_driver(&pci_epf_mhi_driver); +} +module_init(pci_epf_mhi_init); + +static void __exit pci_epf_mhi_exit(void) +{ + pci_epf_unregister_driver(&pci_epf_mhi_driver); +} +module_exit(pci_epf_mhi_exit); + +MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); --=20 2.25.1