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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:53 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 1/8] riscv: dts: microchip: remove icicle memory clocks Date: Sat, 30 Apr 2022 14:09:16 +0100 Message-Id: <20220430130922.3504268-2-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The clock properties in the icicle kit's memory entries cause dtbs_check errors: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@8000= 0000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' Get rid of the clocks to avoid the errors. Reported-by: Palmer Dabbelt Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle k= it device tree") Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 3392153dd0f1..c71d6aa6137a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -32,14 +32,12 @@ cpus { ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x2e000000>; - clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; =20 ddrc_cache_hi: memory@1000000000 { device_type =3D "memory"; reg =3D <0x10 0x0 0x0 0x40000000>; - clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; }; --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF80BC433EF for ; Sat, 30 Apr 2022 13:13:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382728AbiD3NQa (ORCPT ); Sat, 30 Apr 2022 09:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380509AbiD3NQS (ORCPT ); Sat, 30 Apr 2022 09:16:18 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5406082D31 for ; Sat, 30 Apr 2022 06:12:56 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id k2so14050735wrd.5 for ; Sat, 30 Apr 2022 06:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D3SEdr+fxIa6eNX5euS5Om6MuK6d2iGlkw5zs0H/ONs=; b=SkmHarr4ODHRRfHsVgW+WUZyogxa7T/pT1YaBfhU7ZFrtvTjXUbrQfqi/OyqAAvPlx WLvmoOBPYswSby7Wlf4NKPOMi1bPXU/vk5A092djDYYM17RPJNBliiwtkQqLd7vrKi1Y tfKnWH2Pz1C8DBZfrsckNoKk6XJzxqM6iFAdbKJwpdpDJtLXEokZPRoZsLVyhs0LVKH0 fMd977IxvpOH5iDbZnz+tfT0ptHDjlExVzX5wEPxDCKVcSBgj7axOfFVEZA1s618hH5n DhwV7NhonaR9XLG13BEBpWWV3dvTJ1Wn9JsTRs6xn7YnHdYLGSYFCoEGkrUhrO44/3EA 7NpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D3SEdr+fxIa6eNX5euS5Om6MuK6d2iGlkw5zs0H/ONs=; b=bxbg532JG320Svqf+fYHubIN1T8OXS4hcO/SDJt67H3hiKT3znk2Wz7jkwVaWv6dyx m4wL7kREArCuqZMi97PjQQNO3fItj56yP8AmKnppXo67PymYN/oZa9bd8lQgNtbpmTDD UdGNrFdI/xdDQsg9b0aiwBfzGfoQ5eC2pEXDLJWW/pA0glJoeTL3HNjHpm64Tpg2D5LU q3jYkHhPr5uTNi7fAep/Ch2oT7jzDKJ7xhuWr42W1zcV6zdsdS27He3ZQvA21GI23xuP yVarhig0jsFNbgyesLLatS8vyU5ElXv+2eRIUpEM5kwBtxb3ygAJWkFCKtnaJ0ji5Pxr NfZw== X-Gm-Message-State: AOAM530HAR4RbYREgwNkoTwFm5XlphjE6vm8STw4WX2IChUgpjvTiX4X tGEIPyzts6T8L4l79a0eEHjNeg== X-Google-Smtp-Source: ABdhPJzMz8I3WPzdOc01vlw14L5jOcx76muJKJWSX4TSNP+dxUOGGZG58Ebk8tPI/T3KW4pjmDxb3g== X-Received: by 2002:a05:6000:18c9:b0:203:fb67:debe with SMTP id w9-20020a05600018c900b00203fb67debemr3004347wrq.494.1651324374961; Sat, 30 Apr 2022 06:12:54 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:54 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Rob Herring , Conor Dooley Subject: [PATCH v2 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Date: Sat, 30 Apr 2022 14:09:17 +0100 Message-Id: <20220430130922.3504268-3-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The MPFS system controller has no registers of its own, so move it out of the soc node to avoid dtbs_check warnings: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontro= ller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]]= , 'status': ['okay']} should not be valid under {'type': 'object'} Reported-by: Palmer Dabbelt Suggested-by: Rob Herring Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle = kit device tree") Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 746c4d4e7686..bf21a2edd180 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -146,6 +146,11 @@ refclk: mssrefclk { #clock-cells =3D <0>; }; =20 + syscontroller: syscontroller { + compatible =3D "microchip,mpfs-sys-controller"; + mboxes =3D <&mbox 0>; + }; + soc { #address-cells =3D <2>; #size-cells =3D <2>; @@ -446,10 +451,5 @@ mbox: mailbox@37020000 { #mbox-cells =3D <1>; status =3D "disabled"; }; - - syscontroller: syscontroller { - compatible =3D "microchip,mpfs-sys-controller"; - mboxes =3D <&mbox 0>; - }; }; }; --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 168D2C433FE for ; Sat, 30 Apr 2022 13:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382737AbiD3NQd (ORCPT ); Sat, 30 Apr 2022 09:16:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382644AbiD3NQU (ORCPT ); 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:55 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Sat, 30 Apr 2022 14:09:18 +0100 Message-Id: <20220430130922.3504268-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi =3D> mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts =3D> mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi =3D> mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi =3D> mpfs= -fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts =3D> m= pfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi =3D> mpfs.dtsi} = (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arc= h/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ =20 /dts-v1/; =20 -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" =20 /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" =20 / { #address-cells =3D <2>; --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 656AAC433FE for ; Sat, 30 Apr 2022 13:13:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382743AbiD3NQf (ORCPT ); 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:57 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 4/8] dt-bindings: riscv: microchip: document icicle reference design Date: Sat, 30 Apr 2022 14:09:19 +0100 Message-Id: <20220430130922.3504268-5-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a compatible for the icicle kit's reference design. This represents the FPGA fabric's contents & is versioned to denote which release of the reference design it applies to. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/microchip.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 3f981e897126..c9d8fcc7a69e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,10 +17,13 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,mpfs + - items: + - const: microchip,mpfs-icicle-reference-rtlv2203 =20 additionalProperties: true =20 --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 700D9C433F5 for ; Sat, 30 Apr 2022 13:13:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382751AbiD3NQj (ORCPT ); Sat, 30 Apr 2022 09:16:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382698AbiD3NQW (ORCPT ); Sat, 30 Apr 2022 09:16:22 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C85B83016 for ; Sat, 30 Apr 2022 06:13:00 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id i5so14024256wrc.13 for ; Sat, 30 Apr 2022 06:13:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l7Rc5OS3t5jH6ZKfP/hcCEMnf9UpuWYMdCo25UYCckg=; b=X9thXVlmcxmH1PE12wviFkCqeB+MZYit8NQzf7UG+cKxQdSXGYfNvp7epUsMhphPqw dgI0WpBh0Q16kC+ZyLeT3gTwo77RcBTLZdMSrV2LfXYUCnDCz9trJlWx4B6qkjb3UKcH /kwL7Y3RvEE71ZY7lCZrSxmxURm6ziJ/ptAjeQSh8WkExAGRC2DdTIw6RyuHUA0qIUQD aeDj/HfU6moCSAkfL+R0hj+IeFufhNBoyleaw0kmPvK2aA4eotgsq+ljwATz/XNDZBJO KyekhtyA4ptf7zq5UJYpNJUJHZB3KjExiMKo8fb/9Cidq4B5IFsDPeuwpSZ5mq6zs5zH vwag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l7Rc5OS3t5jH6ZKfP/hcCEMnf9UpuWYMdCo25UYCckg=; b=cqt2u4Y0bTfK19MIXPqOBAnISTgMOhM0fAFIlJ/lLGQKgsELDzr2G8Ol6Udhy9bGwG LKUVk/SYaJJ9MU2NMW4Oxo9Fqt+55D7PlLTA8VIlRyJdVGL4OjlpfMKDvGDSiEZnYDgg JPxh2DEfY8f1s5uJvu2I1cR3lOGXUwKpyF4iKMsS1pJOyDkWCkSLzu3lb87tyBfRDU8Z Z3n++mVUXmX00+siR9FPPuIdwu31MEIkrmo9bmG0CSAkgmRQzirxMwT6QwWBIyphrL5q xRluIUgqMWC0GlbDukgrOFktKh2JHjRqqGh0KYwJJAaxpd2nrd32imvUgMbqliMqnqaQ K+Sw== X-Gm-Message-State: AOAM5319zRk1Bmx+HSowWSAOH4slc20KB+qShvnD7UWhreMdDUxUgDVV BLM71wgbzNEnzg0fyxeQ6EzfKMy/DU5dODpE X-Google-Smtp-Source: ABdhPJwfVdzniLJsxd2OkH7C13/Hxoma+jQxRAs+vM3HMP4eVaImC/GGXFNkSLzzDuWaaC2VqGfS6A== X-Received: by 2002:adf:e942:0:b0:20a:c907:90d6 with SMTP id m2-20020adfe942000000b0020ac90790d6mr3047537wrn.163.1651324378647; Sat, 30 Apr 2022 06:12:58 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:58 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 5/8] riscv: dts: microchip: make the fabric dtsi board specific Date: Sat, 30 Apr 2022 14:09:20 +0100 Message-Id: <20220430130922.3504268-6-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine currently since there is only one board with this SoC upstream. However if another board was added, it would include the fabric contents of the Icicle Kit's reference design. To avoid this, rename mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts rather than mpfs.dtsi. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- .../microchip/{mpfs-fabric.dtsi =3D> mpfs-icicle-kit-fabric.dtsi} | 2 ++ arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 - 3 files changed, 3 insertions(+), 1 deletion(-) rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi =3D> mpfs-icicle-ki= t-fabric.dtsi} (93%) diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/bo= ot/dts/microchip/mpfs-icicle-kit-fabric.dtsi similarity index 93% rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index ccaac3371cf9..7ee592e78c05 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { + compatible =3D "microchip,mpfs-icicle-reference-rtlv2203"; + core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x41000000 0x0 0xF0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 84b0015dfd47..739dfa52bed1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -4,6 +4,7 @@ /dts-v1/; =20 #include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" =20 /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index cc3386068c2d..695c4e2807f5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,6 @@ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "mpfs-fabric.dtsi" =20 / { #address-cells =3D <2>; --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF027C433FE for ; Sat, 30 Apr 2022 13:13:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382698AbiD3NQl (ORCPT ); Sat, 30 Apr 2022 09:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382699AbiD3NQW (ORCPT ); Sat, 30 Apr 2022 09:16:22 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31FB282D31 for ; Sat, 30 Apr 2022 06:13:01 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id o12-20020a1c4d0c000000b00393fbe2973dso7489485wmh.2 for ; Sat, 30 Apr 2022 06:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xYRDXpY3Iw2Mp2L+0vKKbLbTXTTo1snejpw1fL9RgNM=; b=U53G3o1zO2TfWVlvRkK8i7XxN1whWKxR20syfYHosot0Pj91VzSi2LEyZqdDh7kfrq ESp4RBFRHnhhskiNmRD0FQKf6Rtu9nmKrIFYAqzhmJ8/+4/60Th4hpZyD9Syi36FgMO4 gROxG2a2Es4t3+lm80t5o+PqPMvWZ0J+jEKDboaBDO8QVWYVmqH7rGMwXwesYGbz9HYf Oi5chDxwdMKBkgf+reDZAEeg9+SCarqF6U7DVhUt6lEqCssDu4HlxGgiiJjk/zKAKWeE nhIcoJlms6omOF0Z5ScPUvuhmiPG8Lii5VTQC57WigTFac9JUR1kOn6++7lZ4+14BDIW zQaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xYRDXpY3Iw2Mp2L+0vKKbLbTXTTo1snejpw1fL9RgNM=; b=Dvt92/RrWSyE+PCLzVV0NcCcFWzyRUnyLZXSqacgS2Gm3ImFwETx22zQ1iVlvXkaT4 YfRERennkJPLFJGP5PCzhLTUTEkrxXAqFzv79epnT9BVQIVA4R88cnmqipuraci/yFzl ouXkYw5pH4dOz8yBftv/RGadWHXHD0xDYJeHgIzRH00NmjycKEXY6GQW1yLUmUVU8LQ4 DTs2rNl8o48UHLPAmXH4wB4bgCVpnZhj58zPXMQM3dysPyr4v9A68/yY4DUMPYjj4yI7 3qvGNGenfjygefeNGKK2NgBsLaDtRxuQMws7bPEPdXB1qN/VNK/o1CO74VMhUpbrWYet npDw== X-Gm-Message-State: AOAM530KB6+wb1r/RcL6uOsgAkfWO2mB/YRHSnRj7Akvxn0b73149aZ5 /TtPkopgUSwfOMetSYkOrWfk0w== X-Google-Smtp-Source: ABdhPJx5TybxW4mPhyRc1B07zUGZnDh+cnuJd20nySqJGiwWmYa+KtUc1qkRi3Adv3YqzZXrvWGq6A== X-Received: by 2002:a05:600c:19c6:b0:392:926e:5023 with SMTP id u6-20020a05600c19c600b00392926e5023mr7558948wmq.110.1651324379745; Sat, 30 Apr 2022 06:12:59 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:59 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Date: Sat, 30 Apr 2022 14:09:21 +0100 Message-Id: <20220430130922.3504268-7-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of high-performance DSP and FPGA processor boards and I/O modules. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 01430973ecec..1d47a38c2a2e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1197,6 +1197,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sundance,.*": + description: Sundance DSP Inc. "^sunplus,.*": description: Sunplus Technology Co., Ltd. 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:13:00 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Date: Sat, 30 Apr 2022 14:09:22 +0100 Message-Id: <20220430130922.3504268-8-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a binding for the Sundance Polarberry board. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index c9d8fcc7a69e..7f9296991a56 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - microchip,mpfs-icicle-kit + - sundance,polarberry - const: microchip,mpfs - items: - const: microchip,mpfs-icicle-reference-rtlv2203 --=20 2.36.0 From nobody Mon Jun 15 10:16:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD128C433EF for ; Sat, 30 Apr 2022 13:13:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379430AbiD3NQr (ORCPT ); Sat, 30 Apr 2022 09:16:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382716AbiD3NQZ (ORCPT ); Sat, 30 Apr 2022 09:16:25 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFEF382D23 for ; Sat, 30 Apr 2022 06:13:03 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id e2so14045328wrh.7 for ; Sat, 30 Apr 2022 06:13:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5BDpWQnhgIgr6un23nDrSpiOtZvz8Bid/I/OR7bUXBg=; b=SlG01VQDuxSxdPy8VMdSmhznbCqvszukWiPbnb3FyMJXyipQCen4pPNN94SZggFHBR Khv8/STbGnjHar2BvWcMavvK+nWHNx4/vLDyhSmKF1w724sCgNYYjRtvGQEwbJnjRTnI SsCBr2A7+YyYPewKZbXskdXlem0Tx0wsiuw0sTypY8DTgT8EJBv4p9x1e8jA5Gfnv02n YJkDQH5oaeAP9EjFiV4q4h3/aZgXkSeR+WJ8b1+dsG8AI3hq2n081ke8V2vUU6UX3Evk bcIsgmakIN3lF27zSgQVwm4S1yL2dE9uKV+ImcWStQjPfAsY4OfloiF484vCfyGRcmmN 27hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5BDpWQnhgIgr6un23nDrSpiOtZvz8Bid/I/OR7bUXBg=; b=4q0UfRoVVSZj6VkYtLdZQukK/3Tw6r2lFZ5nVm60+3UG+GNmHXwC+EmyeIbPmtoKZd vkExvs1Bq51urtOI8D14V/2r1bZn2yrYP3/j+2p3ZSSIuvLRaaau1nyhoaWwYWEHYn4D a+Iof0HsHT3mB1CVPoEf+CgNsbxQArVr7ROG2yg+4GY2ZkTbgTBvMIpUF8MEzENIzUfn AYNuOgecA7lglGNDHuws6Bp/u1q+MswoYbekytBf5+EocoPGStVlE7sZqQzb2wo2J+OR Jia97sXDdys3+jsLa9hwsHB0NXVCVZ0Fq/ZmM83kDPvNDjfKD1VznhIuWuaplAM72s3g EQzQ== X-Gm-Message-State: AOAM531dVDk2k3SIo9nSv79I6OwkBur/W6RBhCtAquIovh01eRPKV3zS twiDAHU/c/0k4oObonPq6kGHQQ== X-Google-Smtp-Source: ABdhPJzGWomTAcKYy8TjYtr6rv50Fq2fu7zj7OZUjLU0Hb9oHeoK5Z30y35gwYrn24hopjf/OilbsA== X-Received: by 2002:a05:6000:1689:b0:20c:4fa1:ffb7 with SMTP id y9-20020a056000168900b0020c4fa1ffb7mr3111374wrd.48.1651324382219; Sat, 30 Apr 2022 06:13:02 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:13:01 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 8/8] riscv: dts: microchip: add the sundance polarberry Date: Sat, 30 Apr 2022 14:09:23 +0100 Message-Id: <20220430130922.3504268-9-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dt= si create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv= /boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..96ec589d1571 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model =3D "Sundance PolarBerry"; + compatible =3D "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 =3D &mmuart0; + ethernet0 =3D &mac1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x2e000000>; + status =3D "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x00000000 0x0 0xC0000000>; + status =3D "okay"; + }; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&mmuart0 { + status =3D "okay"; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay =3D <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@5 { + reg =3D <5>; + ti,fifo-depth =3D <0x01>; + }; + phy0: ethernet-phy@4 { + reg =3D <4>; + ti,fifo-depth =3D <0x01>; + }; +}; + +&mac0 { + status =3D "disabled"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; +}; + +&rtc { + status =3D "okay"; +}; + +&mbox { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; --=20 2.36.0