From nobody Mon Jun 15 10:18:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2C5AC433EF for ; Fri, 29 Apr 2022 21:44:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239082AbiD2VsB (ORCPT ); Fri, 29 Apr 2022 17:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238929AbiD2Vrw (ORCPT ); Fri, 29 Apr 2022 17:47:52 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07702D95CC for ; Fri, 29 Apr 2022 14:44:31 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id h12so8212328plf.12 for ; Fri, 29 Apr 2022 14:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G+b/5mZlFuHtU2XDozomo84+nsQCdCx5HIlm6/xmsSw=; b=Lk7L4IygC+lKFXqlatdS4sTNMrlHQVhH4QHq/GcQWEOUR6yjyfqapWDnENI0syOUvP Pzv1QdFuuw86sXzVfRNyM1MpUmh2rZFLO84tTRpO1RKk4nE8A79vzXTk6vg+/EpXwhl3 GhmbUD8NL9c5bj5oiGDKHapJL4bLvGZP8hYJKNjbpf4YwyFIV/A704gevl80qAnna8dw 6z/7oAuCmHf9MYIdniHiHYo+yFKWsKFck1vKvl2O02zcet1rDAya5x/AlXPuy64iE0ev rU9n9WSGcs5Bhnby8BeF5QDgxgMy2rAenTRY41M2Y2Y/gvok6CsFMUe1AndjZKQUXG74 hapA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G+b/5mZlFuHtU2XDozomo84+nsQCdCx5HIlm6/xmsSw=; b=lsBzWOxOT5DR8L1yt5nhFh0NGcvGDSfV2OI+RC5Emd64ZYLYyUUcVf0F5v7rMUoPmG +29nB0Mv/Tno+chwQvTs3lvMLs49OyzQDGhJF68rZZjs/iSPuE6UDqSAA3ARZaZaPyXj J4eAB40isQZzAaP8eZ4Fq1EeCSXX8o8dEvFwcg3lO15AhyzvtkX/TxRT25VG8CtrLuX3 8KCxkY9azVK1uOn4ziXzZkm2sa48vENZpOWxudQqVR8nmGWmPg6BIimNwv5rOUi2axIA 5VByVQpXzR5Y+H7jjmdBg5ixi3iYAqMBHlCk8oOjXbRDcdfuKTs2v02sH8aRghJQG6sp z8BA== X-Gm-Message-State: AOAM531B7I9Oxi6IgPEsWGWPKqm6hxo/5mydzCkRJD607m2GhVSavve3 j3N0qlcQVkRXoZevqnIO35gxbQ== X-Google-Smtp-Source: ABdhPJwx9C+GPVAfhw27WAXdFgQUSO3zeFDI+lxbdL2k29gyzRGPqHdj1Zd+ey7umQd4Li4UnuYzKw== X-Received: by 2002:a17:903:1252:b0:154:ca85:59a0 with SMTP id u18-20020a170903125200b00154ca8559a0mr1273711plh.169.1651268670521; Fri, 29 Apr 2022 14:44:30 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id fv12-20020a17090b0e8c00b001cd4989fed0sm15271086pjb.28.2022.04.29.14.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:44:30 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, Rob Herring Subject: [PATCH 1/3] arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes Date: Sat, 30 Apr 2022 03:14:18 +0530 Message-Id: <20220429214420.854335-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214420.854335-1-bhupesh.sharma@linaro.org> References: <20220429214420.854335-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'interconnect-names' used for sdhci nodes. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index 7f875bf9390a..db18b35d4a7d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1285,6 +1285,7 @@ sdhc_2: sdhci@c084000 { =20 interconnects =3D <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; + interconnect-names =3D "sdhc-ddr","cpu-sdhc"; operating-points-v2 =3D <&sdhc2_opp_table>; =20 pinctrl-names =3D "default", "sleep"; @@ -1337,7 +1338,7 @@ sdhc_1: sdhci@c0c4000 { =20 interconnects =3D <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; - interconnect-names =3D "sdhc1-ddr", "cpu-sdhc1"; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; operating-points-v2 =3D <&sdhc1_opp_table>; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc1_state_on>; --=20 2.35.1 From nobody Mon Jun 15 10:18:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E1CC433FE for ; Fri, 29 Apr 2022 21:44:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239021AbiD2Vr7 (ORCPT ); Fri, 29 Apr 2022 17:47:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238760AbiD2Vrx (ORCPT ); Fri, 29 Apr 2022 17:47:53 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3210DB0F1 for ; Fri, 29 Apr 2022 14:44:33 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id n14so1352224plf.3 for ; Fri, 29 Apr 2022 14:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3bM9obd8ZUcuxP0enz30vvUZW9ZRPh152lks3wc9yEE=; b=jx/9RFouIHwDBbb5ltParsJO8zX0BXtnSKD44EmOWMp7kf4ItGUYTnPJxMQxvAMJti l1vXQBN4cx1+gql8oX4TyH8vmJavYdYs/533vJ87dfxi5K6G92ypZx4C5R+sMzLbyNot BHn9RIJavZM332RZWSSP/EiVQgdziwCoFMZTYFzzRvqc+TtV8t3sKe9PiRA6BdPvYE8I Sw80enWWUtwh67pOWxl3Q4mPvWgWmQIXIUcCV5E3ixX+bH8xsJ6aCeAR3mEN6Rdw5lIa ki5V5dRe0uH6OC/NdkQXn5oqOGKMaw9891eLUSfSDyFr9Lgemhv7j74ZsLXWZj75PCfH y4DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3bM9obd8ZUcuxP0enz30vvUZW9ZRPh152lks3wc9yEE=; b=kYXuUhGnZhN/nraI46IOR8W5is/DRxeaDVreVCF76lmx8j4uSgs2N9ea69HOs9/JRM XACeu9xpFrIiY4jewUR6up7TURafPXMyd+zHIpB0ko6sZ10GAlESPDtcTb98Mptsp1jm 3KlbogCi55oBe4wk8i3J+qGNg6Es0wDwOdKd0y8QPCe8Fl9spNBasmPeqIO5Tn3odxXh YwqRKNjaWTSoiIAXTPdI9Gdz0HPDHtdiJ7+SOayjCtDHdJCVwjfjPjE2hIvLx62ZUSGB ruuDIQaFzP3b5LJLt3KVvR3kVVeE0mph65fEyZlttjERKjRyqbapO8Tif//0I5HdQfuG mqtA== X-Gm-Message-State: AOAM531zlQIrRADa4dGM4p5JMvgtpe4hsBpWPvy/wBMHC4obCsL5tVFS haTB1eB/j4WTpXbM7JC5MK1XjQnT4pmUnQ== X-Google-Smtp-Source: ABdhPJwLfzQU028dFeAhHJWHK0rfrF/8yy59TSbfdsh5ltBwLCdTmQIhgdRePazCnUeMWPW5UEx4sQ== X-Received: by 2002:a17:902:ce81:b0:15d:29ba:7808 with SMTP id f1-20020a170902ce8100b0015d29ba7808mr1061485plg.153.1651268673158; Fri, 29 Apr 2022 14:44:33 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id fv12-20020a17090b0e8c00b001cd4989fed0sm15271086pjb.28.2022.04.29.14.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:44:32 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, Rob Herring Subject: [PATCH 2/3] arm64: dts: qcom: Fix node names for sdhci 'opp-table' nodes (across dts files) Date: Sat, 30 Apr 2022 03:14:19 +0530 Message-Id: <20220429214420.854335-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214420.854335-1-bhupesh.sharma@linaro.org> References: <20220429214420.854335-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with node names for sdhci 'opp-table' nodes, as it doesn't seem to like any 'preceding text or numbers' before 'opp-table' pattern in the node names. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 86175d257b1e..b6df3186e94c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -725,7 +725,7 @@ sdhc_1: sdhci@7c4000 { =20 status =3D "disabled"; =20 - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table-sdhc1 { compatible =3D "operating-points-v2"; =20 opp-100000000 { @@ -2609,7 +2609,7 @@ sdhc_2: sdhci@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table-sdhc2 { compatible =3D "operating-points-v2"; =20 opp-100000000 { diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index fb1a0f662575..87a5d72b2ca0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -497,7 +497,7 @@ sdhc_1: sdhci@7c4000 { =20 status =3D "disabled"; =20 - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table-sdhc1 { compatible =3D "operating-points-v2"; =20 opp-19200000 { @@ -941,7 +941,7 @@ sdhc_2: sdhci@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table-sdhc2 { compatible =3D "operating-points-v2"; =20 opp-100000000 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 2700a8145cb9..e265d61f7c05 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3563,7 +3563,7 @@ sdhc_2: sdhci@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-19200000 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index dc2562070336..5ca16f76ddeb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2937,7 +2937,7 @@ sdhc_2: sdhci@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-19200000 { --=20 2.35.1 From nobody Mon Jun 15 10:18:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE007C433F5 for ; Fri, 29 Apr 2022 21:44:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239102AbiD2VsE (ORCPT ); Fri, 29 Apr 2022 17:48:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238913AbiD2Vrz (ORCPT ); Fri, 29 Apr 2022 17:47:55 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AAF2D95FF for ; Fri, 29 Apr 2022 14:44:36 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id cx11-20020a17090afd8b00b001d9fe5965b3so9688049pjb.3 for ; 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Fri, 29 Apr 2022 14:44:35 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id fv12-20020a17090b0e8c00b001cd4989fed0sm15271086pjb.28.2022.04.29.14.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:44:35 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, Rob Herring Subject: [PATCH 3/3] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes Date: Sat, 30 Apr 2022 03:14:20 +0530 Message-Id: <20220429214420.854335-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214420.854335-1-bhupesh.sharma@linaro.org> References: <20220429214420.854335-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with ordering of 'clocks' & 'clock-names' for sdhci nodes: arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:0: 'iface' was expected arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:1: 'core' was expected arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:2: 'xo' was expected Fix the same by updating the offending 'dts' files. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/msm8994.dtsi | 14 +++++++------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sdm630.dtsi | 14 ++++++++------ 7 files changed, 40 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index 943243d5515b..8cd4c1fbca17 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -384,10 +384,10 @@ sdhc_1: sdhci@7824900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&xo>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names =3D "xo", "iface", "core"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names =3D "iface", "core", "xo"; max-frequency =3D <384000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 05472510e29d..76bbf7984a62 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1472,10 +1472,10 @@ sdhc_1: sdhci@7824000 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; mmc-ddr-1_8v; bus-width =3D <8>; non-removable; @@ -1490,10 +1490,10 @@ sdhc_2: sdhci@7864000 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index 367ed913902c..3c0df737fa92 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -467,10 +467,10 @@ sdhc1: sdhci@f9824900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; @@ -490,10 +490,10 @@ sdhc2: sdhci@f98a4900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; =20 pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index bc446c6002d0..3d6b88aedff2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -798,10 +798,10 @@ sdcc1: sdcc@7804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index b6df3186e94c..8b4d7d83e582 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -704,10 +704,10 @@ sdhc_1: sdhci@7c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; @@ -2594,10 +2594,10 @@ sdhc_2: sdhci@8804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 interconnects =3D <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index ccf5e95071f9..11270d90e1cc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -873,10 +873,10 @@ sdhc_1: sdhci@7c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; @@ -2950,10 +2950,10 @@ sdhc_2: sdhci@8804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index db18b35d4a7d..65c4e955893b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1278,10 +1278,12 @@ sdhc_2: sdhci@c084000 { interrupt-names =3D "hc_irq", "pwr_irq"; =20 bus-width =3D <4>; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; + =20 interconnects =3D <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; @@ -1330,11 +1332,11 @@ sdhc_1: sdhci@c0c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names =3D "core", "iface", "xo", "ice"; + clock-names =3D "iface", "core", "xo", "ice"; =20 interconnects =3D <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; --=20 2.35.1