From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C15B8C4321E for ; Fri, 29 Apr 2022 17:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236329AbiD2RYp (ORCPT ); Fri, 29 Apr 2022 13:24:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236397AbiD2RYa (ORCPT ); Fri, 29 Apr 2022 13:24:30 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7192051E59; Fri, 29 Apr 2022 10:21:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1651252837; bh=n+fYbs1revJrCSfeZGgMBlQnPyJ+1djPv/sSqDYSh2M=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=PLZ4JQRYGDdEFKjhek+GvIAHzcaErcttl2lIEORTdJhliutBiTJTgwvytTYmfljkJ 6bDKgIwQw/EPjBDGh9Wlz2ZYCoevf9lqi1zFIqkHcab+gD6ot/YKU+TXRlIi6HT2RV JgNNjjVkM1YCX1I1JwFaKPThaBtPvCmVUdx/8fb8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MFKKh-1neAlY3EL3-00Flrr; Fri, 29 Apr 2022 19:20:37 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 1/7] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 29 Apr 2022 19:20:24 +0200 Message-Id: <20220429172030.398011-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:p6rSWqprkd/QaVYN6U31GBpxz/6hVLr3+Oe2BrJnZNSPt2M7+ap dIJpPkkVmy4PvlULhC3lfyadwa2uR7z0xdBxu08izsSoANi5UpMgvVG3M8758BuTEdEqfDp SXMWPYfeGd3DwBI7KsQgFo4+mFaIVJDZP/XgzcRdp0C74wSDFrnCXaLfDN9aRzOOon2Hvqi Gtneq4HkjbdpmIP2StEeQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:p+Br6C7z6cY=:5VhrNBlpnMvwTXnoJIWo0M fsPgh8JUsRjopAOMXm+IqN7CIaYvdtSpvvOu3Yvme81d8vAX152vwnm3ydnmYWiD+1oVzInDH PvwYxYc0oZJTbEHyRlCAgzlShAizuPb6ipvCQY654AnqONXE/xF2XlBQkFxvBDKJntb1PtNUZ B9+3Xf3l8crGm/4s4YONxnsK2ALiQ8RgDwOwLNv/d1O1EZB7owOzOWXP9GItnCCBY02MKGIr6 az8S8CGf9OI9ePp3np7+LpOk395xdV8rGU1jsET5tkOAU7su5yYropkAlX4r1gBP0hHwDun1t lTrKMEHAF7WyruQ+Hv6jm0+HPieAKaWo4KLAqRm4SH0COU55hdf9pgg3IuoJWI13NnCVOh69j gnDTKzZDXGJiNGpSWmDx/V94C1R2u8Hrp75utgGstsAcavvuYnMJEjewD615sqFQ8r2BPQXQp 7+ba2m83qDCt7cZGwRnNbAVd1X02LVmmsSslAMi6HBA8dNl1OeIq91v2r4158KUyVJaxnfRQg P2SyWpWiYCdHQUFWFLngCMFgDRE80/Ix0ncpqbQZK3d9xOWrVA1q9h3Rq50agWsv5lV/i4JJ1 o38OsY41VaAP6/4NBHAIOBstQevqspfmH9bSUZ9Fl6n4AXNOfJBwp5y+e2pSA/YODpAygTHUd zN/72o3UsfA9lv0kkN21X8tlC0DvWrbSY6D0mQRK9SuWJIkf2Ke6XV1wQwMXtetjJZNw0kwOf KqfVjufYpwbtYCdindy99eV9xK5oyrWb8Wvbc/LAXv/MvYuFPgLaTi6eQI2wRv7/hcIuNmvjM oaBNO8GMZkIE0KKkjrkDFqwCeIxVenlh3ubWSLv/jkM/9buldVbIse1maMXAe2vhAUEzAz/do 0MNva4VMUQqlyC6P2NczzLlNPeuYkk/kt1jaohguMmHDVGyO9Hd9A54cJBl5TPgZbU8y3Eg4E vsuqKDHPGtcDNPOWtXWOtxdLssivm/4nI/2Wh3MrPuWy6uaIhBGEbffqAjwHsZHZQoLr7o3rc l8vSZPMvFauIAvNj8m6LnfwyGorowL7HMe2GhXINK6iKgDKznyZmO+T+TXwNsWyhDiPsBgRi5 V1n3uMv0lbXoMM= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neusch=C3=A4fer Reviewed-by: Rob Herring --- v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.= yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD6D7C433EF for ; Fri, 29 Apr 2022 17:21:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236289AbiD2RYh (ORCPT ); Fri, 29 Apr 2022 13:24:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236057AbiD2RY3 (ORCPT ); Fri, 29 Apr 2022 13:24:29 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CADD64C790; Fri, 29 Apr 2022 10:21:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1651252840; bh=KjOTaewkXeg9gD63/HWGEfLtPHd2o/Nc1ZX9pL1ItJU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=fFKo+3FN3UNC4U+2YAFSv/d5O/JNFoCcTVYmlaK5MK5v6vvEtXWx+xJ38FybQNk8n pi7K5syL1mamdZl4Quns2rgkcxH/0y8KCi2IDGmQNgsP/ej60Q8cfRcViOv821f9jL sxrpMltzCuNOk0DtF+db46Fi/H6Uw+OtcMHlwi1w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MvK0X-1o2ZLN1Vx3-00rFqR; Fri, 29 Apr 2022 19:20:40 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 2/7] clocksource: timer-npcm7xx: Enable timer 1 clock before use Date: Fri, 29 Apr 2022 19:20:25 +0200 Message-Id: <20220429172030.398011-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:F0+IFMLwve1L01E5CbdzpXZxEC0gnGkE9a9+pZhDgs7EwhdNaGh E1hluldQg3kkl+1INd3E7S8dTQgQ9HPZR2BbRTxEokRuS3BFevdFBa13+ypjpPS6lKM/EdL 9piJW4rKikAiJZwMwKGIvJRj5ZQm7HdNQIF8NQe/EoGdcJN7Q0Hdu6h72LC1KRLn6/d4LtK NaXntm46PxSIKEGKff71A== X-UI-Out-Filterresults: notjunk:1;V03:K0:i9zb9H0jIH8=:GjPNtl7S/40sSf5720RMYP eT78eAyQB5ybkGXAP74BN0IdHf19AmQk16ZrbNCkPBc2jgUofVhI1gNCaQwLcZWmOqajQ02HP UDe+R7Om/NRe2Y93Q3j/NblA4AfQBgZg8pB2kn7CKcAWtOOpRsX+1WW/SQIcUgtRN3TCD6QkW RPQKtSdMbTxDVObbBakJP4yk2F8YjnZABQyF9YiY3c29GDlavTTPJT4U/BstLYVL7R3U9XCaj 75vW5TCFDZ3rjrkOweqwRR1X9Xu3X2TeZCDJM3JMy7JCsQCt7tRwqTtS1OLMBR7A1c9olYhXB WAHawMIrSiFnSAOa4eaXHOu4pv7GS6TZnwv1sht5Y2HCvncPKntmVjRiNqCyf/elrRDIchywb 1wKSbNNpYQtm5PYHNzX0m/eZjRd1wbYm2EbHrh+ZHge0GpjdC1OygAKqb77fg6oyTijkNvi8S xC6tsmbAHllH/S6gik7zOgUBtcrYDpSjtiS8fhARU6WWMztEBn1EQE8dmHEn+TT1qgK6U9TSw 5pydtrW1BQqaDJgOnfr7A0DkdsCk2P+gghsIm+sk3CKV2L2SEcrF5GC5O0ArLirb0KJNdE7s/ I736sLwQkscHcbEW4/+B1clyyzE6Hrk0GTWsKdf6sc28aXtoKcSmvcKmR6iq1nUvWZdpmQkDR PEFg79afpMOhljpt54QccOqjlan26P04dJpTlhTntnKnagUKhDz8xUuIuDoQPbdmKS+Y+RX3q y1ws/xCjVfZWebyd+lIKpxl0ewn0K3+snNQJPwVMdOjyOCa/UgbSGXokLHd/T0cs+7BUJrxiG t3WLwkn/Gd4H6T8djfPLqyV4PGtXoZf652RXJopHcNAg9WWMLaq7XRufq1uEGqplzgN8h57ul TAllRufMmrbelvcTHnZjORlg7IceaI2cRqZ60FYPnV+sk4cUHzisPGnhk9zLETMUqnj0JfPMM G4XnEsJ2ZMA9gGdGBKTNvniirSfL7Bx2udvV3uDLI1jZ//OsHn00n9H35Io+8B5bPr3U/2Xt0 OHIu9uEs5az8CG91t82K15C3Dkj1RP8IT+lStp9MZAfk9WTvzy6fU5xIftBdSmJFFPukL4ouS KuhLYz+pwn4q94= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neusch=C3=A4fer --- v2: - Provide context in pr_warn message v1: - https://lore.kernel.org/lkml/20220422183012.444674-3-j.neuschaefer@gmx.ne= t/ --- drivers/clocksource/timer-npcm7xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/time= r-npcm7xx.c index a00520cbb660a..9af30af5f989a 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,6 +188,7 @@ static void __init npcm7xx_clocksource_init(void) static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; ret =3D timer_of_init(np, &npcm7xx_to); @@ -199,6 +200,15 @@ static int __init npcm7xx_timer_init(struct device_nod= e *np) npcm7xx_to.of_clk.rate =3D npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); + /* Enable the clock for timer1, if it exists */ + clk =3D of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA854C433EF for ; Fri, 29 Apr 2022 17:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376602AbiD2RYt (ORCPT ); Fri, 29 Apr 2022 13:24:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235457AbiD2RYm (ORCPT ); Fri, 29 Apr 2022 13:24:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 693BA527F6; Fri, 29 Apr 2022 10:21:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1651252841; bh=IhOdbQHhR5x4m2YHZI3GQ3kZqNDq8I52f2wlB/H7xmQ=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=dA4cH0SDbhY7UYk9O9kn3Rwqm7xs44n0nL1OVpQtvTcXxiTqsuo/Rt4fI+B50M47A wW1hMSQlxpQ23uE0N53bUuxqy8jqu9v8ru5Pvd000/ow5s96FsuLOxWsvPMSIqnA9M I3URDEZpJhETZjK9I2rjEI3H07pf1C4z4vkSGG7w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MhU5b-1oP1uk2O5D-00egWU; Fri, 29 Apr 2022 19:20:41 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 3/7] watchdog: npcm: Enable clock if provided Date: Fri, 29 Apr 2022 19:20:26 +0200 Message-Id: <20220429172030.398011-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:66AxyOQT8oGkP067LNEqWrXN+/37a9u2A+gPdM7rlN8B6lFXd0C 8Vk9WD1HaD188zOsZF0JP1gnmOLarpkqZk6LLlwxgzV14Q4++88f76f2rp3T2edEAr6ldgm hw8mK0il9mfN4zu/KWIv2bu2HmDhQlbZa5yx/RW0B++GLzdq3+Bo/FtEbvOBlBAQddX6EKl Sm0ciC2AUtqmRWUgYx9Aw== X-UI-Out-Filterresults: notjunk:1;V03:K0:XW/wXwxEP5U=:79Z8+UWKUEfRNtNA52vATW wJFlpXQJKhon4qx2TxrMMafIyL42sVkPIPJc2rskAGgzgC/FOeO11fz/QefenLXsMdT2VELUZ 44RvnWRl9TPWPXFuNifEoW5suiHjvuY/oylL5uONKdU1IKO7S/05YD2iHDLQdJhosyUlszwca Ml7tmlixRU25mCTiCL74raMH9tMvSHlCe5iOvP6su/sorGLf8Wl0zthZY7d7afFMdaOkuJIBm g3TisDJASG5vMTJzvfDx2RLUS/WrRF0xtWuyyTuNgWVqN7tIPCuVaJY+w8kos6lSVqonJ0AIw K+DvAbjynU5mDgi57yL06M1vA0Zh/81frCfu3tr4x+ybQFFyY+8jmwzurKQkbzh+zK129HKMy Piqzc4u2jIhptvRb4wt2349hNO2QKXhEWFWvVE4nG+tO6AGA5qYjB9RyVLnrDY0m5ZrAO55VX 4HrmdaQFZkE1H+WuASdeVgkQ4/XSi92Nss09TT/whzE+coMujv1LjXxzu873DfEuM/JdV1dve /6BjlVdcZik3FxrfVEW8v3Y7Frb8aPbBGlu6kN+NUENulhgMQnPE69UtdeWeKh/wPGmyVy3Yo QnpdzhUU2eREX/6u+oxsrbQoWXUe7hEFJzRAoiJ7hV5DvtTNLCUbqvIu47Sw2bG7g2JGbMNQ3 xg1sseJbybmGgPZ6iB8EgHeoavAparMN3E5ZZYefvjp8WF0g/xbmKUdnh1v7mXrtYgLIfH7q7 kX0+uL/DGFayDSWpid6Oee0WV9Z4FJQlDKBaqXH8kf3vGfK0lnDBropu5VhG6NUxoKld8TEjx kxYHUnGvYf1yKfbaW8nepoWjH/MB8+ulZuMJCfBQNb9kVoHCQG/leKLHp2KNz549Xgu6pj3WZ 1/tmhHj3EwYY9IYDuizRfGxbGxXfS1Q4JsTbidV/g2km8iWaRf52h5uJ8j6e139mOg1Mnu9Cg doffYObyOKXwiMY3u7o9xeJ2627y0zmhgTrd5htadJt8Epe46DJt2NEnHSey+N4IGp5BKScFk cjxH7sV41R9R0XXihvJ9ZuF6liBUblweYxIhR7O/3sA9V4SSCMeabkEOwV2Y0kzARsDmkzMdp y3SNDVoqkCNZpY= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neusch=C3=A4fer Acked-by: Guenter Roeck --- v2: - Add clk_disable_unprepare call, suggested by Guenter Roeck v1: - https://lore.kernel.org/lkml/20220422183012.444674-4-j.neuschaefer@gmx.ne= t/ --- drivers/watchdog/npcm_wdt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..ee08d9805f966 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -43,6 +44,7 @@ struct npcm_wdt { struct watchdog_device wdd; void __iomem *reg; + struct clk *clk; }; static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) @@ -66,6 +68,9 @@ static int npcm_wdt_start(struct watchdog_device *wdd) struct npcm_wdt *wdt =3D to_npcm_wdt(wdd); u32 val; + if (wdt->clk) + clk_prepare_enable(wdt->clk); + if (wdd->timeout < 2) val =3D 0x800; else if (wdd->timeout < 3) @@ -100,6 +105,9 @@ static int npcm_wdt_stop(struct watchdog_device *wdd) writel(0, wdt->reg); + if (wdt->clk) + clk_disable_unprepare(wdt->clk); + return 0; } @@ -191,6 +199,10 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + wdt->clk =3D devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(wdt->clk)) + return PTR_ERR(wdt->clk); + irq =3D platform_get_irq(pdev, 0); if (irq < 0) return irq; -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40AD2C433EF for ; Fri, 29 Apr 2022 17:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379550AbiD2RY6 (ORCPT ); Fri, 29 Apr 2022 13:24:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379561AbiD2RYn (ORCPT ); Fri, 29 Apr 2022 13:24:43 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5851953E29; Fri, 29 Apr 2022 10:21:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1651252847; bh=Z1/WCslgP8Wu/YmkLh8+6LMQRMiTIAjbeV6cgUezSJc=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=fIRtFzawmsaX6o+ddoVPLzUuLxHc6cxoqE5L4Ot69i90OAnPCIm6fDKERamVqglvC FhSeVsDIegW5T7aRLtNfN1Dv2Ve7Cd/fCZ+uvOjAdRi6wuSW9IKpVBYaxvHpI3gIjf kgnUxUWCRrAkn8fSh8BO8imx4zSZ2vTnpVc4Zp+M= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1N7R1T-1nusEd3qwv-017jjP; Fri, 29 Apr 2022 19:20:47 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 29 Apr 2022 19:20:27 +0200 Message-Id: <20220429172030.398011-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:FtwV/jWJy43+n4llwQ3Sij16mE4Ezw/LQCEHbWDDWomdDPeXN0W gWHIQ2vodYBekKau1Gcs4lGe15j7SSyRB7plaBkNyN4lXlYhN72apLn8onSAoJWlphjkx33 ufeP9wbjSAepDspynVTGPM09cV2EYFChmgjd+3FDL2B9JQcW8mwNLjDhIBn59SlcNOVB0EY D6FTt9A/39yDlM1SLXPsQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:etFaIwB0Row=:FOazck2oRSDPJD3vGjwi1h Ep2ZieZ4k3EtjmCJ3+DtHg11ZAaW47kyxMVF7XQIFZOb1nvckWZVyUNeKH+MoG852VZJNYrid F1eqYGSu2+tQsXqXb38SUnp3qnVxWWqxPH9vIct5TTOaRhyRE1rXriKdnLCb6EXk6A+YhU5dX yjils8QyaCc/2EBN/MXeDIdwehVryorvQj5u+NJdw9IXEjrISc9csU4H5l7C90Xq73pZxvR8S g0I2vAiMWZogdYGh5RcBKX7w5g9dkTJIp3pKaLdnUCPh4/YP9bj696qU+n4Tj9611NP9zdDRu GphRgtPtP4vJzqh7ND2EQ7URfZoLNK3rjbe8Ntgq7xqDRMgAvIHwh1qVzmMDa0X01TQxBHswB ekLCwyehyyYQX2JOeIJ6+gSY/JD4AitKy5mmk7gaxXgu8Vm2kVjZniHr80O1utoXk0uZWxZM7 8ZttWUKd8am2DxTi7Gv6rPFTAVYz3niQBreJkI2NjXTiSjdHPyS1pD2XXWWR29g+8Ve1jEUSu CkRrBUovuWE969vNmQMKOG8OM2U1JLtHhz/uASSK5kzexGCUoGdjAdfJ1QB2pu9N+2kA5qbeG l9qcfn2aYEcXUiKtlk3sapFMq/yDTwHtubN3jm2UOY2SFCKUNc4HDhS/+6o4etaH5lleeJ078 OHtEIJtAOBqyPWXCovDun1beDMH9/hPuDtbu4STnWBYX7ykBGm+4T3/knnh5L7TaJ/7xTRNrU mjQDOJDvHMzIT4cCppW2A3kh6VSYl/MRZ20Ibl8qaitxG0v7g8oZWiB42zJ2XP3aPUsA2IC4U EwczzHeaxXdWdtua2howGf5ii5Rb3ltf6X3B+5A9el/4tK6oUrD4UebJR/J3mkILpevL0Jjpe tfRgG8L2QDrtCCcr0Crz6LPQr1VALEJEvGKpHnODi4q3mE2KSL9aZXm2umY9+xDrMM7TXAcW6 at8c1wzRJ1h+eGltgE84TYNzyb8qyrRMo91iffifMyNopEdURXR3Qq4vP1spCRH5tDI9WB2At R8MiuYnbcimva8t2+VdZ/5ProvdjHhY1v7JreGwtIfFiOSf9KaOPymJ0UQ6SEYeH/0zI5qin3 KN8tTgtUoYwJOM= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neusch=C3=A4fer --- v2: - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.ne= t/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450= -clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.ya= ml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..3ed3e40e39637 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neusch=C3=A4fer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and rese= ts to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: refclk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible =3D "fixed-clock"; + clock-output-names =3D "refclk"; + clock-frequency =3D <48000000>; + #clock-cells =3D <0>; + }; + + clk: clock-controller@b0000200 { + reg =3D <0xb0000200 0x100>; + compatible =3D "nuvoton,wpcm450-clk"; + clocks =3D <&refclk>; + clock-names =3D "refclk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-b= indings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD49C433F5 for ; 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Fri, 29 Apr 2022 19:20:48 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 5/7] ARM: dts: wpcm450: Add clock controller node Date: Fri, 29 Apr 2022 19:20:28 +0200 Message-Id: <20220429172030.398011-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:5w8WTRIP7F+Bno5d3r/iMNvZAr/pydK7Dnl1ZI+EUCtsm6H7QTd FFO3kj1TeeCaYaFHYu6u3dQGvdEtTnDnZkEPCp9rbbzLEfZVXzpoUiQEpp8LxbZmequ1CN4 WERVz3FqRB4OFmPreLckTbkuynhDS4lHf35vOuqRhnLA59nUtRnECtacpKpK+WtuwtN8Uf0 A3VhM2iEV6p9cRgFhGPUw== X-UI-Out-Filterresults: notjunk:1;V03:K0:yLsn5BD1VVY=:cXqMcFYjp6NL4zbtrRSrmb RMG0H/ZVas9mOrE5yxIVkDc7oNoH2VGYlo/EzhH82kl9xg9ff+jAYB/eWZHc9OCX0+ktdHOOh 0V6opfDjBClj0Wj3bgpcsCr/oJQ/9vqOie8ZXyJGc6C9OYe5zWD/N7yVYCOBNHVtVpwktkDgH kuszmjWvnkTaRz53UEbMfT7TUgv6FoBoJPQm5huAYNF9g5i8Qf8mxNGF4rYDyQaD5JzMwZPhJ IqVFoLKI3g3kOLMKDjU/HpR3ac/VUaOBN0KtvcwzJhVec91LwYz8rcE4CEnIfcEgupLtNuRnq CV14ns80l90CySn7w6xR49a/jmdkaWu982oDGNF+umDeaA1JkH/NRDDaWXaUbulmMS98vmQFG 0S7KYz6emeh4VNZaNExUfz2WY9JR2jnJPO9nxTFNPw770ieHmRFg3Up5RCRDVRRz7Tbj9Rdgn LZ44yma0EC4UddTWtKP9YI9ee0RiUVoLTvz4DVM2FR2CoWEKZ+gErTobFRh8pownNHAacKI52 VYrP9exys9IGdp87LlNqTYL3o2t5PxknR8rN/6uVA8q68GO+5ySvszbd/RnbL4U0bF8WjLY91 07FbYK8Y9lqzgSgFSiZ31gaITOxYIfUMO2gdA2ltKLO7ikyrQr5k/h5Efw8vrDVhlkZvVxrhF feQ/QZm1mBQVkEJlbsjYhHloqe6acoSbgzJYuqhIBAFbvKWfOiJhl0yEsDW3epsgLf1SpJ9rN EtIfJLhZaACnlOGicRq3DyRHO7Z/NjbhOubgpLhYx1f3/kcnxYlWjG3tTOPc5a2Cr+JS9U3MW Vms7ooQO9QtwEpboR68/IS1R1vc8OFYqYwjUzMMKWjuynouWyhDI63YFYwEkui9c6xfyKI8og TMpoZUWauAWc6R/YvP1F+qDlNXv0WCX84rkJuN6QtbfnbYZ+RQOEpyYG1ZnLWomy6wScJkZ6J eQ3vj7vwqwcDFuUGC4AoLy8e7NEvJTcrccviLaBavOx4+iLDKpam3AYloXxMY4hpLx06mEVY2 nLx17jLWA+wF2U6l+8vrP8355yd8DjNX84rnBEospHpxck9xHqsNpFNa3sRmfOuBujGpUNMR1 hWUAWdN1QPbEGo= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neusch=C3=A4fer --- v2: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuv= oton-wpcm450.dtsi index 1c63ab14c4383..62d70fda7b520 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -39,6 +39,14 @@ clk24m: clock-24mhz { #clock-cells =3D <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible =3D "fixed-clock"; + clock-output-names =3D "refclk"; + clock-frequency =3D <48000000>; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; #address-cells =3D <1>; @@ -51,6 +59,15 @@ gcr: syscon@b0000000 { reg =3D <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible =3D "nuvoton,wpcm450-clk"; + reg =3D <0xb0000200 0x100>; + clocks =3D <&refclk>; + clock-names =3D "refclk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + serial0: serial@b8000000 { compatible =3D "nuvoton,wpcm450-uart"; reg =3D <0xb8000000 0x20>; -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB7C1C4167D for ; Fri, 29 Apr 2022 17:21:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379558AbiD2RYz (ORCPT ); Fri, 29 Apr 2022 13:24:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379556AbiD2RYn (ORCPT ); Fri, 29 Apr 2022 13:24:43 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED31E532D8; Fri, 29 Apr 2022 10:21:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1651252850; bh=llfgzCd3ucSChxpYY4SF3bZ2AyHAwWZStlZtAezA+dA=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=JVV1VTwxjxuO2z69/87Gf+bxSSfLG8IsoGVbE+4McpHYsA7GGnfHLx+98m+BHVYFm xQ8WP64n0luQZRmsBMc4fcfoJvLgYgA+ETINbIl4RyG2zhf2sAnzz1M520oFsNVclt UtIetxhGGd9UlcYQvTT5DYgxZYOT4Qv6kEiTXbF0= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MLzFr-1nTEWp1qd7-00Huez; Fri, 29 Apr 2022 19:20:50 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 6/7] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Fri, 29 Apr 2022 19:20:29 +0200 Message-Id: <20220429172030.398011-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:ZOfeOCMdZofEcyuR5uuNInx3I8WK1UfXL12y2zSTVL2e/eyzBY0 MIkeocB5BPuZbLf7CENfqIbYxbYVCohYMhsTRudfXmu3mSo/nQa7s7gj5qrXZHcwt3SNh/N Sq34jobcWF4P8MaMm5kcQTbw/JXYiwHScyCIP+Q7QdwQTjbamnVgGtkFV/ltjWcQEH5/am5 m/cTOdMjW2M3rEHZIvvIw== X-UI-Out-Filterresults: notjunk:1;V03:K0:edl2KdBPkKo=:qznQSu9YMJXv//uq5UaQ2m 0h7X01c9g0zM1rjp+F+5wqyqT7Xb/sWSxynqdlq29DKMGgr3khnFRSqwmmlfrDJ46bRHRnZo8 hXLYwEoAiCsQ//8MEQcaUdWuPOaNSk/91d8HAiyA6lGf3Rnor3N8j1llMx63S7g4q/Abzmb0k +PDjJxGXNz5ovIekaSzL4yB8htzua23qVnHdJjJQ47ZDFlljlr6Iw2h/Z7zlGTGDQnFlLzt8f +V5C/yNR0eZ7INxKrQSb3mc+tzV6/xb3zgBfWf3pNlkiVn+Tuwefq+8PsYNhZwcMSQ9FS7SDg KdTiW77vUt4PQAlsQqPom5ziO8PjTo+AnjDCbyypIsLp2RArRVGC9dFeg/yVNnjmCpDHWRoK9 l1XBvhPZxppFOuByaQteCQ11y3f7L0kLZmHdVwNZqi1wStVhsXJ+kibzr04BI8ILFrDHknD0/ VaclSKnpZ7DoJ7hqQz6VyUhRX+LKmoGtlwYiwXeyLLGnc0pNiVrcnaDmU9pdbhjTDvcYMnXmb jQxYfdieUo03zkJIONOlxcQxu/1byFBxcexXW3raz7y8js+JD8itNctQ/jZMSpowskvM9XFz2 MQP1/vw1Nx8oGGScpfCTIpC2dvhnLPs8XmZNDhnFxg1ySdX3oR7BtNx8LfimfXSPfPfu2ffZn jM+xsIuoWqLRa0nsLtTUx7IuSU8f6Kp8Dme3rUKAlaKgErdUoeRoUMkUi+fpL6Yn19xY80wD2 /2NWjKCoSCZN6x0CKMFBe3MX6MBrdMLzvJT8Q70EqNrQqzp95arjHCwUNz2lLStbQyD3Qum7Q NWyvgCaJIxuyWQibC86xPjn20ya+DrnlO6zizeDeYReBdKBqiiKfHyM1Q6xJTM6SppS450OgJ LbprJp9j4fSIGAXMTvFs6qF0UNm2YAuXpJy+Swf377ik0xXU++m+KCNxe8IHFg/A0gQn9SDyh copKy1c7NYGM3smVVxnp07UFHSpQO5YDS83NPOKU+7/Ow8mJC6WLr0pAw90+MaPFiytUix8O7 rnlJbJ7yoCLsOm5ENChyskqnywsXrbibVrgQ0YpFTyuON9dctQ41qIIx2lo1f4FVTWFPgtwsN 8NZIUw/0HflIjU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neusch=C3=A4fer --- v2: - no changes --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 378 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bd5ffd595bf3..07edb0f4ba8ba 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_ARCH_VT8500) +=3D clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) +=3D clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) +=3D clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) +=3D clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) +=3D clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..3b62b5961d5f0 --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neusch=C3=A4fer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, = hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll =3D to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate =3D=3D 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon =3D readl_relaxed(pll->pllcon); + + indv =3D FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv =3D FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv =3D FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate =3D (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll =3D to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon =3D readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll =3D to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon =3D readl_relaxed(pll->pllcon); + pllcon |=3D PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops =3D { + .recalc_rate =3D wpcm450_clk_pll_recalc_rate, + .is_enabled =3D wpcm450_clk_pll_is_enabled, + .disable =3D wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll =3D kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &wpcm450_clk_pll_ops; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + init.flags =3D flags; + + pll->pllcon =3D pllcon; + pll->hw.init =3D &init; + + ret =3D clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + hw =3D ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + const char *parent_name; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] =3D { + { "pll0", "refclk", REG_PLLCON0, 0 }, + { "pll1", "refclk", REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const char *const *parent_names; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] =3D { 0, 1, 2 }; +static const char *const default_parents[] =3D { "pll0", "pll1", "refclk" = }; +static const char *const huart_parents[] =3D { "refclk", "refdiv2" }; + +static const struct wpcm450_clksel_data clksel_data[] =3D { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_default[] =3D { + { .val =3D 0, .div =3D 1, }, + { .val =3D 1, .div =3D 2, }, + { .val =3D 2, .div =3D 4, }, + { .val =3D 3, .div =3D 8, }, + { } +}; + +static const struct clk_div_table div_ahb[] =3D { + { .val =3D 0, .div =3D 1, }, + { .val =3D 1, .div =3D 2, }, + { } +}; + +static const struct clk_div_table div_fixed2[] =3D { + { .val =3D 0, .div =3D 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + const char *parent_name; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] =3D { + { "refdiv2", "refclk", 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] =3D { + { "cpu", "cpusel", 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", "refclk", CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", "cpu", CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", "uartsel", 0, NULL, 16, 4, 0 }, + { "ahb3", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + const char *parent_name; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] =3D { + { "fiu", "ahb3", WPCM450_CLK_FIU, 0 }, + { "xbus", "ahb3", WPCM450_CLK_XBUS, 0 }, + { "kcs", "apb", WPCM450_CLK_KCS, 0 }, + { "shm", "ahb3", WPCM450_CLK_SHM, 0 }, + { "usb1", "ahb", WPCM450_CLK_USB1, 0 }, + { "emc0", "ahb", WPCM450_CLK_EMC0, 0 }, + { "emc1", "ahb", WPCM450_CLK_EMC1, 0 }, + { "usb0", "ahb", WPCM450_CLK_USB0, 0 }, + { "peci", "apb", WPCM450_CLK_PECI, 0 }, + { "aes", "apb", WPCM450_CLK_AES, 0 }, + { "uart0", "uart", WPCM450_CLK_UART0, 0 }, + { "uart1", "uart", WPCM450_CLK_UART1, 0 }, + { "smb2", "apb", WPCM450_CLK_SMB2, 0 }, + { "smb3", "apb", WPCM450_CLK_SMB3, 0 }, + { "smb4", "apb", WPCM450_CLK_SMB4, 0 }, + { "smb5", "apb", WPCM450_CLK_SMB5, 0 }, + { "huart", "huartsel", WPCM450_CLK_HUART, 0 }, + { "pwm", "apb", WPCM450_CLK_PWM, 0 }, + { "timer0", "refdiv2", WPCM450_CLK_TIMER0, 0 }, + { "timer1", "refdiv2", WPCM450_CLK_TIMER1, 0 }, + { "timer2", "refdiv2", WPCM450_CLK_TIMER2, 0 }, + { "timer3", "refdiv2", WPCM450_CLK_TIMER3, 0 }, + { "timer4", "refdiv2", WPCM450_CLK_TIMER4, 0 }, + { "mft0", "apb", WPCM450_CLK_MFT0, 0 }, + { "mft1", "apb", WPCM450_CLK_MFT1, 0 }, + { "wdt", "refdiv2", WPCM450_CLK_WDT, 0 }, + { "adc", "adcdiv", WPCM450_CLK_ADC, 0 }, + { "sdio", "ahb", WPCM450_CLK_SDIO, 0 }, + { "sspi", "apb", WPCM450_CLK_SSPI, 0 }, + { "smb0", "apb", WPCM450_CLK_SMB0, 0 }, + { "smb1", "apb", WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_controller_dev *rcdev; + + clk_base =3D of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data =3D kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KE= RNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num =3D WPCM450_NUM_CLKS; + hws =3D clk_data->hws; + + for (i =3D 0; i < WPCM450_NUM_CLKS; i++) + hws[i] =3D ERR_PTR(-ENOENT); + + // PLLs + for (i =3D 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data =3D &pll_data[i]; + + hw =3D wpcm450_clk_register_pll(clk_base + data->reg, data->name, + data->parent_name, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i =3D 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data =3D &clkdiv_data_early[i]; + + hw =3D clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i =3D 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data =3D &clksel_data[i]; + + hw =3D clk_hw_register_mux_table(NULL, data->name, data->parent_names, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + BIT(data->width) - 1, 0, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >=3D 0) + clk_data->hws[data->index] =3D hw; + } + + // Divisors + for (i =3D 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data =3D &clkdiv_data[i]; + + hw =3D clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i =3D 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data =3D &clken_data[i]; + + hw =3D clk_hw_register_gate(NULL, data->name, data->parent_name, data->f= lags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] =3D hw; + } + + ret =3D of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + rcdev =3D kzalloc(sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + goto err_free; + rcdev->owner =3D THIS_MODULE; + rcdev->nr_resets =3D WPCM450_NUM_RESETS; + rcdev->ops =3D &reset_simple_ops; + rcdev->of_node =3D clk_np; + ret =3D reset_controller_register(rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b496028b6bfaf..50a3c1403c335 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -201,7 +201,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || AR= CH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || AR= CH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, -- 2.35.1 From nobody Sun May 10 15:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CCD7C433EF for ; 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Fri, 29 Apr 2022 19:20:51 +0200 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v2 7/7] ARM: dts: wpcm450: Switch clocks to clock controller Date: Fri, 29 Apr 2022 19:20:30 +0200 Message-Id: <20220429172030.398011-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429172030.398011-1-j.neuschaefer@gmx.net> References: <20220429172030.398011-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:CapGnF66PbIaJCrYydROSSzdBD4+jGIG259czWWFShncx/7mfO5 n7LWPKDdswQhfnHBzXYt8/fCGYBOs/TNhEn25Fwffb80q+MwOOZ/NEiURk+UPXwY48HALAb FbieQhHcsWYBrn+zRmzCSCsAlAiOK8G3pN4hGDYJzh4lauaSbA0mrj4YIkwuAW/mxJDP71A WtSOAngqDLdX/T5fi7Z+Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:op7guGsTdCo=:wC4SD8Y6g9Umj7VnspIayf M+K6RolgpoBePq+LQFfem4hZ/4qtppk6wZv/b5ufzOtFf7pn5u7aptkk68boj8jPa3xOSKeCm gvipfpEuKYq6jwsFS5l3nUNpNTle18GMbLDwHoOBahGxOmNyZrl1pPQY5sl1IVs0W2F1iKeTR J74wtKyQBw9WsURuXNCp6j9F8MktBcPOo6HSVGT8H9HNV4Ti4fp53S6OzQS2la/BqcZWwPi7s wxm//FqpVJutc+WperY1CO5EBT9pMzH08efPnCua8Ek6xBeUKHtnAlxlxlLGDofQcJ95YEmRQ xA//2YdM7BrZXFuRtGcdGVn9QDRrVBMyOaT3bX6HwvjR9sEc4Z/IOWhfgPWk5hldVXknze4Vk uX9cBpXZMZkwBpg+1RqNzjyLrPUG1e1l1MAl/BUWM1sKkIu775SQJtBF8xgpBoHyl0sySYrqb WH8a1koFNspArjEaKdsgNa867z1EsE8FeV1ec2l4fTr18MdA/vC1eeab1Ib30aLklltfp76Cv xP7pcO7oPQZI/FWhPoFiFonH1RGGBNXuUqSQkwR8AKZN0aPpc/LoYUOUXnUXMgVdOrGXL9Y32 z9R/fMTs0xz0hrXAoR12Y6uBZ4XGBS2eqdb3AuMNcadYYNHLWhPeXq8omoaZe1/kniBnF88Tn Mk6AZ31Wx2wrI5OCfEnJ2DxnIuz8w7QSUea1K/xzn2xj0B+Ef4fU9aj9jwFSJ4bEX3UGCWXhz qb3BTZJ1ELYrxLj5ocIlmWSxEnorHWa6iBGSsRFu4hv7wGTJFojL+iOvxrhhQlRX052pW7cuu Gk9lTUcxyeOvMHPGnnta/R8yeasFpp395WVdzy4c4GxowDOmNdkH79Od/BiXM/x1DxUtHjJFB lcVIQayLDqnFmRNEoYJ/8y7J2K4M9QJ+Tb/4W4RcHfO4qjaNWwy7gDGwQbV0PQfGR7pgL1/mY QcBCw+n+yE56UXHSAdTIDM3Uwh2Agsn7aNZJ7+LP4KSIk09Nmxas2hUkDrNP2j1zJgEo9NJA4 yRJSkKhI/E9xl/lQQXPs+bEwm96qYbA5l6hDaoB9oFjin3r6pMCPubmsgXG9upCPTcKDBfxJ1 xKJR09p/xyGTsc= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neusch=C3=A4fer --- v2: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuv= oton-wpcm450.dtsi index 62d70fda7b520..f868bd7db009a 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neusch=C3=A4fer #include +#include / { compatible =3D "nuvoton,wpcm450"; @@ -32,13 +33,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible =3D "fixed-clock"; - clock-frequency =3D <24000000>; - #clock-cells =3D <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible =3D "fixed-clock"; @@ -73,7 +67,7 @@ serial0: serial@b8000000 { reg =3D <0xb8000000 0x20>; reg-shift =3D <2>; interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk24m>; + clocks =3D <&clk WPCM450_CLK_UART0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&bsp_pins>; status =3D "disabled"; @@ -84,7 +78,7 @@ serial1: serial@b8000100 { reg =3D <0xb8000100 0x20>; reg-shift =3D <2>; interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk24m>; + clocks =3D <&clk WPCM450_CLK_UART1>; status =3D "disabled"; }; @@ -92,14 +86,18 @@ timer0: timer@b8001000 { compatible =3D "nuvoton,wpcm450-timer"; interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>; reg =3D <0xb8001000 0x1c>; - clocks =3D <&clk24m>; + clocks =3D <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible =3D "nuvoton,wpcm450-wdt"; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH>; reg =3D <0xb800101c 0x4>; - clocks =3D <&clk24m>; + clocks =3D <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 { -- 2.35.1