From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AAD8C4321E for ; Fri, 29 Apr 2022 11:53:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358745AbiD2L4b (ORCPT ); Fri, 29 Apr 2022 07:56:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239302AbiD2L42 (ORCPT ); Fri, 29 Apr 2022 07:56:28 -0400 Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E16C5C6EE8; Fri, 29 Apr 2022 04:53:09 -0700 (PDT) Received: by mail-qv1-xf31.google.com with SMTP id k12so5153252qvc.4; Fri, 29 Apr 2022 04:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/0BzL8B3OkyLX9kPF01T/3su20f1yiIHSqjn4IIxTHE=; b=EWQyr3BtXtid12435zlUXMdpotNXe7nlWXj21MJoKVVQ0kdevcfwpx9/gTwuT+d4n3 ZlmSRcLRaOVwcQHYDZmpsqyhyWCyAKpy5CXg0CLKxF/TsK3iTPrZUZCAIWYtFbJdF8Oy 2L/7EWvQMVU3UHIRS6ApD0VCHvQGcoWTpJxi2IF8b8hQL9DKh39G5OO0prIEcyu0LhVF p1vGUTpZDQllC+jW0+1pNKvD20+P4wf13knEF1aBjVhqLIMZQ8BdRAxLtjaAn7vmY8Vk O/s1KiUdbmD/BS8r5haUjw6uX/QfU/a9Ekw08kKtk6fHc1eMfd/43RhTn87fiuo1VbGW +IfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/0BzL8B3OkyLX9kPF01T/3su20f1yiIHSqjn4IIxTHE=; b=yCNlHXT2wzIrk5N3rfOMyaw5hIy3JIj9sxm6lwmwv0LHH0OjT/YFxlnPLGgp65Mayh w5JS2B/kUDy+/nGcpJx/ApIBOBF92R9SkhajgATeWWxckngPNLZS9vTUD4o+A39LqG08 wpJa+sUMMfiyg+g0gyCPS2cTUxx7i2pZt5PHKIyLO84AKz1Zf1CLWKAS/McwxAAcERUh xSlH4xUtD0+g/+2/LZoA82UQ2yRz3ocibRyX0co53a5SQw2Gutgl5+6jDLFXyrCaTlt9 EcWL54CAOz86dtoHEBEqp82+miYd2zQHZUSQ7bC3JkhSSfNBVZXCgtEhNZs603Oi4GvG e8Yw== X-Gm-Message-State: AOAM530C2qO693IIKd2uQgTpBTTvKUFagPuvrnW8LyPmYKrOnQeIWrKp vf1bq46NkzVxhzfIQBxu6qw= X-Google-Smtp-Source: ABdhPJw1Q6hPXonGtQBvISs/6ZWPt5hrKsKtiTrqr280rT/+R3hNuoup9aJuXugDkKrDlFCrNeUAWw== X-Received: by 2002:a05:6214:4104:b0:42c:1db0:da28 with SMTP id kc4-20020a056214410400b0042c1db0da28mr27420668qvb.67.1651233189032; Fri, 29 Apr 2022 04:53:09 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:08 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B Date: Fri, 29 Apr 2022 07:52:46 -0400 Message-Id: <20220429115252.2360496-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Quartz64 Model B is a compact single board computer from Pine64 based on the rk3566 SoC. It outputs on uart2 for the debug console. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index eece92f83a2d..beb5b0ac1a2a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -502,9 +502,11 @@ properties: - const: pine64,rockpro64 - const: rockchip,rk3399 =20 - - description: Pine64 Quartz64 Model A + - description: Pine64 Quartz64 Model A/B items: - - const: pine64,quartz64-a + - enum: + - pine64,quartz64-a + - pine64,quartz64-b - const: rockchip,rk3566 =20 - description: Radxa Rock --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C951AC433F5 for ; Fri, 29 Apr 2022 11:53:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358772AbiD2L4h (ORCPT ); Fri, 29 Apr 2022 07:56:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239407AbiD2L43 (ORCPT ); Fri, 29 Apr 2022 07:56:29 -0400 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE2A3C6EF9; Fri, 29 Apr 2022 04:53:10 -0700 (PDT) Received: by mail-qk1-x72e.google.com with SMTP id 126so4653871qkm.4; Fri, 29 Apr 2022 04:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jW8w5Kaw7/H5XCbI2kCQ16R8uTSgfLbNJXXeM0gMkvo=; b=RNt7zo98GfO6oQ2OvLOZidtn73jtI6KGw7Tbw7PdL1cJ0/n5ihcStj0IdxKjnP3klH S516ToXWBx3vo5aF9t2aEmMX9HJAkeaHyJ4bVL/Ya9gZMZquLsGppaNZnVcMVGrt7Bqr gcnhvgBEF3/I0N/P/TjykqoeH7Ok7Hb0Azmx6p4JUWPYTrlt/hawzbvlvpEZ3aLGK9Om B3jyCQIQieHzFv/inOnb+vITn6qDa0VlZRPJ/ayRCag0qkvzSiNu0v/OpanuyBabjz4I IV4THTJREjqC+NTWxkXG2Bg7Z7FP0QdZ7udG1HQJGkghRwAcmfeVbp6HIW9fQw3NL0Gr F1ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jW8w5Kaw7/H5XCbI2kCQ16R8uTSgfLbNJXXeM0gMkvo=; b=Y5E0i74sRtG24vYXQcuQgDZEfWoxN+j12VNr1/Ru0aCh1A9e2YufTUFOIdfChTJYHK CmKBjZfJSUn04GTvBE26u8YS216VkKduhCPsJywnM0b4aZkUOQvjkuKk92cnBw/lEFbo 7RDibXbxF84Jr6+bYAdQGfoT3+98QwoDXQZ5mUImJx1wqmDrP6xFzupi3aR2gXiUL0J7 JSPQpb3McfHgK8XUbqrCnPsYnulMg15F4t2yWGCCMKCJItr64M596ujU/aKm34lkAb8a LgYrwzDxu7JRIfe+o9qgDgy5KEVaxTPooiFcMLVV9RE6YlUrQank9y7EIVdjXrtukdwf i+vA== X-Gm-Message-State: AOAM5315st/uAo3ww95gh4TwRwrq+GMReukwIyckSWaG2CnRGCJDZ+Sw UPQW5OwG9uDn+ysMmnH2B+M= X-Google-Smtp-Source: ABdhPJwbuQgvcFaVFG72RI4ScVNdIUw9FCOeppgEtLex90TTIiMwKskD7aNa6c7UPCidcXCwFKvbvg== X-Received: by 2002:a37:6902:0:b0:606:853:fe50 with SMTP id e2-20020a376902000000b006060853fe50mr22197916qkc.751.1651233189959; Fri, 29 Apr 2022 04:53:09 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:09 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM Date: Fri, 29 Apr 2022 07:52:47 -0400 Message-Id: <20220429115252.2360496-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SoQuartz system on module is designed to be pin compatible with the RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for debug and console. The first carrier board supported is the CM4IO board from RPi. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index beb5b0ac1a2a..b85a8e6c5e75 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -509,6 +509,13 @@ properties: - pine64,quartz64-b - const: rockchip,rk3566 =20 + - description: Pine64 SoQuartz SoM + items: + - enum: + - pine64,soquartz-cm4io + - const: pine64,soquartz + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CBE1C433EF for ; Fri, 29 Apr 2022 11:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358764AbiD2L4q (ORCPT ); Fri, 29 Apr 2022 07:56:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358734AbiD2L4b (ORCPT ); Fri, 29 Apr 2022 07:56:31 -0400 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7898C6ED3; Fri, 29 Apr 2022 04:53:11 -0700 (PDT) Received: by mail-qk1-x735.google.com with SMTP id y6so3476763qke.10; Fri, 29 Apr 2022 04:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gGeL3vqvV+tsZXortm1bChbjn2BI/sUzqWi2Z5G5epg=; b=gHuIH+ICOFoIXkjGy7RKBQ2zwMf/vZuR/lkb7AySl9mTPbJVzIBHpa29CnhPA9ff/a if0iKwPV1lO7dw2PcKXUalir6wvcEcnmlgALlwkKyCkyV2KZLqMxshNVSJXBg19NSEvR 58ZJ/4Wh+sky5VvR02xO4X6ptkonHKtR5yCP95AgD0V9VLLVN/w2RPTInDfEhFIPrjt4 m/Im26teWUlAM9ZrH0swzoRQnXPpaj9sdrPTvvg//xuIesfW/fQYAlylw5nUJdBi9vdB +Eb0UgFeBnbQBfvyUIrLg9GRnqMN5x1yMX+LroCfYTRBAalNfckFiBWxi57jVnM3lrDB M4Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gGeL3vqvV+tsZXortm1bChbjn2BI/sUzqWi2Z5G5epg=; b=D2CMy4wBHd/eVAdsfoRofJ4UK64X95tmQqy5woXu1dLl/kLf/VSe7Mu77apUM8wBf8 hAyT4PLHK060uA+gvBiKSQKJf7WU9JmjmsXu9ubMyefzlw7eHARA0RhpmaiQhizI8C2H 9npQTU4EtTsq0Y+SU7+YBqcM3tLiNvdo8zTc/KqxtMfx4KhwqXim+YGph1PPzcV6DRsU 34/VUNiBHRZuqDqiEL5kQfhb5aAqbrPV452oAlOt1u5i5G2/SFCnIFl8PpVoZsSjyrrM X0t6Qwp7oLIlvZfcHbpEwRUUCYTax2EKNQI4m+2MsrL0oY4sP7YYionAb8FR6etV+2eY 30UA== X-Gm-Message-State: AOAM531zMUMJwBWT0SlbGjA5lulVr0deCiedsRsnDwESorajisQD4Kuf b+fMNW9VzJxpXFZd2Gl70TI= X-Google-Smtp-Source: ABdhPJw/jdE9yOwN6ajIW50uiF7ojyla0JcoEwOGAtnxxCReSGQD6/sAc4TCfGtIR586QfdVldxkbg== X-Received: by 2002:a05:620a:4689:b0:69e:a3c7:4cfa with SMTP id bq9-20020a05620a468900b0069ea3c74cfamr22637948qkb.591.1651233190865; Fri, 29 Apr 2022 04:53:10 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:10 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 3/7] dt-bindings: arm: rockchip: Add Firefly Station M2 Date: Fri, 29 Apr 2022 07:52:48 -0400 Message-Id: <20220429115252.2360496-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Station M2 is a compact single board computer based on the rk3566 SoC. It outputs on uart2 for debug and console purposes. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index b85a8e6c5e75..288d044d48bc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -133,6 +133,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 =20 + - description: Firefly Station M2 + items: + - const: firefly,rk3566-roc-pc + - const: rockchip,rk3566 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2883DC433FE for ; Fri, 29 Apr 2022 11:53:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358794AbiD2L4m (ORCPT ); Fri, 29 Apr 2022 07:56:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358733AbiD2L4b (ORCPT ); Fri, 29 Apr 2022 07:56:31 -0400 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2C7CC6ECD; Fri, 29 Apr 2022 04:53:12 -0700 (PDT) Received: by mail-qv1-xf2d.google.com with SMTP id q13so5154424qvk.3; Fri, 29 Apr 2022 04:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zdBkDQmKoIggvVv+9nKr+EG7gevAiBpcUOqfYxzGhEU=; b=btsBbf150KlxvPgk29yG535UtWnJICkliDohSbgYOm9Uxqzs45Q0cuw8eRkzeIo5m6 UfaWty44QpA9Jq89tmgWpEOdOse/nkT7r7cU140rXyr5Phfrbkhhm9qemHu6GA7Qrpl2 SmHZ4gQ+HFsujQfELi7YlgJ8R6JqnRgk/3kFkvGT2PtRBKJqSrQXEH4glvObWFiKy7A1 n9x5lmUZJJktqSy+q6lGotSKf+WQdV56AOB2vixJn0q9i9UFFMjPi1k+C1/shz4NVMMc RXfFg6Xb1R28QVl2uLN8h0+1ItWu52ebkixk2rqspzuVqyKKCknQDYaugrQOr7UvnCdA lPZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zdBkDQmKoIggvVv+9nKr+EG7gevAiBpcUOqfYxzGhEU=; b=HI6vnSA8dEj3ETI1AVWIe27xtJoZtTuW9h0oCTWsaWxpGIyWJdIk+GxEm/MZzulLQ6 Ld4fkceLD35jdTey5unNunUH0xxIDy1PmSLdj9hgiyNDbpV5wN86nla+iKmoZpYusNVc h0137ofz6/N/IF3o+HKPgdtXSCyxvishrkTi+HmyjVFPr2yMTJKKibIReXejNNn5Vd9o 2D0BAXdVqGFITeRVPJkWm/G8h/5nqHP5/yx2Z4+0Kbew5goR6GQWEuqptjC9fu2DYLky OLk+u50FWBebyREcCuqfp18zvvXs+fUl5HI8hk6jWU8RhMoooO5xnnv3p/R3wYRmFul7 RwcQ== X-Gm-Message-State: AOAM532+NPKxfAkTJL4i6B5z6Cu68GBnT+ilR6rhubDLo/FAUhEM/gex AEEm7cF4gWRLPlEFZhKopFThgE9FFUpJlw== X-Google-Smtp-Source: ABdhPJxHLLSlDuQSF8q/L28tDhOJvVMBBSaB10SlvL2+Jt+VX752p8Q+6XTmT2eS4vLZrXwe6fmZMA== X-Received: by 2002:a05:6214:202b:b0:458:10af:3f59 with SMTP id 11-20020a056214202b00b0045810af3f59mr2314048qvf.57.1651233191745; Fri, 29 Apr 2022 04:53:11 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:11 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] arm64: dts: rockchip: add rk356x sfc support Date: Fri, 29 Apr 2022 07:52:49 -0400 Message-Id: <20220429115252.2360496-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the sfc node to the rk356x device tree. This enables spi flash support for this soc. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index ca20d7b91fe5..61a6d9d4c8a0 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,6 +750,17 @@ sdmmc1: mmc@fe2c0000 { status =3D "disabled"; }; =20 + sfc: spi@fe300000 { + compatible =3D "rockchip,sfc"; + reg =3D <0x0 0xfe300000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names =3D "clk_sfc", "hclk_sfc"; + pinctrl-0 =3D <&fspi_pins>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + sdhci: mmc@fe310000 { compatible =3D "rockchip,rk3568-dwcmshc"; reg =3D <0x0 0xfe310000 0x0 0x10000>; --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D628BC433EF for ; Fri, 29 Apr 2022 11:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358790AbiD2L44 (ORCPT ); Fri, 29 Apr 2022 07:56:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358751AbiD2L4c (ORCPT ); Fri, 29 Apr 2022 07:56:32 -0400 Received: from mail-qv1-xf35.google.com (mail-qv1-xf35.google.com [IPv6:2607:f8b0:4864:20::f35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3513DC6EF9; Fri, 29 Apr 2022 04:53:14 -0700 (PDT) Received: by mail-qv1-xf35.google.com with SMTP id k12so5153378qvc.4; Fri, 29 Apr 2022 04:53:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W0ONHOXp1qQGx3VZ4Yf3E6RTaBqhduQyGs/XNLTvGpc=; b=F8Av0BmkTr7hhVmgRGZrjQAg26Eo2iw2kpQ7pKf0K9p6vz1HisX8s6BYbQqqqbrzvQ o5TKMsYjaELU0qCoAKqO25YTXCFEaC5n3jwFURp0Xqcr3PIJte607p4BM7XKMC9pcoYR O5TFOLan0zsDHKp5hV6g0XuvTsxu+UmK8AwwuR5nRfVvdV48hjWzY7CCHSGpB988Od9E 0R2z75bvJgV/wivyHLX0vp9WZRTeZ8TiG9q7OqN2yrWHgUsBd1bIKMGOi/alyAzHOniV NGjMyZpfS4oHtQM6GSOHM06bHXArvBv0y/PK5HuvCGefTkHa4hbkEjk9LBVtMboQCo2m Aqcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W0ONHOXp1qQGx3VZ4Yf3E6RTaBqhduQyGs/XNLTvGpc=; b=KIazKm/lspesE3VYBMakz2d+MzjIHDiiUO6p31qCjXMCxsIRvm+O3NtGz8xtUfVU/B h1kH7hoP3pQQGKbqAWHEhSE4s7n9SK1jWjNWMEwffSXPYe3TIwzkolS6eHEUIjTEfcWy bcOZ8XloMmTPOpz0VLO6yulJqSi9DM03C5sE3s9acpxhVI183OddG0w7rmngJVh9XEg7 pRUXAZQ8lsvv7RnEJEmTamdRlE+05Qu+rSZ1Tnvau0mdRCPRUv9KzjOvdcQ7dBdrKnMs 7PGjksCptPoDBuSP2lJZXyu2jh8iHkeU6B3yQL1qppZ1qGfhabE2sPVonfoxZQtCFSff VEdA== X-Gm-Message-State: AOAM532tf0ypqkfYULuv3+tC6FI/WQDdOppm/34osfLcVIpMpGZdUUGQ Gjlm/dAI6IE1tEF1PYQuPIyf612Ja9V5eg== X-Google-Smtp-Source: ABdhPJyzj0vycROF8ldbRjwKRVRG2fyQS6mi305aMZtpp/XjVqz62/DgLuB9XwGZIXw+2KOtNW51Kw== X-Received: by 2002:a05:6214:2308:b0:432:e69f:5d71 with SMTP id gc8-20020a056214230800b00432e69f5d71mr27122939qvb.19.1651233193210; Fri, 29 Apr 2022 04:53:13 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:13 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree Date: Fri, 29 Apr 2022 07:52:50 -0400 Message-Id: <20220429115252.2360496-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device tree for the Pine64 Quartz64 Model B single board computer. This board ouputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 x2 (one port otg capable) USB3 PCIe/SATA M2 HDMI DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI Flash PI-40 compatible pin header Signed-off-by: Peter Geis Reported-by: kernel test robot --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++ 2 files changed, 616 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 4ae9f35434b8..252ee47b8a1d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm6= 4/boot/dts/rockchip/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..184ab7e1d178 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Pine64 RK3566 Quartz64-B Board"; + compatible =3D "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-user { + label =3D "user-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <5000000>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb30_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio =3D <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x4f>; + rx_delay =3D <0x24>; + phy-handle =3D <&rgmii_phy1>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name =3D "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m1_xfer>; + status =3D "okay"; +}; + +/* i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status =3D "okay"; +}; + +/* i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status =3D "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcca1v8_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcca1v8_pmu>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcca1v8_pmu>; + status =3D "okay"; +}; + +&sfc { + pinctrl-0 =3D <&fspi_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <24000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <1>; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status =3D "okay"; + uart-has-rtscts; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +/* uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BF56C433EF for ; Fri, 29 Apr 2022 11:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358776AbiD2L5C (ORCPT ); Fri, 29 Apr 2022 07:57:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358761AbiD2L4f (ORCPT ); Fri, 29 Apr 2022 07:56:35 -0400 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFF55C6F12; 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Fri, 29 Apr 2022 04:53:14 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id 123-20020a370c81000000b0069fa408fdb7sm1382505qkm.24.2022.04.29.04.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 04:53:14 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts Date: Fri, 29 Apr 2022 07:52:51 -0400 Message-Id: <20220429115252.2360496-7-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is the initial SoQuartz SoM device tree on a CM4IO carrier board. This board outputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 (OTG/Host shared) PCIe 2.0 x1 HDMI (HDMI Port 0) eDP (HDMI Port 1) DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI NOR Flash (Not placed) PI-40 compatible pin header Signed-off-by: Peter Geis Reported-by: kernel test robot --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++ .../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 ++++++++++++++++++ 3 files changed, 775 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 252ee47b8a1d..23a2a0c111ac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,5 +60,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/ar= m64/boot/dts/rockchip/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..fa470a587e2b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model =3D "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible =3D "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk35= 66"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&gmac1 { + status =3D "okay"; +}; + +/* i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "okay"; + + /* the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063"; + reg =3D <0x51>; + }; +}; + +/* i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status =3D "disabled"; +}; + +/* i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status =3D "disabled"; +}; + +/* i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status =3D "disabled"; +}; + +&led_diy { + status =3D "okay"; +}; + +&led_work { + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +/* saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status =3D "disabled"; +}; + +&sdmmc0 { + vmmc-supply =3D <&sdmmc_pwr>; + status =3D "okay"; +}; + +&sdmmc_pwr { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + status =3D "okay"; +}; + +/* spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +/* uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +/* uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc_5v>; + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&vbus { + vin-supply =3D <&vcc_5v>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..9ebb2afe7e82 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Pine64 RK3566 SoQuartz SOM"; + compatible =3D "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led_diy: led-diy { + label =3D "diy-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&diy_led_enable_h>; + retain-state-suspended; + status =3D "disabled"; + }; + + led_work: led-work { + label =3D "work-led"; + default-state =3D "off"; + gpios =3D <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&work_led_enable_h>; + retain-state-suspended; + status =3D "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + sdmmc_pwr: sdmmc-pwr-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_pwr_h>; + regulator-name =3D "sdmmc_pwr"; + status =3D "disabled"; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-supply =3D <&vcc_3v3>; + phy-mode =3D "rgmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio =3D <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x30>; + rx_delay =3D <0x10>; + phy-handle =3D <&rgmii_phy1>; + status =3D "disabled"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + status =3D "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "disabled"; +}; + +/* i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "disabled"; +}; + +/* i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4m1_xfer>; + status =3D "disabled"; +}; + +/* i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status =3D "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + status =3D "disabled"; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc-pwr { + sdmmc_pwr_h: sdmmc-pwr-h { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vcc_3v3>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +/* saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "disabled"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "disabled"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +/* spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +/* uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status =3D "disabled"; +}; + +/* uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart7m2_xfer>; + status =3D "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status =3D "disabled"; +}; + +&usb2phy0_otg { + status =3D "disabled"; +}; + +&usb_host0_xhci { + status =3D "disabled"; +}; --=20 2.25.1 From nobody Sun May 10 16:25:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5C01C433F5 for ; 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Fri, 29 Apr 2022 04:53:15 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Furkan Kardame , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566 Date: Fri, 29 Apr 2022 07:52:52 -0400 Message-Id: <20220429115252.2360496-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220429115252.2360496-1-pgwipeout@gmail.com> References: <20220429115252.2360496-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Furkan Kardame Add dts for Firefly Station M2. Working IO: * UART * LED * LAN * Wifi * SD Card * eMMC * USB2 Signed-off-by: Furkan Kardame Signed-off-by: Peter Geis Reported-by: kernel test robot --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 ++++++++++++++++++ 2 files changed, 581 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 23a2a0c111ac..617915c17ca8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/bo= ot/dts/rockchip/rk3566-roc-pc.dts new file mode 100644 index 000000000000..1ede01b46e1c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Firefly Station M2"; + compatible =3D "firefly,rk3566-roc-pc", "rockchip,rk3566"; + + aliases { + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-user { + label =3D "user-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + usb_5v: usb-5v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&usb_5v>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb30_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio =3D <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x4f>; + rx_delay =3D <0x24>; + phy-handle =3D <&rgmii_phy1>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name =3D "vcc3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m1_xfer>; + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcca1v8_pmu>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_xfer>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn>; + status =3D "okay"; + uart-has-rtscts; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.25.1