From nobody Sun Sep 22 06:41:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2152BC433F5 for ; Thu, 28 Apr 2022 13:38:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347478AbiD1Nl2 (ORCPT ); Thu, 28 Apr 2022 09:41:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235759AbiD1NlS (ORCPT ); Thu, 28 Apr 2022 09:41:18 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C789FA0BC7; Thu, 28 Apr 2022 06:38:03 -0700 (PDT) X-UUID: 1d5cccb3290041eabd259e4a26d24d88-20220428 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:37a250c0-03a1-45cb-9515-15c8422d1047,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,A CTION:release,TS:5 X-CID-META: VersionHash:faefae9,CLOUDID:62450e2f-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 1d5cccb3290041eabd259e4a26d24d88-20220428 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2027890787; Thu, 28 Apr 2022 21:37:55 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 28 Apr 2022 21:37:54 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Apr 2022 21:37:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Apr 2022 21:37:54 +0800 From: Rex-BC Chen To: , , , CC: , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 1/4] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml Date: Thu, 28 Apr 2022 21:37:50 +0800 Message-ID: <20220428133753.8348-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220428133753.8348-1-rex-bc.chen@mediatek.com> References: <20220428133753.8348-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Convert mediatek,dsi.txt to mediatek,dsi.yaml format Signed-off-by: Xinlei Lee Signed-off-by: Rex-BC Chen --- .../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 122 ++++++++++++++++++ 2 files changed, 122 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dsi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for detai= ls. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connect= ed - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -MIPI TX Configuration Module -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -See phy/mediatek,dsi-phy.yaml - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible =3D "mediatek,mt8173-mipi-tx"; - reg =3D <0 0x10215000 0 0x1000>; - clocks =3D <&clk26m>; - clock-output-names =3D "mipi_tx0_pll"; - #clock-cells =3D <0>; - #phy-cells =3D <0>; - drive-strength-microamp =3D <4600>; - nvmem-cells=3D <&mipi_tx_calibration>; - nvmem-cell-names =3D "calibration-data"; -}; - -dsi0: dsi@1401b000 { - compatible =3D "mediatek,mt8173-dsi"; - reg =3D <0 0x1401b000 0 0x1000>; - interrupts =3D ; - clocks =3D <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names =3D "engine", "digital", "hs"; - resets =3D <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; - phys =3D <&mipi_tx0>; - phy-names =3D "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint =3D <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.ya= ml new file mode 100644 index 000000000000..2ca9229ef69e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DSI Controller Device Tree Bindings + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + - Jitao Shi + - Xinlei Lee + +description: | + The MediaTek DSI function block is a sink of the display subsystem and c= an + drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dua= l- + channel output. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt2701-dsi + - mediatek,mt7623-dsi + - mediatek,mt8167-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Engine Clock + - description: Digital Clock + - description: HS Clock + + clock-names: + items: + - const: engine + - const: digital + - const: hs + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port node. This port should be connected to the input + port of an attached DSI panel or DSI-to-eDP encoder chip. + + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + - clock-names + - phys + - phy-names + - port + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0 0x14014000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + resets =3D <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + port { + dsi0_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; + +... --=20 2.18.0