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[71.202.34.56]) by smtp.gmail.com with ESMTPSA id g15-20020aa7818f000000b00505ce2e4640sm21011462pfi.100.2022.04.28.01.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 01:41:05 -0700 (PDT) From: "Joseph S. Barrera III" To: LKML Cc: Douglas Anderson , Alexandru M Stan , "Joseph S. Barrera III" , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v1] arm64: dts: qcom: sc7180: Add mrbland dts files Date: Thu, 28 Apr 2022 01:41:00 -0700 Message-Id: <20220428014022.v1.1.I08a15a73996211d37dff16810c40ee1539658601@changeid> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mrbland is a trogdor-based board which may ship as the Lenovo 10e Gen 2. These dts files are copies from the downstream Chrome OS 5.4 kernel, but with the camera (sc7180-trogdor-mipi-camera.dtsi) #include removed. Signed-off-by: Joseph S. Barrera III --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcom/sc7180-trogdor-mrbland-rev0-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev0-boe.dts | 22 ++ .../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 53 +++ .../qcom/sc7180-trogdor-mrbland-rev1-auo.dts | 22 ++ .../qcom/sc7180-trogdor-mrbland-rev1-boe.dts | 24 ++ .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 351 ++++++++++++++++++ 7 files changed, 498 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-au= o.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-bo= e.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dt= si create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-au= o.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-bo= e.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f9e6343acd03..93758a62f4d7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limoze= en-r9.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-mrbland-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts new file mode 100644 index 000000000000..2767817fb053 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 =3D> 0 + * - bits 7..4: Panel ID: 0x0 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model =3D "Google Mrbland rev0 AUO panel board"; + compatible =3D "google,mrbland-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible =3D "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts new file mode 100644 index 000000000000..711485574a03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 =3D> 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model =3D "Google Mrbland rev0 BOE panel board"; + compatible =3D "google,mrbland-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible =3D "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/ar= ch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi new file mode 100644 index 000000000000..7bc8402c018e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +&avdd_lcd { + gpio =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ +&avdd_lcd_en { + pinmux { + pins =3D "gpio80"; + }; + + pinconf { + pins =3D "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins =3D "gpio81"; + }; + + pinconf { + pins =3D "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins =3D "gpio76"; + }; + + pinconf { + pins =3D "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts new file mode 100644 index 000000000000..275313ef7554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 =3D> 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model =3D "Google Mrbland rev1+ AUO panel board"; + compatible =3D "google,mrbland-sku1536", "qcom,sc7180"; +}; + +&panel { + compatible =3D "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b= /arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts new file mode 100644 index 000000000000..87c6b6c30b5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x300 =3D> 768 + * - bits 11..8: Panel ID: 0x3 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model =3D "Google Mrbland (rev1 - 2) BOE panel board"; + /* Uses ID 768 on rev1 and 1024 on rev2+ */ + compatible =3D "google,mrbland-sku1024", "google,mrbland-sku768", + "qcom,sc7180"; +}; + +&panel { + compatible =3D "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/ar= m64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi new file mode 100644 index 000000000000..49c75990954a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + avdd_lcd: avdd-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avdd_lcd"; + + gpio =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avdd_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible =3D "regulator-fixed"; + regulator-name =3D "avee_lcd"; + + gpio =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&avee_lcd_en>; + + vin-supply =3D <&pp5000_a>; + }; + + v1p8_mipi: v1p8-mipi { + compatible =3D "regulator-fixed"; + regulator-name =3D "v1p8_mipi"; + + gpio =3D <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_1800_en>; + + vin-supply =3D <&pp3300_a>; + }; +}; + +&ap_tp_i2c { + status =3D "disabled"; +}; + +&backlight { + pwms =3D <&cros_ec_pwm 0>; +}; + +&camcc { + status =3D "okay"; +}; + +&dsi0 { + + panel: panel@0 { + reg =3D <0>; + enable-gpios =3D <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_reset_1800>; + avdd-supply =3D <&avdd_lcd>; + avee-supply =3D <&avee_lcd>; + pp1800-supply =3D <&v1p8_mipi>; + pp3300-supply =3D <&pp3300_dx_edp>; + backlight =3D <&backlight>; + rotation =3D <270>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; + clock-frequency =3D <400000>; + + ap_ts: touchscreen@5d { + compatible =3D "goodix,gt7375p"; + reg =3D <0x5d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply =3D <&pp3300_ts>; + }; +}; + +&pp1800_uf_cam { + status =3D "okay"; +}; + +&pp1800_wf_cam { + status =3D "okay"; +}; + +&pp2800_uf_cam { + status =3D "okay"; +}; + +&pp2800_wf_cam { + status =3D "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant =3D "GO_MRBLAND"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio =3D <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins =3D "gpio85"; + }; + pinconf { + pins =3D "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names =3D "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio87"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins =3D "gpio88"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio88"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd_en { + pinmux { + pins =3D "gpio21"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio21"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins =3D "gpio86"; + function =3D "gpio"; + }; + + pinconf { + pins =3D "gpio86"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.31.0