From nobody Sun May 10 18:33:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEFD8C433F5 for ; Wed, 27 Apr 2022 07:53:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359156AbiD0H5G (ORCPT ); Wed, 27 Apr 2022 03:57:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359138AbiD0H45 (ORCPT ); Wed, 27 Apr 2022 03:56:57 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62416144DDA; Wed, 27 Apr 2022 00:53:47 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id DC3E922248; Wed, 27 Apr 2022 09:53:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1651046025; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DJ+JVV6J1GmFzoijuIZAOgNfLf+/ye6hsTvF19I8ivU=; b=vETvq7iISJndT7F2b1obdYRc8p/yqR1iv39ldM3clYK6VQ7AmXbIHg42Zr7xBnJZvTUgk5 ugTbLhIEDKtfBWRxn4JfGBphdwcwUQQG43GUnCj6Q0SqBYgJ6PRftzQ6n3U5CmiT6nvMQB sXPcNm1o6eHwf8A4KLLLxV+8Ql+oSao= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski Cc: Li Yang , Michael Walle , Shawn Guo , Thomas Gleixner , Marc Zyngier , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] ARM: dts: ls1021a: reduce the interrupt-map-mask Date: Wed, 27 Apr 2022 09:53:35 +0200 Message-Id: <20220427075338.1156449-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220427075338.1156449-1-michael@walle.cc> References: <20220427075338.1156449-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reduce the interrupt-map-mask of the external interrupt controller to 7 to align with the devicetree schema. Signed-off-by: Michael Walle --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2e69d6eab4d1..5354104cae12 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -192,7 +192,7 @@ extirq: interrupt-controller@1ac { <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0x7 0x0>; }; }; =20 --=20 2.30.2 From nobody Sun May 10 18:33:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77100C433F5 for ; Wed, 27 Apr 2022 07:54:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359178AbiD0H5L (ORCPT ); Wed, 27 Apr 2022 03:57:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359139AbiD0H45 (ORCPT ); Wed, 27 Apr 2022 03:56:57 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 718BA144DF0; Wed, 27 Apr 2022 00:53:47 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 7468922249; Wed, 27 Apr 2022 09:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1651046025; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gcuTyEAl8fBHDAyAKfO+ZMUc6CSNaKRTQvrLjq6mLNE=; b=B1q+Beee7HfLZkfm6FkYoks+RrPjBNjysiTOwYe6lQdWX3aoG/8Jw4NZjrNbBHHSgEAAHm 3o0ChWtJiZeuSYBgvgcfSjRPcjs2wXQgZ8Ky1BRGMBRcQCYSXTgO6UAEFs0o/ZwNbNT9y2 PnNBTGv0efFpFqMcrEQNgob1T1PDimo= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski Cc: Li Yang , Michael Walle , Shawn Guo , Thomas Gleixner , Marc Zyngier , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] arm64: dts: freescale: reduce the interrup-map-mask Date: Wed, 27 Apr 2022 09:53:36 +0200 Message-Id: <20220427075338.1156449-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220427075338.1156449-1-michael@walle.cc> References: <20220427075338.1156449-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reduce the interrupt-map-mask of the external interrupt controller to 0xf to align with the devicetree schema. Signed-off-by: Michael Walle --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1043a.dtsi index 35d1939e690b..46cc8d45ca65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -335,7 +335,7 @@ extirq: interrupt-controller@1ac { <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0xf 0x0>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1046a.dtsi index 4e7bd04d9798..3e8def8fe1b4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -341,7 +341,7 @@ extirq: interrupt-controller@1ac { <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0xf 0x0>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1088a.dtsi index 18e529118476..33c5ad1b9b96 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -265,7 +265,7 @@ extirq: interrupt-controller@14 { <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0xf 0x0>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls208xa.dtsi index 1282b61da8a5..3f767994b02d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -305,7 +305,7 @@ extirq: interrupt-controller@14 { <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0xf 0x0>; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-lx2160a.dtsi index 82bd8c0f318b..47ea854720ce 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -698,7 +698,7 @@ extirq: interrupt-controller@14 { <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; + interrupt-map-mask =3D <0xf 0x0>; }; }; =20 --=20 2.30.2 From nobody Sun May 10 18:33:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C4B4C433F5 for ; Wed, 27 Apr 2022 07:54:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359189AbiD0H5O (ORCPT ); Wed, 27 Apr 2022 03:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359141AbiD0H5B (ORCPT ); Wed, 27 Apr 2022 03:57:01 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75B75145845; Wed, 27 Apr 2022 00:53:48 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id E55DB2224D; Wed, 27 Apr 2022 09:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1651046026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c8md0w7nTqGQ2WYhNmFqixpQ0s9YgN3QXjIFu39VBh0=; b=uO9TCJkvgR02p9dHf+IqBSj/GTs0FSB18noOSS5R5pUmXa9F/CkDd1wtBqpVwk4uuBq0EM /qPRAVeQwT86SD7HzkgVp+bcv3Kz07zr/lFy/WYLcUB5Cj7GtSfAKmkxnM2LEum0wG+nkm ef4VyieYBshjzDGdfwn1A7zS7fLdUEE= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski Cc: Li Yang , Michael Walle , Shawn Guo , Thomas Gleixner , Marc Zyngier , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: interrupt-controller: fsl,ls-extirq: convert to YAML Date: Wed, 27 Apr 2022 09:53:37 +0200 Message-Id: <20220427075338.1156449-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220427075338.1156449-1-michael@walle.cc> References: <20220427075338.1156449-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the fsl,ls-extirq binding to the new YAML format. In contrast to the original binding documentation, there are three compatibles which are used in their corresponding device trees which have a specific compatible and the (already documented) fallback compatible: - "fsl,ls1046a-extirq", "fsl,ls1043a-extirq" - "fsl,ls2080a-extirq", "fsl,ls1088a-extirq" - "fsl,lx2160a-extirq", "fsl,ls1088a-extirq" Depending on the number of the number of the external IRQs which is usually 12 except for the LS1021A where there are only 6, the interrupt-map-mask was reduced from 0xffffffff to 0xf and 0x7 respectively and the number of interrupt-map entries have to match. Signed-off-by: Michael Walle Reviewed-by: Krzysztof Kozlowski --- changes since v2: - drop $ref to interrupt-controller.yaml - use a more strict interrupt-map-mask and make it conditional on SoC changes since v1: - new patch .../interrupt-controller/fsl,ls-extirq.txt | 53 -------- .../interrupt-controller/fsl,ls-extirq.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= fsl,ls-extirq.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= fsl,ls-extirq.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-= extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-= extirq.txt deleted file mode 100644 index 4d47df1a5c91..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.= txt +++ /dev/null @@ -1,53 +0,0 @@ -* Freescale Layerscape external IRQs - -Some Layerscape SOCs (LS1021A, LS1043A, LS1046A -LS1088A, LS208xA, LX216xA) support inverting -the polarity of certain external interrupt lines. - -The device node must be a child of the node representing the -Supplemental Configuration Unit (SCFG). - -Required properties: -- compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". - "fsl,ls1043a-extirq": for LS1043A, LS1046A. - "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA. -- #interrupt-cells: Must be 2. The first element is the index of the - external interrupt line. The second element is the trigger type. -- #address-cells: Must be 0. -- interrupt-controller: Identifies the node as an interrupt controller -- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in - the SCFG or the External Interrupt Control Register (IRQCR) in - the ISC. -- interrupt-map: Specifies the mapping from external interrupts to GIC - interrupts. -- interrupt-map-mask: Must be <0xffffffff 0>. - -Example: - scfg: scfg@1570000 { - compatible =3D "fsl,ls1021a-scfg", "syscon"; - reg =3D <0x0 0x1570000 0x0 0x10000>; - big-endian; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0x0 0x0 0x1570000 0x10000>; - - extirq: interrupt-controller@1ac { - compatible =3D "fsl,ls1021a-extirq"; - #interrupt-cells =3D <2>; - #address-cells =3D <0>; - interrupt-controller; - reg =3D <0x1ac 4>; - interrupt-map =3D - <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask =3D <0xffffffff 0x0>; - }; - }; - - - interrupts-extended =3D <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <&extirq 1 IRQ_TYPE_LEVEL_LOW>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-= extirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls= -extirq.yaml new file mode 100644 index 000000000000..887e565b9573 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.= yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape External Interrupt Controller + +maintainers: + - Shawn Guo + - Li Yang + +description: | + Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA, + LX216xA) support inverting the polarity of certain external interrupt + lines. + +properties: + compatible: + oneOf: + - enum: + - fsl,ls1021a-extirq + - fsl,ls1043a-extirq + - fsl,ls1088a-extirq + - items: + - enum: + - fsl,ls1046a-extirq + - const: fsl,ls1043a-extirq + - items: + - enum: + - fsl,ls2080a-extirq + - fsl,lx2160a-extirq + - const: fsl,ls1088a-extirq + + '#interrupt-cells': + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + description: + Specifies the Interrupt Polarity Control Register (INTPCR) in the + SCFG or the External Interrupt Control Register (IRQCR) in the ISC. + + interrupt-map: + description: Specifies the mapping from external interrupts to GIC int= errupts. + + interrupt-map-mask: true + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + - interrupt-map + - interrupt-map-mask + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1021a-extirq + then: + properties: + interrupt-map: + minItems: 6 + maxItems: 6 + interrupt-map-mask: + items: + - const: 0x7 + - const: 0 + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1043a-extirq + - fsl,ls1046a-extirq + - fsl,ls1088a-extirq + - fsl,ls2080a-extirq + - fsl,lx2160a-extirq + then: + properties: + interrupt-map: + minItems: 12 + maxItems: 12 + interrupt-map-mask: + items: + - const: 0xf + - const: 0 + +additionalProperties: false + +examples: + - | + #include + interrupt-controller@1ac { + compatible =3D "fsl,ls1021a-extirq"; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x1ac 4>; + interrupt-map =3D + <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0x7 0x0>; + }; --=20 2.30.2 From nobody Sun May 10 18:33:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41023C433F5 for ; Wed, 27 Apr 2022 07:54:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359196AbiD0H5U (ORCPT ); Wed, 27 Apr 2022 03:57:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359142AbiD0H5B (ORCPT ); Wed, 27 Apr 2022 03:57:01 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E808814585A; Wed, 27 Apr 2022 00:53:48 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id DD49C2224E; Wed, 27 Apr 2022 09:53:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1651046027; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bHj8Kou7jO8BNYgik9QQT7XahJy0bju+c9x5EmPkq+Y=; b=K41lDRsp12VRgR/KMTqpEQY6DXk/ODC8VQLswwqFjFoVaVZAgh7vKd0E4rngFNFvjRBfOH FxCJUwcQhwzBb2tlcRrLaX4juliKKH0HW/QkuL0GbCeLlh73K0KugFVKpQ43Ehoo5LiMSE d8RV4NLT65Jzvd3oOPVY7Q5eZCU3/JE= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski Cc: Li Yang , Michael Walle , Shawn Guo , Thomas Gleixner , Marc Zyngier , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 4/4] dt-bindings: fsl: convert fsl,layerscape-scfg to YAML Date: Wed, 27 Apr 2022 09:53:38 +0200 Message-Id: <20220427075338.1156449-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220427075338.1156449-1-michael@walle.cc> References: <20220427075338.1156449-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the fsl,layerscape-scfg binding to the new YAML format. In the device trees, the device node always have a "syscon" compatible, which wasn't mentioned in the previous binding. Also added, compared to the original binding, is the interrupt-controller subnode as used in arch/arm/boot/dts/ls1021a.dtsi as well as the litte-endian and big-endian properties. Signed-off-by: Michael Walle Reviewed-by: Krzysztof Kozlowski --- changes since v2: - none changes since v1: - moved to soc/fsl/fsl,layerscape-scfg.yaml - generic name for node in example - mention added "syscon" compatible in commit message - reference specific interrupt controller .../arm/freescale/fsl,layerscape-scfg.txt | 19 ------ .../bindings/soc/fsl/fsl,layerscape-scfg.yaml | 58 +++++++++++++++++++ 2 files changed, 58 insertions(+), 19 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,lay= erscape-scfg.txt create mode 100644 Documentation/devicetree/bindings/soc/fsl/fsl,layerscap= e-scfg.yaml diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape= -scfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-= scfg.txt deleted file mode 100644 index 0ab67b0b216d..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.t= xt +++ /dev/null @@ -1,19 +0,0 @@ -Freescale SCFG - -SCFG is the supplemental configuration unit, that provides SoC specific -configuration and status registers for the chip. Such as getting PEX port -status. - -Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,-scfg", - The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg: should contain base address and length of SCFG memory-mapped regi= sters - -Example: - scfg: scfg@1570000 { - compatible =3D "fsl,ls1021a-scfg"; - reg =3D <0x0 0x1570000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.= yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml new file mode 100644 index 000000000000..8d088b5fe823 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape Supplemental Configuration Unit + +maintainers: + - Shawn Guo + - Li Yang + +description: | + SCFG is the supplemental configuration unit, that provides SoC specific + configuration and status registers for the chip. Such as getting PEX port + status. + +properties: + compatible: + items: + - enum: + - fsl,ls1012a-scfg + - fsl,ls1021a-scfg + - fsl,ls1028a-scfg + - fsl,ls1043a-scfg + - fsl,ls1046a-scfg + - const: syscon + + reg: + maxItems: 1 + + little-endian: true + big-endian: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^interrupt-controller@[a-z0-9]+$": + $ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@1570000 { + compatible =3D "fsl,ls1021a-scfg", "syscon"; + reg =3D <0x1570000 0x10000>; + }; --=20 2.30.2