From nobody Sun Sep 22 05:41:05 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65F73C433EF for ; Wed, 27 Apr 2022 03:13:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357249AbiD0DQV (ORCPT ); Tue, 26 Apr 2022 23:16:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357417AbiD0DPk (ORCPT ); Tue, 26 Apr 2022 23:15:40 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D3A12AAC; Tue, 26 Apr 2022 20:12:28 -0700 (PDT) X-UUID: 50b315ba0c3a4f0d8444d5f4245ccad8-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:3d699a84-c96e-4296-9868-db596b0b36fb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:1603d42e-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 50b315ba0c3a4f0d8444d5f4245ccad8-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1804241659; Wed, 27 Apr 2022 11:12:23 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:22 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 15/15] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Date: Wed, 27 Apr 2022 11:09:50 +0800 Message-ID: <20220427030950.23395-16-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon. To support this, remove the property of ti reset and add the property of #reset-cells for mediatek clock reset. Fixes: 4c78814a1f46ac0 (arm64: dts: Add mediatek SoC mt8195 and evaluation = board) Signed-off-by: Rex-BC Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index b57e620c2c72..8e5ac11b19f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include #include #include -#include =20 / { compatible =3D "mediatek,mt8195"; @@ -295,17 +294,7 @@ compatible =3D "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; - - infracfg_rst: reset-controller { - compatible =3D "ti,syscon-reset"; - #reset-cells =3D <1>; - ti,reset-bits =3D < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pc= ie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* sv= s gpu */ - >; - }; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { --=20 2.18.0