From nobody Sun May 10 19:51:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0699C433F5 for ; Tue, 26 Apr 2022 02:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241921AbiDZCDD (ORCPT ); Mon, 25 Apr 2022 22:03:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241806AbiDZCCu (ORCPT ); Mon, 25 Apr 2022 22:02:50 -0400 Received: from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com [72.21.196.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B3E51229CC; Mon, 25 Apr 2022 18:59:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1650938386; x=1682474386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2kGoDhwDDU4SUv0yonPrLgPdKoDB23uSHWFWBT2qSyo=; b=m6uScNj85j4uttDCIhRFL1MTX1ytFCkp2HSKgEPu+8pVO6+zLVUM5aKk HduDF4L2kzH9n6iFtFdmlgTUBj6L7izCIHKbcn9tW6RFut8hZfRsImQzY 8NeZpxj5dymKNk1VLI6X743I7WF8xNgNsbb6Z19eHHcmuQunDiZVspp3a 4=; X-IronPort-AV: E=Sophos;i="5.90,289,1643673600"; d="scan'208";a="192942726" Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-pdx-2a-11a39b7d.us-west-2.amazon.com) ([10.43.8.2]) by smtp-border-fw-2101.iad2.amazon.com with ESMTP; 26 Apr 2022 01:59:42 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan3.pdx.amazon.com [10.236.137.198]) by email-inbound-relay-pdx-2a-11a39b7d.us-west-2.amazon.com (Postfix) with ESMTPS id C443F40FA6; Tue, 26 Apr 2022 01:59:40 +0000 (UTC) Received: from EX13D02UWC004.ant.amazon.com (10.43.162.236) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from EX13MTAUEB002.ant.amazon.com (10.43.60.12) by EX13D02UWC004.ant.amazon.com (10.43.162.236) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.60.234) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Tue, 26 Apr 2022 01:59:33 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id C166520BE; Tue, 26 Apr 2022 01:59:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 1/5] perf: Add SNOOP_PEER flag to perf mem data struct Date: Tue, 26 Apr 2022 01:59:22 +0000 Message-ID: <20220426015926.22011-2-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220426015926.22011-1-alisaidi@amazon.com> References: <20220426015926.22011-1-alisaidi@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a flag to the perf mem data struct to signal that a request caused a cache-to-cache transfer of a line from a peer of the requestor and wasn't sourced from a lower cache level. The line being moved from one peer cache to another has latency and performance implications. On Arm64 Neoverse systems the data source can indicate a cache-to-cache transfer but not if the line is dirty or clean, so instead of overloading HITM define a new flag that indicates this type of transfer. Signed-off-by: Ali Saidi Reviewed-by: Leo Yan --- include/uapi/linux/perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index d37629dbad72..7b88bfd097dc 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1310,7 +1310,7 @@ union perf_mem_data_src { #define PERF_MEM_SNOOP_SHIFT 19 =20 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ -/* 1 free */ +#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ #define PERF_MEM_SNOOPX_SHIFT 38 =20 /* locked instruction */ --=20 2.32.0 From nobody Sun May 10 19:51:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE078C433F5 for ; Tue, 26 Apr 2022 01:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241913AbiDZCCw (ORCPT ); Mon, 25 Apr 2022 22:02:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241735AbiDZCCt (ORCPT ); Mon, 25 Apr 2022 22:02:49 -0400 Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB3CE12197D; Mon, 25 Apr 2022 18:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1650938384; x=1682474384; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g7YWa84Ggc9PbBc2yEEwZ6f7hUrSoU1ylmKnDzAKmLc=; b=RZyhxnA03enLNgj4Mu6mF9sn4hIt+Xtlm2JYgxD0vQVmw6VPiiK8h+iU 4ePh0ckETpD1H4LZ5k3eGr5xMyRi50bdMMHfCMGyfzkiudc8KB6oel/gd qXWMy3BOaYtnLjH3A1rHsN3eEF3y3XxHz7dJkQFTUteoFml/ghzaexdQn w=; X-IronPort-AV: E=Sophos;i="5.90,289,1643673600"; d="scan'208";a="196211016" Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-pdx-2c-9ec26c6c.us-west-2.amazon.com) ([10.43.8.2]) by smtp-border-fw-6002.iad6.amazon.com with ESMTP; 26 Apr 2022 01:59:41 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2c-9ec26c6c.us-west-2.amazon.com (Postfix) with ESMTPS id DCEFA414D1; Tue, 26 Apr 2022 01:59:34 +0000 (UTC) Received: from EX13D02UWC001.ant.amazon.com (10.43.162.243) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from EX13MTAUWC001.ant.amazon.com (10.43.162.135) by EX13D02UWC001.ant.amazon.com (10.43.162.243) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.162.232) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Tue, 26 Apr 2022 01:59:34 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id C263620CB; Tue, 26 Apr 2022 01:59:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 2/5] perf tools: sync addition of PERF_MEM_SNOOPX_PEER Date: Tue, 26 Apr 2022 01:59:23 +0000 Message-ID: <20220426015926.22011-3-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220426015926.22011-1-alisaidi@amazon.com> References: <20220426015926.22011-1-alisaidi@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a flag to the perf mem data struct to signal that a request caused a cache-to-cache transfer of a line from a peer of the requestor and wasn't sourced from a lower cache level. The line being moved from one peer cache to another has latency and performance implications. On Arm64 Neoverse systems the data source can indicate a cache-to-cache transfer but not if the line is dirty or clean, so instead of overloading HITM define a new flag that indicates this type of transfer. Signed-off-by: Ali Saidi Reviewed-by: Leo Yan --- tools/include/uapi/linux/perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/lin= ux/perf_event.h index d37629dbad72..7b88bfd097dc 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -1310,7 +1310,7 @@ union perf_mem_data_src { #define PERF_MEM_SNOOP_SHIFT 19 =20 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ -/* 1 free */ +#define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ #define PERF_MEM_SNOOPX_SHIFT 38 =20 /* locked instruction */ --=20 2.32.0 From nobody Sun May 10 19:51:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09AE4C433F5 for ; Tue, 26 Apr 2022 02:00:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237834AbiDZCDb (ORCPT ); Mon, 25 Apr 2022 22:03:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242318AbiDZCDS (ORCPT ); Mon, 25 Apr 2022 22:03:18 -0400 Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D88E65BC; Mon, 25 Apr 2022 19:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1650938408; x=1682474408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IC8noDBK4X51feo0Vpeik5XnaP2Xw/g4NSKwFbVg0tA=; b=vLGPj0GrD4YPOPqIk+cZ3o+fPfIctF3EEat2gzPKIhz1aUf/sUMWyACX 3Fs7FW0YXELiL7hOrI1ETzGldjwQkjqVGe96mVX4RroEEJOjgo18aXwBi Cg8C0WPykMLhVIK/PkBP69QNWe0cRiifkPmj612c0QIiIERW+0hc8hXuv A=; X-IronPort-AV: E=Sophos;i="5.90,289,1643673600"; d="scan'208";a="213855622" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO email-inbound-relay-iad-1a-828bd003.us-east-1.amazon.com) ([10.25.36.214]) by smtp-border-fw-9102.sea19.amazon.com with ESMTP; 26 Apr 2022 02:00:05 +0000 Received: from EX13MTAUWB001.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-iad-1a-828bd003.us-east-1.amazon.com (Postfix) with ESMTPS id 676398128D; Tue, 26 Apr 2022 01:59:58 +0000 (UTC) Received: from EX13D02UWB001.ant.amazon.com (10.43.161.240) by EX13MTAUWB001.ant.amazon.com (10.43.161.249) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from EX13MTAUWB001.ant.amazon.com (10.43.161.207) by EX13D02UWB001.ant.amazon.com (10.43.161.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.161.249) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Tue, 26 Apr 2022 01:59:34 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id C5AFE20DB; Tue, 26 Apr 2022 01:59:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 3/5] perf mem: Print snoop peer flag Date: Tue, 26 Apr 2022 01:59:24 +0000 Message-ID: <20220426015926.22011-4-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220426015926.22011-1-alisaidi@amazon.com> References: <20220426015926.22011-1-alisaidi@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Leo Yan Since PERF_MEM_SNOOPX_PEER flag is a new snoop type, print this flag if it is set. Before: memstress 3603 [020] 122.463754: 1 l1d-miss: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 l1d-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-miss: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 tlb-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 memory: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP N/A|TLB Walker hit|LCK No|BL= K N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) After: memstress 3603 [020] 122.463754: 1 l1d-miss: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 l1d-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-miss: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 llc-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 tlb-access: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) memstress 3603 [020] 122.463754: 1 memory: = 8688000842 |OP LOAD|LVL L3 or L3 hit|SNP Peer|TLB Walker hit|LCK No|B= LK N/A aaaac17c3e88 [unknown] (/home/ubuntu/memstress) Signed-off-by: Leo Yan Reviewed-by: Ali Saidi Tested-by: Ali Saidi --- tools/perf/util/mem-events.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index efaf263464b9..db5225caaabe 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -410,6 +410,11 @@ static const char * const snoop_access[] =3D { "HitM", }; =20 +static const char * const snoopx_access[] =3D { + "Fwd", + "Peer", +}; + int perf_mem__snp_scnprintf(char *out, size_t sz, struct mem_info *mem_inf= o) { size_t i, l =3D 0; @@ -430,13 +435,20 @@ int perf_mem__snp_scnprintf(char *out, size_t sz, str= uct mem_info *mem_info) } l +=3D scnprintf(out + l, sz - l, snoop_access[i]); } - if (mem_info && - (mem_info->data_src.mem_snoopx & PERF_MEM_SNOOPX_FWD)) { + + m =3D 0; + if (mem_info) + m =3D mem_info->data_src.mem_snoopx; + + for (i =3D 0; m && i < ARRAY_SIZE(snoopx_access); i++, m >>=3D 1) { + if (!(m & 0x1)) + continue; + if (l) { strcat(out, " or "); l +=3D 4; } - l +=3D scnprintf(out + l, sz - l, "Fwd"); + l +=3D scnprintf(out + l, sz - l, snoopx_access[i]); } =20 if (*out =3D=3D '\0') --=20 2.32.0 From nobody Sun May 10 19:51:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B71BC433F5 for ; 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Tue, 26 Apr 2022 01:59:33 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id C362820D6; Tue, 26 Apr 2022 01:59:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 4/5] perf arm-spe: Don't set data source if it's not a memory operation Date: Tue, 26 Apr 2022 01:59:25 +0000 Message-ID: <20220426015926.22011-5-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220426015926.22011-1-alisaidi@amazon.com> References: <20220426015926.22011-1-alisaidi@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Leo Yan Except memory load and store operations, Arm SPE records also can support other operation types, bug when set the data source field the current code assumes a record is a either load operation or store operation, this leads to wrongly synthesize memory samples. This patch strictly checks the record operation type, it only sets data source only for the operation types ARM_SPE_LD and ARM_SPE_ST, otherwise, returns zero for data source. Therefore, we can synthesize memory samples only when data source is a non-zero value, the function arm_spe__is_memory_event() is useless and removed. Signed-off-by: Leo Yan Reviewed-by: Ali Saidi Tested-by: Ali Saidi --- tools/perf/util/arm-spe.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index d2b64e3f588b..76251825c01d 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -387,26 +387,16 @@ static int arm_spe__synth_instruction_sample(struct a= rm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } =20 -#define SPE_MEM_TYPE (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \ - ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \ - ARM_SPE_REMOTE_ACCESS) - -static bool arm_spe__is_memory_event(enum arm_spe_sample_type type) -{ - if (type & SPE_MEM_TYPE) - return true; - - return false; -} - static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) { union perf_mem_data_src data_src =3D { 0 }; =20 if (record->op =3D=3D ARM_SPE_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; - else + else if (record->op & ARM_SPE_ST) data_src.mem_op =3D PERF_MEM_OP_STORE; + else + return 0; =20 if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { data_src.mem_lvl =3D PERF_MEM_LVL_L3; @@ -510,7 +500,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq) return err; } =20 - if (spe->sample_memory && arm_spe__is_memory_event(record->type)) { + /* + * When data_src is zero it means the record is not a memory operation, + * skip to synthesize memory sample for this case. + */ + if (spe->sample_memory && data_src) { err =3D arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err; --=20 2.32.0 From nobody Sun May 10 19:51:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA104C433FE for ; Tue, 26 Apr 2022 01:59:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241858AbiDZCCv (ORCPT ); Mon, 25 Apr 2022 22:02:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241745AbiDZCCt (ORCPT ); Mon, 25 Apr 2022 22:02:49 -0400 Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B41B1229C2; Mon, 25 Apr 2022 18:59:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1650938383; x=1682474383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rC1MlZNl8mQZ6vzpsAGRx48MMRV71nfzeKa4CmcIlQ8=; b=kOuE9NcWfhg0kUBZuH659aBq1dJGZ7XNo9oNYjSkjjpiOD8K6xRlzsQb +d5HGs+oIJTxTIxsGl+dD0R7abIY1hI/DpnuCSKjZ0+wX3tNhcBaaYkTF C/4wWnE/NxRV8JW1cdVWso9IzvLbgEyywZBspJd29qgjThFWKJXckMg44 c=; X-IronPort-AV: E=Sophos;i="5.90,289,1643673600"; d="scan'208";a="82994482" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-pdx-2a-6a4112b2.us-west-2.amazon.com) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP; 26 Apr 2022 01:59:43 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2a-6a4112b2.us-west-2.amazon.com (Postfix) with ESMTPS id D07204C8CDB; Tue, 26 Apr 2022 01:59:41 +0000 (UTC) Received: from EX13D02UWC003.ant.amazon.com (10.43.162.199) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from EX13MTAUEB002.ant.amazon.com (10.43.60.12) by EX13D02UWC003.ant.amazon.com (10.43.162.199) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 26 Apr 2022 01:59:34 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.60.234) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Tue, 26 Apr 2022 01:59:33 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id C487620DA; Tue, 26 Apr 2022 01:59:33 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 5/5] perf arm-spe: Use SPE data source for neoverse cores Date: Tue, 26 Apr 2022 01:59:26 +0000 Message-ID: <20220426015926.22011-6-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220426015926.22011-1-alisaidi@amazon.com> References: <20220426015926.22011-1-alisaidi@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When synthesizing data from SPE, augment the type with source information for Arm Neoverse cores. The field is IMPLDEF but the Neoverse cores all use the same encoding. I can't find encoding information for any other SPE implementations to unify their choices with Arm's thus that is left for future work. This change populates the mem_lvl_num for Neoverse cores as well as the deprecated mem_lvl namespace. Signed-off-by: Ali Saidi --- .../util/arm-spe-decoder/arm-spe-decoder.c | 1 + .../util/arm-spe-decoder/arm-spe-decoder.h | 12 ++ tools/perf/util/arm-spe.c | 130 +++++++++++++++--- 3 files changed, 127 insertions(+), 16 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.c index 5e390a1a79ab..091987dd3966 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -220,6 +220,7 @@ static int arm_spe_read_record(struct arm_spe_decoder *= decoder) =20 break; case ARM_SPE_DATA_SOURCE: + decoder->record.source =3D payload; break; case ARM_SPE_BAD: break; diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.h index 69b31084d6be..46a61df1145b 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -29,6 +29,17 @@ enum arm_spe_op_type { ARM_SPE_ST =3D 1 << 1, }; =20 +enum arm_spe_neoverse_data_source { + ARM_SPE_NV_L1D =3D 0x0, + ARM_SPE_NV_L2 =3D 0x8, + ARM_SPE_NV_PEER_CORE =3D 0x9, + ARM_SPE_NV_LOCAL_CLUSTER =3D 0xa, + ARM_SPE_NV_SYS_CACHE =3D 0xb, + ARM_SPE_NV_PEER_CLUSTER =3D 0xc, + ARM_SPE_NV_REMOTE =3D 0xd, + ARM_SPE_NV_DRAM =3D 0xe, +}; + struct arm_spe_record { enum arm_spe_sample_type type; int err; @@ -40,6 +51,7 @@ struct arm_spe_record { u64 virt_addr; u64 phys_addr; u64 context_id; + u16 source; }; =20 struct arm_spe_insn; diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 76251825c01d..4065fa180140 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -34,6 +34,7 @@ #include "arm-spe-decoder/arm-spe-decoder.h" #include "arm-spe-decoder/arm-spe-pkt-decoder.h" =20 +#include "../../arch/arm64/include/asm/cputype.h" #define MAX_TIMESTAMP (~0ULL) =20 struct arm_spe { @@ -45,6 +46,7 @@ struct arm_spe { struct perf_session *session; struct machine *machine; u32 pmu_type; + u64 midr; =20 struct perf_tsc_conversion tc; =20 @@ -387,35 +389,128 @@ static int arm_spe__synth_instruction_sample(struct = arm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } =20 -static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) +static const struct midr_range neoverse_spe[] =3D { + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + {}, +}; + +static void arm_spe__synth_data_source_neoverse(const struct arm_spe_recor= d *record, + union perf_mem_data_src *data_src) { - union perf_mem_data_src data_src =3D { 0 }; + /* + * Even though four levels of cache hierarchy are possible, no known + * production Neoverse systems currently include more than three levels + * so for the time being we assume three exist. If a production system + * is built with four the this function would have to be changed to + * detect the number of levels for reporting. + */ =20 - if (record->op =3D=3D ARM_SPE_LD) - data_src.mem_op =3D PERF_MEM_OP_LOAD; - else if (record->op & ARM_SPE_ST) - data_src.mem_op =3D PERF_MEM_OP_STORE; - else - return 0; + /* + * We have no data on the hit level or data source for stores in the + * Neoverse SPE records. + */ + if (record->op & ARM_SPE_ST) { + data_src->mem_lvl =3D PERF_MEM_LVL_NA; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_ANY_CACHE; + data_src->mem_snoop =3D PERF_MEM_SNOOP_NA; + return; + } + + switch (record->source) { + case ARM_SPE_NV_L1D: + data_src->mem_lvl =3D PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L1; + data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; + break; + case ARM_SPE_NV_L2: + data_src->mem_lvl =3D PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L2; + data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; + break; + case ARM_SPE_NV_PEER_CORE: + data_src->mem_lvl =3D PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L2; + data_src->mem_snoopx =3D PERF_MEM_SNOOPX_PEER; + break; + /* + * We don't know if this is L1, L2 but we do know it was a cache-2-cache + * transfer, so set SNOOPX_PEER + */ + case ARM_SPE_NV_LOCAL_CLUSTER: + case ARM_SPE_NV_PEER_CLUSTER: + data_src->mem_lvl =3D PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L3; + data_src->mem_snoopx =3D PERF_MEM_SNOOPX_PEER; + break; + /* + * System cache is assumed to be L3 + */ + case ARM_SPE_NV_SYS_CACHE: + data_src->mem_lvl =3D PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L3; + data_src->mem_snoop =3D PERF_MEM_SNOOP_HIT; + break; + /* + * We don't know what level it hit in, except it came from the other + * socket + */ + case ARM_SPE_NV_REMOTE: + data_src->mem_lvl =3D PERF_MEM_LVL_REM_RAM1 | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_RAM; + data_src->mem_remote =3D PERF_MEM_REMOTE_REMOTE; + data_src->mem_snoop =3D PERF_MEM_SNOOP_NA; + break; + case ARM_SPE_NV_DRAM: + data_src->mem_lvl =3D PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT; + data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_RAM; + data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; + break; + default: + break; + } +} =20 +static void arm_spe__synth_data_source_generic(const struct arm_spe_record= *record, + union perf_mem_data_src *data_src) +{ if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { - data_src.mem_lvl =3D PERF_MEM_LVL_L3; + data_src->mem_lvl =3D PERF_MEM_LVL_L3; =20 if (record->type & ARM_SPE_LLC_MISS) - data_src.mem_lvl |=3D PERF_MEM_LVL_MISS; + data_src->mem_lvl |=3D PERF_MEM_LVL_MISS; else - data_src.mem_lvl |=3D PERF_MEM_LVL_HIT; + data_src->mem_lvl |=3D PERF_MEM_LVL_HIT; } else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) { - data_src.mem_lvl =3D PERF_MEM_LVL_L1; + data_src->mem_lvl =3D PERF_MEM_LVL_L1; =20 if (record->type & ARM_SPE_L1D_MISS) - data_src.mem_lvl |=3D PERF_MEM_LVL_MISS; + data_src->mem_lvl |=3D PERF_MEM_LVL_MISS; else - data_src.mem_lvl |=3D PERF_MEM_LVL_HIT; + data_src->mem_lvl |=3D PERF_MEM_LVL_HIT; } =20 if (record->type & ARM_SPE_REMOTE_ACCESS) - data_src.mem_lvl |=3D PERF_MEM_LVL_REM_CCE1; + data_src->mem_lvl |=3D PERF_MEM_LVL_REM_CCE1; +} + +static u64 arm_spe__synth_data_source(const struct arm_spe_record *record,= u64 midr) +{ + union perf_mem_data_src data_src =3D { 0 }; + bool is_neoverse =3D is_midr_in_range(midr, neoverse_spe); + + if (record->op =3D=3D ARM_SPE_LD) + data_src.mem_op =3D PERF_MEM_OP_LOAD; + else if (record->op =3D=3D ARM_SPE_ST) + data_src.mem_op =3D PERF_MEM_OP_STORE; + else + return 0; + + if (is_neoverse) + arm_spe__synth_data_source_neoverse(record, &data_src); + else + arm_spe__synth_data_source_generic(record, &data_src); =20 if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) { data_src.mem_dtlb =3D PERF_MEM_TLB_WK; @@ -436,7 +531,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; =20 - data_src =3D arm_spe__synth_data_source(record); + data_src =3D arm_spe__synth_data_source(record, spe->midr); =20 if (spe->sample_flc) { if (record->type & ARM_SPE_L1D_MISS) { @@ -1177,6 +1272,8 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, struct perf_record_auxtrace_info *auxtrace_info =3D &event->auxtrace_info; size_t min_sz =3D sizeof(u64) * ARM_SPE_AUXTRACE_PRIV_MAX; struct perf_record_time_conv *tc =3D &session->time_conv; + const char *cpuid =3D perf_env__cpuid(session->evlist->env); + u64 midr =3D strtol(cpuid, NULL, 16); struct arm_spe *spe; int err; =20 @@ -1196,6 +1293,7 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, spe->machine =3D &session->machines.host; /* No kvm support */ spe->auxtrace_type =3D auxtrace_info->type; spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE]; + spe->midr =3D midr; =20 spe->timeless_decoding =3D arm_spe__is_timeless_decoding(spe); =20 --=20 2.32.0