From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB6AC4332F for ; Mon, 25 Apr 2022 17:13:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243774AbiDYRRA (ORCPT ); Mon, 25 Apr 2022 13:17:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243594AbiDYRQ4 (ORCPT ); Mon, 25 Apr 2022 13:16:56 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89F2D1707E; Mon, 25 Apr 2022 10:13:48 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id b17so12246795qvf.12; Mon, 25 Apr 2022 10:13:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DLU7Byu++ueSPleKFASenNUYu4xE0XjTscVJ1fB23CI=; b=bCDXpHkDeJiwI3/+FK6eKtKKvdVw+nWM0xwrlOLYBuSZYGKWgtGiUBRF6SWicWNrQY VCtWoNmzt8hYvVyaqGjG2EhMOuv/0LH9d5aEjh5Ywo9vXRxGwO4jhV+U4OXwdsL2AUxZ DGHD1kQP4S33ULejyh3VniTF1vCqwYvFNm6IzUnM9dlCRhYT0Iamdmr01IXFdKHIug2d HhhJRnosHLzkEV38kSQtymjuNOHfeJr2Tq9rEUSbmpX9EyuBGfvW8LaqwX++LY8dr247 T9TXLNVVAeynqOmR9HQbAXqtP06x7XLz8y4vGn3kDfHWn3ra5ac9qBQNCr9dJCf1GJye kbUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DLU7Byu++ueSPleKFASenNUYu4xE0XjTscVJ1fB23CI=; b=BGaQE0v0m713L5+tn/3X9X2hBBEI+ukci2uKtxLGNVsm8LlG1eaWo2dVXDZDukAaxw YI1j/mDGvVOUNwBhCXBJAOCc2FQlkKDVr3cfHm/t+Eoe8LmdAVtDUXTxeYT/TN7tqqTT tpAH4VseLNNOXHMFe0/UGOp5W0gWH6foThQdcvqcJlyvzMEZL8yXCuvvwOJYxxheJwwM KF6xAyZZjwpc5OFqqLTzeQioOkgB8UXdZt9fQRyVgvENnH9uuUr7cOrt79xUZ7Eco10C sxa1SUQoEljwd5wNcMUyMv9CtKz27/DpE1t1s9FC58O7QcOP4D2O0Vrg/Bb7gOy/g3Ct 9pdg== X-Gm-Message-State: AOAM530XNvP93OmD4hOXur5WZT3LLQiIEKFmDe6/6wZvJMGClpmQOux7 b3B8OzcKyREHfwKctSbt9gUKbEjObWR0XA== X-Google-Smtp-Source: ABdhPJwHRDB8KYA8NTouw9jD9sdzZIhMtIUI7b9FLcMDA0XemGjLUmgWw0wblhuNPVxnEKQimCdJzw== X-Received: by 2002:a05:6214:2388:b0:441:37e5:baec with SMTP id fw8-20020a056214238800b0044137e5baecmr13665169qvb.66.1650906827628; Mon, 25 Apr 2022 10:13:47 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:47 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B Date: Mon, 25 Apr 2022 13:13:38 -0400 Message-Id: <20220425171344.1924057-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Quartz64 Model B is a compact single board computer from Pine64 based on the rk3566 SoC. It outputs on uart2 for the debug console. Signed-off-by: Peter Geis --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index eece92f83a2d..d6650a366753 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -507,6 +507,11 @@ properties: - const: pine64,quartz64-a - const: rockchip,rk3566 =20 + - description: Pine64 Quartz64 Model B + items: + - const: pine64,quartz64-b + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53634C433FE for ; Mon, 25 Apr 2022 17:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243768AbiDYRQ5 (ORCPT ); Mon, 25 Apr 2022 13:16:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243750AbiDYRQ4 (ORCPT ); Mon, 25 Apr 2022 13:16:56 -0400 Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 543ED17E3F; Mon, 25 Apr 2022 10:13:49 -0700 (PDT) Received: by mail-qt1-x82b.google.com with SMTP id v2so4103697qto.6; Mon, 25 Apr 2022 10:13:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SzhN/kJ1Ng8zCdutOc3nctS/QZK6IJDtlvfBQWvSTto=; b=DpQq/Hsa5QR5ZA9qodYr092BiMhLcpbjYU+g9TwkZDltW4qBD8QreTp9GqVRRJadN9 VseBb3c5pgroMUvVAPftP2PAVwT4V7Ehtwi8zHTUnPxfpco+kzWUYig1m/ybLqrFEbvt k9Jx0ptBxg4uHyHNdipsJCujEYPsUd6wtP9RsZRwLNtgrCjgCohFrM+eRtYgxLkR6Ezn DLgSfheTbpKKKpLDePSoWTqTnXDckZ5q9c8v+Pl8sjPin4fr9oxrUBLXYeYFkOulqYiA V1VXo5IHGwaOCIZE0Ax79dylvfz+qQ4Q2bz3D8Vv8rvuGAX3EctCDRMN5MBclxz3KWAm FKhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SzhN/kJ1Ng8zCdutOc3nctS/QZK6IJDtlvfBQWvSTto=; b=pyvu52V25ANkiJl8T0AXkxI2NkqQsaNbW4zmUGncxPHC9bhrPqNW02Mo7k79UHbKZ3 J+WyRM/K92EHpfpWcC0TqPXx9vxQEA2VKzng7ZVUzXQxBO/9k3HV6ZxudR4byLdE0EZK h8plmDmL1eJjfgrCrj1fYyBOVydCeOWP6mQ+k7Dsdv8lLBAj8c6y73cRL4r+Kuc3a6lH AU3ylFLZLbZ7jiekWLHXenR6QlJO/P7njkvYxQtJBldMjZMfcsinEgDmcw35RpHdJQ3p j7VFx7RDJz8DWEfKAE4T1KSfDbZR6Mju75PvIiSX4D4UMAWJhvM+IOr+6UUJJULq0U4X tPOA== X-Gm-Message-State: AOAM530URPaL43S4mOym+lLZJ9UN9V6lgn9f6D0G2ofIL7CQmXyO7r73 D6u+tX8UIR7+QH5+DzVl82c= X-Google-Smtp-Source: ABdhPJxgdYaaCfLD97p67JumbC8icR3zvjp2z5x1tM5o4WTDF047qyxbG6wGzR56X86sQJRyLWUQYA== X-Received: by 2002:a05:622a:507:b0:2f3:57bd:1241 with SMTP id l7-20020a05622a050700b002f357bd1241mr11808542qtx.199.1650906828430; Mon, 25 Apr 2022 10:13:48 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:48 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM Date: Mon, 25 Apr 2022 13:13:39 -0400 Message-Id: <20220425171344.1924057-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SoQuartz system on module is designed to be pin compatible with the RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for debug and console. The first carrier board supported is the CM4IO board from RPi. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index d6650a366753..ad940e4127d9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -512,6 +512,13 @@ properties: - const: pine64,quartz64-b - const: rockchip,rk3566 =20 + - description: Pine64 SoQuartz SoM + items: + - enum: + - pine64,soquartz-cm4io + - const: pine64,soquartz + - const: rockchip,rk3566 + - description: Radxa Rock items: - const: radxa,rock --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0373AC4332F for ; Mon, 25 Apr 2022 17:14:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243789AbiDYRRD (ORCPT ); Mon, 25 Apr 2022 13:17:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243756AbiDYRQ4 (ORCPT ); Mon, 25 Apr 2022 13:16:56 -0400 Received: from mail-qv1-xf2c.google.com (mail-qv1-xf2c.google.com [IPv6:2607:f8b0:4864:20::f2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AEC018364; Mon, 25 Apr 2022 10:13:50 -0700 (PDT) Received: by mail-qv1-xf2c.google.com with SMTP id 1so1323931qvs.8; Mon, 25 Apr 2022 10:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s77Njj2Eom5x0HLbfJedPsYIdxNJX9SrLtCBw7r9BJI=; b=cWfu5B9KVG4HPZaLMMC3NeI9CrkUh8GOBVoOfmN6qUo+H5kY6oaJJD+9OCftTd+EmI x0V2FXej7qvvueaC/U0U7v+3OHbefL2JaM8+oFas//pE4IfJjj8MLZBFmt0+8DYfDbVh CJkMynhhbGoSJ1hS0zEyL9nr8NbaO1GnuPNFw/3IDcxpQidP26M00WTM64y3UaERiMvz vKOfS4fyuxGSMOwU6b8CyGwjvSQPNf4/RAh0m207E5eSrrIAcpF/bqQvPCjl+nzwlaSo Gzkhwz2QTnyED/MyzksxVD56lCDnVfC8LxEsdGooRX8V7J1U40HyY0MyEHAeedoXk+ss JN7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s77Njj2Eom5x0HLbfJedPsYIdxNJX9SrLtCBw7r9BJI=; b=SZ9S4N/rKigXNY+7y+FCKNu7qPUCUCdBqspcThjRNIIZGX7QQDXDNiB3E1Bs9Fdj1Q qUMGRrAJ9BIcScqq1+JhK2EmaJGgjcmpkm68YE0BRbe+tpyZzRLSmsr5oHZwpIdadwSD o/SpSRpmhLcmmpqDF5cHaoQ6iMKGM/3E5Wbo4haxdQpGEU3gFPDlnHKhoUOl0DfsIXVV pdEb0fIG2qjHcTstx1vRqng9q2GuIgkfTLB8g5S2Yp3JQvvnRmINY+gvolZCMmJk/oKr qHwJWArYrEC0giV/6zqjLEE9VMloQZEAOGXH66IwQT7dHtlJ1RHekguKJR2gxXBmRYxm nNRQ== X-Gm-Message-State: AOAM5331TzH2uirsydk0Wxs3qDWRSon3bPXuqRTLIdjtqJtYF0JkOtBg pIlzMgQCrI1+O4irI1vs/4c= X-Google-Smtp-Source: ABdhPJyro5vTEBEMuwz58jmXSQvQ7tsKDOfZB5SwaI6jAUxxh0kmIsH4yE9T9NaRpmY5OGThtkH+TA== X-Received: by 2002:a05:6214:20ab:b0:446:26a7:ef2f with SMTP id 11-20020a05621420ab00b0044626a7ef2fmr13622003qvd.37.1650906829286; Mon, 25 Apr 2022 10:13:49 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:49 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/7] dt-bindings: arm: rockchip: Add Firefly Station M2 Date: Mon, 25 Apr 2022 13:13:40 -0400 Message-Id: <20220425171344.1924057-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Station M2 is a compact single board computer based on the rk3566 SoC. It outputs on uart2 for debug and console purposes. Signed-off-by: Peter Geis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index ad940e4127d9..b6254baffa67 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -133,6 +133,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 =20 + - description: Firefly Station M2 + items: + - const: firefly,rk3566-roc-pc + - const: rockchip,rk3566 + - description: FriendlyElec NanoPi R2S items: - const: friendlyarm,nanopi-r2s --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95417C433F5 for ; Mon, 25 Apr 2022 17:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243802AbiDYRRJ (ORCPT ); Mon, 25 Apr 2022 13:17:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243759AbiDYRQ4 (ORCPT ); Mon, 25 Apr 2022 13:16:56 -0400 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EB5C13DD7; Mon, 25 Apr 2022 10:13:51 -0700 (PDT) Received: by mail-qk1-x734.google.com with SMTP id e128so11259192qkd.7; Mon, 25 Apr 2022 10:13:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zdBkDQmKoIggvVv+9nKr+EG7gevAiBpcUOqfYxzGhEU=; b=paxMNbaCwj5l3BgZd9lXV3mk+YDHGTTipw58Fdv/lu3cA8wVeGSVFUT4BcRfYY7TJ8 KFmWRn8nG2Z29rqjm72k8XN1HnSVkIxfZprfp3gH84s9xECBZ+J26J2jiJxI8WzAeS/P 9YGQ5pOgxCJC0sL7bhLQuIEN0f/bX+7KXfINO2VPnaVXTr3ByI2AIWkL846sovb6hhhn Uz9dP4c4CmE0FsHMmXXrVFIBKV+Wq7/BRbKRbnxie9kBXcoOdERewQkGzBLkUQs4G+E+ KvdMqn+Gl7HWGDzlC3t2CsoRUyQRIsHlN5dlyJ2nIbI8ri+GwpIpPt8241yPRxtuxDCP JxJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zdBkDQmKoIggvVv+9nKr+EG7gevAiBpcUOqfYxzGhEU=; b=k1VeV790DM16bxO6xv4cug4U6GDQHLQV6W0boplYRyr1Q2JhiAXzwd6cOshqgQvg/U gqt5kQYFm8rzUoZyk4bDZvAmx9gTm8H7a3TevwV5vXK3O2yWNnt6558+6B6jJ1v7jNNM z2bStbfxZrlkgc4FO6ShbydynUOe+aQRvL9PGZK8wEdy+garIBH7boDVRIgWMNcTymvI 70WzecwyxDBf5VrJpT5evICOrWHtgCDK8N6dn6KIXKoiyHWx/PaSwDFT6C507SYxkK6V uK85P96p+XDJn+qEpZqfumV1T1HOldhnrThPPaVe32Y/4EW3/ilstaEYmxfBDGGXqkZn GnEA== X-Gm-Message-State: AOAM530CnCoa29T9UsT/v0mSrxpi1vaundM0Bbht2bSbpfalJ18NIRub QfXGCOuyaZFBPzlIMNcIILE= X-Google-Smtp-Source: ABdhPJxb2SXF9ciMnaHs12z+YBgFKGrTWnGOCo6+3US1a6jJS7uDHVoqaFxdI5yGP+IDlmXKOilTYQ== X-Received: by 2002:a37:b686:0:b0:69e:99ba:4ce2 with SMTP id g128-20020a37b686000000b0069e99ba4ce2mr10728313qkf.721.1650906830113; Mon, 25 Apr 2022 10:13:50 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:49 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/7] arm64: dts: rockchip: add rk356x sfc support Date: Mon, 25 Apr 2022 13:13:41 -0400 Message-Id: <20220425171344.1924057-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the sfc node to the rk356x device tree. This enables spi flash support for this soc. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index ca20d7b91fe5..61a6d9d4c8a0 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,6 +750,17 @@ sdmmc1: mmc@fe2c0000 { status =3D "disabled"; }; =20 + sfc: spi@fe300000 { + compatible =3D "rockchip,sfc"; + reg =3D <0x0 0xfe300000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names =3D "clk_sfc", "hclk_sfc"; + pinctrl-0 =3D <&fspi_pins>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + sdhci: mmc@fe310000 { compatible =3D "rockchip,rk3568-dwcmshc"; reg =3D <0x0 0xfe310000 0x0 0x10000>; --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 384CDC433F5 for ; Mon, 25 Apr 2022 17:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243783AbiDYRRY (ORCPT ); Mon, 25 Apr 2022 13:17:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243769AbiDYRQ5 (ORCPT ); Mon, 25 Apr 2022 13:16:57 -0400 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ECD5183B2; Mon, 25 Apr 2022 10:13:52 -0700 (PDT) Received: by mail-qk1-x736.google.com with SMTP id b189so11245113qkf.11; Mon, 25 Apr 2022 10:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W0ONHOXp1qQGx3VZ4Yf3E6RTaBqhduQyGs/XNLTvGpc=; b=PgLoTl+5teAMU/O0oLpgBdcLONE3BP52caH0FZvIgERXTM1MXxZYfhq3wJGelibms4 70E0FFRF0V1D1G1ZClqfAnEg1RQaWH4TFdwqb0m6Iwc7G+g7QyRsHBZzDz2QZuflaFbT EIh41BVOeCvLOrbd/nAmR0cLBPfE9huJOxaEClPVFeX2vjOdxSdVE8BWyqF0CKmOyzOd K4Z6qNFIKFhH2PD/pmUZMN2LGgTI9CWq+zyCVuCyBHBPo5OD1QJHoIaK3UVFTkR9AZUN FwIMfuGKcJujKRGVNhFFAtjQwhTLgAOAp2sPmtGeOU5Ux3OP8vPXIQSpYOfgDrCCXPke UqgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W0ONHOXp1qQGx3VZ4Yf3E6RTaBqhduQyGs/XNLTvGpc=; b=BZf9FwVO8NYbSVT4juBvJVmQN7MQ6IAfbGoTlqiSjrJ8KB7tBBi9MfSzWluU29v7Ds prD67mD+49eSYyMOr5L1tXsf7tuaaD4pcdih1/kQ2rfYVVHDDLtneLlKbd7EC/j+wca4 WIsqEiqQs2rVmO3ZkJJmvqarQ5/HZYxmhzkRx3DNvASazNGGkEOXBL2/sYFyWgoOOi6s ZpLEoYVPfZkuAOdtIij7PxM/WcVHDl0TFaq7XFV70hbe4FRPb6f4CxDyF+yJ32+8yzrj kNEthtcJw8xXFJBCNgPMCEZLYPh6TxBIrawXKK8tVwZe0LKeFOhgfNZXDKcr2sEMrE53 7JWQ== X-Gm-Message-State: AOAM530YLNnoxco5b4STaGhAArhbvBje0m/3M3xYEl+HD4aj9UpI3BJn 0bDZlKJsBLsqAzFvnc9lEpSHbXLGVLythg== X-Google-Smtp-Source: ABdhPJz05BK7iVd11vG2EA0I2eh/hhUWpkrCY83UPUE4pw1zx8tY8bItEgpo9+PtY7UvZONp/GrOIA== X-Received: by 2002:a37:bd82:0:b0:69e:9da7:f0e4 with SMTP id n124-20020a37bd82000000b0069e9da7f0e4mr11014710qkf.354.1650906831504; Mon, 25 Apr 2022 10:13:51 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:51 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree Date: Mon, 25 Apr 2022 13:13:42 -0400 Message-Id: <20220425171344.1924057-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device tree for the Pine64 Quartz64 Model B single board computer. This board ouputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 x2 (one port otg capable) USB3 PCIe/SATA M2 HDMI DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI Flash PI-40 compatible pin header Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++ 2 files changed, 616 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 4ae9f35434b8..252ee47b8a1d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm6= 4/boot/dts/rockchip/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..184ab7e1d178 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Pine64 RK3566 Quartz64-B Board"; + compatible =3D "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-user { + label =3D "user-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <5000000>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb30_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio =3D <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x4f>; + rx_delay =3D <0x24>; + phy-handle =3D <&rgmii_phy1>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name =3D "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m1_xfer>; + status =3D "okay"; +}; + +/* i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status =3D "okay"; +}; + +/* i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status =3D "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcca1v8_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcca1v8_pmu>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcca1v8_pmu>; + status =3D "okay"; +}; + +&sfc { + pinctrl-0 =3D <&fspi_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <24000000>; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <1>; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status =3D "okay"; + uart-has-rtscts; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +/* uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 443B5C433EF for ; Mon, 25 Apr 2022 17:14:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243822AbiDYRRb (ORCPT ); Mon, 25 Apr 2022 13:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243775AbiDYRQ7 (ORCPT ); Mon, 25 Apr 2022 13:16:59 -0400 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DDCF13DD7; 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Mon, 25 Apr 2022 10:13:53 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id v3-20020a05622a014300b002e1dcd4cfa9sm7154928qtw.64.2022.04.25.10.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 10:13:52 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts Date: Mon, 25 Apr 2022 13:13:43 -0400 Message-Id: <20220425171344.1924057-7-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is the initial SoQuartz SoM device tree on a CM4IO carrier board. This board outputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 (OTG/Host shared) PCIe 2.0 x1 HDMI (HDMI Port 0) eDP (HDMI Port 1) DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI NOR Flash (Not placed) PI-40 compatible pin header Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++ .../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 ++++++++++++++++++ 3 files changed, 775 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 252ee47b8a1d..23a2a0c111ac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,5 +60,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/ar= m64/boot/dts/rockchip/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..fa470a587e2b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model =3D "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible =3D "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk35= 66"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&gmac1 { + status =3D "okay"; +}; + +/* i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "okay"; + + /* the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063"; + reg =3D <0x51>; + }; +}; + +/* i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status =3D "disabled"; +}; + +/* i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status =3D "disabled"; +}; + +/* i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status =3D "disabled"; +}; + +&led_diy { + status =3D "okay"; +}; + +&led_work { + status =3D "okay"; +}; + +&rgmii_phy1 { + status =3D "okay"; +}; + +/* saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status =3D "disabled"; +}; + +&sdmmc0 { + vmmc-supply =3D <&sdmmc_pwr>; + status =3D "okay"; +}; + +&sdmmc_pwr { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + status =3D "okay"; +}; + +/* spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +/* uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status =3D "okay"; +}; + +/* uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc_5v>; + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&vbus { + vin-supply =3D <&vcc_5v>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64= /boot/dts/rockchip/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..9ebb2afe7e82 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Pine64 RK3566 SoQuartz SOM"; + compatible =3D "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 =3D &gmac1; + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led_diy: led-diy { + label =3D "diy-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&diy_led_enable_h>; + retain-state-suspended; + status =3D "disabled"; + }; + + led_work: led-work { + label =3D "work-led"; + default-state =3D "off"; + gpios =3D <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&work_led_enable_h>; + retain-state-suspended; + status =3D "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + sdmmc_pwr: sdmmc-pwr-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc_pwr_h>; + regulator-name =3D "sdmmc_pwr"; + status =3D "disabled"; + }; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-supply =3D <&vcc_3v3>; + phy-mode =3D "rgmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio =3D <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x30>; + rx_delay =3D <0x10>; + phy-handle =3D <&rgmii_phy1>; + status =3D "disabled"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-initial-mode =3D <0x2>; + regulator-name =3D "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + status =3D "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status =3D "disabled"; +}; + +/* i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "disabled"; +}; + +/* i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status =3D "disabled"; +}; + +/* i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4m1_xfer>; + status =3D "disabled"; +}; + +/* i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status =3D "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + status =3D "disabled"; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins =3D <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc-pwr { + sdmmc_pwr_h: sdmmc-pwr-h { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vcc_3v3>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_3v3>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +/* saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "disabled"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "disabled"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +/* spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status =3D "disabled"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +/* uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status =3D "disabled"; +}; + +/* uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart7m2_xfer>; + status =3D "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status =3D "disabled"; +}; + +&usb2phy0_otg { + status =3D "disabled"; +}; + +&usb_host0_xhci { + status =3D "disabled"; +}; --=20 2.25.1 From nobody Mon Jun 15 18:31:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9085DC43217 for ; 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Mon, 25 Apr 2022 10:13:54 -0700 (PDT) From: Peter Geis To: linux-rockchip@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Furkan Kardame , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: [PATCH v1 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566 Date: Mon, 25 Apr 2022 13:13:44 -0400 Message-Id: <20220425171344.1924057-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220425171344.1924057-1-pgwipeout@gmail.com> References: <20220425171344.1924057-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Furkan Kardame Add dts for Firefly Station M2. Working IO: * UART * LED * LAN * Wifi * SD Card * eMMC * USB2 Signed-off-by: Furkan Kardame Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 ++++++++++++++++++ 2 files changed, 581 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 23a2a0c111ac..617915c17ca8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/bo= ot/dts/rockchip/rk3566-roc-pc.dts new file mode 100644 index 000000000000..1ede01b46e1c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model =3D "Firefly Station M2"; + compatible =3D "firefly,rk3566-roc-pc", "rockchip,rk3566"; + + aliases { + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + clock-output-names =3D "gmac1_clkin"; + #clock-cells =3D <0>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-user { + label =3D "user-led"; + default-state =3D "on"; + gpios =3D <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status =3D "okay"; + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + reset-gpios =3D <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + usb_5v: usb-5v-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&usb_5v>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb30_host"; + enable-active-high; + gpio =3D <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb_otg"; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED= >, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC= 1>, <&gmac1_clkin>; + clock_in_out =3D "input"; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio =3D <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us =3D <0 20000 100000>; + tx_delay =3D <0x4f>; + rx_delay =3D <0x24>; + phy-handle =3D <&rgmii_phy1>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + clock-output-names =3D "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells =3D <1>; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name =3D "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-init-microvolt =3D <900000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name =3D "vcc3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m1_xfer>; + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x0>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins =3D <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins =3D + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins =3D <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status =3D "okay"; + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcca1v8_pmu>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_xfer>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn>; + status =3D "okay"; + uart-has-rtscts; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + clocks =3D <&rk809 1>; + clock-names =3D "lpo"; + device-wakeup-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply =3D <&vcc3v3_sys>; + vddio-supply =3D <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb30_host>; + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb_host0_xhci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; --=20 2.25.1