From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C953FC433F5 for ; Sun, 24 Apr 2022 16:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234541AbiDXQ3n (ORCPT ); Sun, 24 Apr 2022 12:29:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233829AbiDXQ3i (ORCPT ); Sun, 24 Apr 2022 12:29:38 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAE6B8566D; Sun, 24 Apr 2022 09:26:37 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 49F305C0112; Sun, 24 Apr 2022 12:26:37 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Sun, 24 Apr 2022 12:26:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817597; x=1650903997; bh=iZ 8UlWzjvuD9578rf5+qyEth9oXMoy4abZ8+2x1E9TI=; b=LU+CgGYWItGih3EZoW 2BA2xbYs6LRQaS2/4drtlMuO47F0oSD1SMjch+h/dsJM+48sV5MdVCE5oRwkq5Ei +3Nm8889pnsNNNEDSkaNIKum7de+aogyuFHzhHCeZTGj+8pcxhfBA5APggj5UNhL aXjcbCnHe18RKvlyn7kAoRAZghl1dmp0tQ6OFT++tbk9ykOFo/RoGj+Ub3RDs6Qf ka10ttlIm3K3UNqG7kekdnsS3Pl/YdcpKKgWOjBUQ2BGvEeaRamFOAAUE3V43tPj K2vJ6ONJCtEp1/Ox7s12yy0oSs9WpF+axg7vJpyjgFJP9z1E05BS129pxDb/bj4M qoGQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817597; x=1650903997; bh=iZ8UlWzjvuD9578rf5+qyEth9oXMoy4abZ8 +2x1E9TI=; b=dKvZ9lq93DVs9J+rT5WMTSvg0j9W1BVyo3dNGkMlLF4uREL2eHO sI1VaTnyT8vXrZEwPpCw+SrezHcptZ4cfGLZ5L7514SxNhZIZG1/LsnhK+aP7Adc AsM000xnf14LgErHp1N3oTKm+3e/Q7YfcAOZSf1kWQSGyNI7RPC6duK7i9WS4XZg F2JR11/DNjY1p+u43ie8RGoF8YeKGFByjtr/XnyN9vaqM3fpW+HzG9OafF7juLVI 84zYgMNkzpa2PUaoWLqqOEXHymO/XTUMg4kJyJyPOY3JsVnzZVkWNG1Gjm0SNj3K PSOmdSF0ggtWRWCocmjSzBcwbDHfUgrm2tg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutdefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:36 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH v3 01/14] dt-bindings: display: Separate clock item lists by compatible Date: Sun, 24 Apr 2022 11:26:19 -0500 Message-Id: <20220424162633.12369-2-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" So far, the binding and driver have relied on the fact that the H6 clocks are both a prefix and a subset of the R40 clocks. This allows them to share the clocks/clock-names items and the clock-output-names order between the hardware variants. However, the D1 hardware has TCON TV0 and DSI, but no TCON TV1. This cannot be supported by the existing scheme because it puts a gap in the middle of the item lists. To prepare for adding D1 support, use separate lists for variants with different combinations of clocks. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Samuel Holland --- Changes in v3: - Drop redundant minItems and maxItems .../display/allwinner,sun8i-r40-tcon-top.yaml | 105 ++++++++++-------- 1 file changed, 61 insertions(+), 44 deletions(-) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-= tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r= 40-tcon-top.yaml index 61ef7b337218..449fa99aa51b 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-to= p.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-to= p.yaml @@ -48,31 +48,15 @@ properties: =20 clocks: minItems: 2 - items: - - description: The TCON TOP interface clock - - description: The TCON TOP TV0 clock - - description: The TCON TOP TVE0 clock - - description: The TCON TOP TV1 clock - - description: The TCON TOP TVE1 clock - - description: The TCON TOP MIPI DSI clock + maxItems: 6 =20 clock-names: minItems: 2 - items: - - const: bus - - const: tcon-tv0 - - const: tve0 - - const: tcon-tv1 - - const: tve1 - - const: dsi + maxItems: 6 =20 clock-output-names: minItems: 1 maxItems: 3 - description: > - The first item is the name of the clock created for the TV0 - channel, the second item is the name of the TCON TV1 channel - clock and the third one is the name of the DSI channel clock. =20 resets: maxItems: 1 @@ -129,32 +113,65 @@ required: =20 additionalProperties: false =20 -if: - properties: - compatible: - contains: - const: allwinner,sun50i-h6-tcon-top - -then: - properties: - clocks: - maxItems: 2 - - clock-output-names: - maxItems: 1 - -else: - properties: - clocks: - minItems: 6 - - clock-output-names: - minItems: 3 - - ports: - required: - - port@2 - - port@3 +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-r40-tcon-top + + then: + properties: + clocks: + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + - description: The TCON TOP TVE0 clock + - description: The TCON TOP TV1 clock + - description: The TCON TOP TVE1 clock + - description: The TCON TOP MIPI DSI clock + + clock-names: + items: + - const: bus + - const: tcon-tv0 + - const: tve0 + - const: tcon-tv1 + - const: tve1 + - const: dsi + + clock-output-names: + items: + - description: TCON TV0 output clock name + - description: TCON TV1 output clock name + - description: DSI output clock name + + ports: + required: + - port@2 + - port@3 + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-tcon-top + + then: + properties: + clocks: + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + + clock-names: + items: + - const: bus + - const: tcon-tv0 + + clock-output-names: + items: + - description: TCON TV0 output clock name =20 examples: - | --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A2FC433F5 for ; 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Sun, 24 Apr 2022 12:26:38 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski Subject: [PATCH v3 02/14] dt-bindings: display: Add D1 display engine compatibles Date: Sun, 24 Apr 2022 11:26:20 -0500 Message-Id: <20220424162633.12369-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner D1 contains a display engine 2.0. It features two mixers, a TCON TOP (with DSI and HDMI), one TCON LCD, and one TCON TV. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Samuel Holland --- Changes in v3: - Drop redundant minItems and maxItems .../allwinner,sun4i-a10-display-engine.yaml | 1 + .../display/allwinner,sun4i-a10-tcon.yaml | 2 ++ .../allwinner,sun8i-a83t-de2-mixer.yaml | 2 ++ .../display/allwinner,sun8i-r40-tcon-top.yaml | 28 +++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-= display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,s= un4i-a10-display-engine.yaml index d4412aea7b73..c388ae5da1e4 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display= -engine.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display= -engine.yaml @@ -62,6 +62,7 @@ properties: - allwinner,sun8i-r40-display-engine - allwinner,sun8i-v3s-display-engine - allwinner,sun9i-a80-display-engine + - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine - allwinner,sun50i-h6-display-engine =20 diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-= tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-t= con.yaml index 3a7d5d731712..4a92a4c7dcd7 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.ya= ml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.ya= ml @@ -33,6 +33,8 @@ properties: - const: allwinner,sun8i-v3s-tcon - const: allwinner,sun9i-a80-tcon-lcd - const: allwinner,sun9i-a80-tcon-tv + - const: allwinner,sun20i-d1-tcon-lcd + - const: allwinner,sun20i-d1-tcon-tv =20 - items: - enum: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t= -de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i= -a83t-de2-mixer.yaml index 4f91eec26de9..cb243bc58ef7 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mi= xer.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mi= xer.yaml @@ -19,6 +19,8 @@ properties: - allwinner,sun8i-r40-de2-mixer-0 - allwinner,sun8i-r40-de2-mixer-1 - allwinner,sun8i-v3s-de2-mixer + - allwinner,sun20i-d1-de2-mixer-0 + - allwinner,sun20i-d1-de2-mixer-1 - allwinner,sun50i-a64-de2-mixer-0 - allwinner,sun50i-a64-de2-mixer-1 - allwinner,sun50i-h6-de3-mixer-0 diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-= tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r= 40-tcon-top.yaml index 449fa99aa51b..845e226d7aff 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-to= p.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-to= p.yaml @@ -41,6 +41,7 @@ properties: compatible: enum: - allwinner,sun8i-r40-tcon-top + - allwinner,sun20i-d1-tcon-top - allwinner,sun50i-h6-tcon-top =20 reg: @@ -151,6 +152,33 @@ allOf: - port@2 - port@3 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-d1-tcon-top + + then: + properties: + clocks: + items: + - description: The TCON TOP interface clock + - description: The TCON TOP TV0 clock + - description: The TCON TOP TVE0 clock + - description: The TCON TOP MIPI DSI clock + + clock-names: + items: + - const: bus + - const: tcon-tv0 + - const: tve0 + - const: dsi + + clock-output-names: + items: + - description: TCON TV0 output clock name + - description: DSI output clock name + - if: properties: compatible: --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E89C433F5 for ; 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Sun, 24 Apr 2022 12:26:40 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 03/14] drm/sun4i: Remove obsolete references to PHYS_OFFSET Date: Sun, 24 Apr 2022 11:26:21 -0500 Message-Id: <20220424162633.12369-4-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" commit b4bdc4fbf8d0 ("soc: sunxi: Deal with the MBUS DMA offsets in a central place") added a platform device notifier that sets the DMA offset for all of the display engine frontend and backend devices. The code applying the offset to DMA buffer physical addresses was then removed from the backend driver in commit 756668ba682e ("drm/sun4i: backend: Remove the MBUS quirks"), but the code subtracting PHYS_OFFSET was left in the frontend driver. As a result, the offset was applied twice in the frontend driver. This likely went unnoticed because it only affects specific configurations (scaling or certain pixel formats) where the frontend is used, on boards with both one of these older SoCs and more than 1 GB of DRAM. In addition, the references to PHYS_OFFSET prevent compiling the driver on architectures where PHYS_OFFSET is not defined. Fixes: b4bdc4fbf8d0 ("soc: sunxi: Deal with the MBUS DMA offsets in a centr= al place") Reviewed-by: Jernej Skrabec Signed-off-by: Samuel Holland --- (no changes since v1) drivers/gpu/drm/sun4i/sun4i_frontend.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c b/drivers/gpu/drm/sun4i= /sun4i_frontend.c index 56ae38389db0..462fae73eae9 100644 --- a/drivers/gpu/drm/sun4i/sun4i_frontend.c +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c @@ -222,13 +222,11 @@ void sun4i_frontend_update_buffer(struct sun4i_fronte= nd *frontend, =20 /* Set the physical address of the buffer in memory */ paddr =3D drm_fb_cma_get_gem_addr(fb, state, 0); - paddr -=3D PHYS_OFFSET; DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr); regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr); =20 if (fb->format->num_planes > 1) { paddr =3D drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1); - paddr -=3D PHYS_OFFSET; DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr); regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG, paddr); @@ -236,7 +234,6 @@ void sun4i_frontend_update_buffer(struct sun4i_frontend= *frontend, =20 if (fb->format->num_planes > 2) { paddr =3D drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2); - paddr -=3D PHYS_OFFSET; DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr); regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG, paddr); --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB257C433F5 for ; Sun, 24 Apr 2022 16:26:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234741AbiDXQ3v (ORCPT ); Sun, 24 Apr 2022 12:29:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234593AbiDXQ3o (ORCPT ); Sun, 24 Apr 2022 12:29:44 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C75518596B; Sun, 24 Apr 2022 09:26:43 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 38A295C010D; Sun, 24 Apr 2022 12:26:43 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 24 Apr 2022 12:26:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817603; x=1650904003; bh=IO 2nJQg7ZpLgbDDCjHzDR4pLdHAIP+lsCx6T8EE6RlY=; b=ZM+7HkG33TFGd4SnTl pPu0uPke8mtVg/q7fHqDEd4Fuerod5HZNJJkvnTmHf+DYpdqtWwX2Su9M6LQBu54 +3NFgTgVCDbmnofc9D7okjWLGEJnLwgHa/Ypj5XTQtVPOais5oZf89pxirbXaIQn cuFJDUXBw6x6q/I6iEcJLUGWXV6IPIqkLKy/4eNdIZ5vnq9n1iG6DfWCbtLfqRhp VAFCTTNlKmLxUxYnTka3Lzj/Qy6fQ8bBoDyEpASMYwZ6c/rhRLmQkf01Gz3b02Ry PpeHNxD5pS3SgjNyTIyzeDwOqwghaP3C18WXFTbNO20IFJs1HH3QBHW1atm5PwLo uMZg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817603; x=1650904003; bh=IO2nJQg7ZpLgbDDCjHzDR4pLdHAIP+lsCx6 T8EE6RlY=; b=L8MCGD/7ZVhcs26x/u62cYKUgqkuivZgDan7O/ye4vQcSXXZMRO ZrGYYFd+a/MA9piLbpJVpWoZuPLzB7AxwH1ql2V8qf1oV02XLom3kOMUTedkmD5U 89blgeCjkG1bXKt43BmYJaulQdRXpQTw1bgKVfTbptkAGN0TQLf39uGRw6pspQh6 MXIsHYBWlBz8Wz+feeC/x3MT4GCfnMqGFTniRsvlam48MVuCdqU0r0DJUgtGdckp GQ/clLFrNWC9obt9nQbhgpIeyXdqkxsrDbos7omOq/jVmUtNtRw9VBchXeB95s2x 2m4YipgN2dBCI1rW9+qKGB74S5+GV3wbDjA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:42 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, kernel test robot Subject: [PATCH v3 04/14] drm/sun4i: hdmi: Use more portable I/O helpers Date: Sun, 24 Apr 2022 11:26:22 -0500 Message-Id: <20220424162633.12369-5-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" readsb/writesb are unavailable on some architectures. In preparation for removing the Kconfig architecture dependency, switch to the equivalent but more portable ioread/write8_rep helpers. Reported-by: kernel test robot Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v2) Changes in v2: - New patch: I/O helper portability drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i= /sun4i_hdmi_i2c.c index b66fa27fe6ea..c7d7e9fff91c 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c @@ -56,9 +56,9 @@ static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf= , int len, bool read) return -EIO; =20 if (read) - readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); + ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); else - writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); + iowrite8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); =20 /* Clear FIFO request bit by forcing a write to that bit */ regmap_field_force_write(hdmi->field_ddc_int_status, --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25F3CC433EF for ; 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Sun, 24 Apr 2022 12:26:44 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 05/14] drm/sun4i: Allow building the driver on RISC-V Date: Sun, 24 Apr 2022 11:26:23 -0500 Message-Id: <20220424162633.12369-6-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allwinner D1 is a RISC-V SoC which contains a DE 2.0 engine. Let's remove the dependency on a specific CPU architecture, so the driver can be built wherever ARCH_SUNXI is selected. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland --- (no changes since v1) drivers/gpu/drm/sun4i/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index befc5a80222d..3a43c436c74a 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_SUN4I tristate "DRM Support for Allwinner A10 Display Engine" - depends on DRM && (ARM || ARM64) && COMMON_CLK + depends on DRM && COMMON_CLK depends on ARCH_SUNXI || COMPILE_TEST select DRM_GEM_CMA_HELPER select DRM_KMS_HELPER --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E605C43219 for ; Sun, 24 Apr 2022 16:27:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234916AbiDXQaF (ORCPT ); Sun, 24 Apr 2022 12:30:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234699AbiDXQ3s (ORCPT ); Sun, 24 Apr 2022 12:29:48 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B1E986E04; Sun, 24 Apr 2022 09:26:47 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 0C8705C00D0; Sun, 24 Apr 2022 12:26:47 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 24 Apr 2022 12:26:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817607; x=1650904007; bh=X3 nfO2+qIHZjcadT9+iWcXRozE5825pqSV9bZL4/rK0=; b=lnLxQOZUs/SwZDs0bf 8NAIL+Am3ykLhS24HooBKFZTk10oUic8LAbPUpFA2ArjLfBiB/Rv+h3B3UOZRWL6 fzBnn6NAtSVHU9kGaCyHlmayzG1fjgbCSzrHBZvhDRRJfC7sEk+SCaxR3YK1WUh7 mp0RKC4OuXQbPgQdB5JyYfQEd56XZa6KpwCx18Od7rsg8fRAi9f4ptxfejh+K3Op cP8lJaxFJrx3uYyIDWHxFAu6wBU24xz9NwFXhjLHnFnbvkkw2N9P3UjNxlkmbI50 psrVZOMKC9SOMCle6W5Wt4qfDZchBIvHkIJet/M2f4W3gZu+y89OZsTLXCInwlsZ nWhw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817607; x=1650904007; bh=X3nfO2+qIHZjcadT9+iWcXRozE5825pqSV9 bZL4/rK0=; b=VfxMzzD6WOqJ64/v+5/0fC3oj6wkmgFbFWttPWa1UUL32B/kCIM OzpLFeSqE+p3z5cOtQ/QIdpPd+EcJTmAd7av8LsffRVR/G47OQwjyp3gIi2IEVgj 7zVSlvbsxxwD0pyNUSnb8W751hNfybvAtDPt5PC6Bgcq6KXfu6zxz6O2RgdyM4rx EEKENuSpP/65ijOTNxGJgdXRgdzCvfGGgd4qDhfaQ+u0MBvMxUE+QLI3b7j0b9vi jEIbxHgQ7vnJzScpUscCDXeoJ/8zg4h4zPX3iOu6SW1QH5B1lT4bl617WLC0NMxS PeMRiv2wbS33tgO7WE2I756OaJ6Bhe67O0w== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutddvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:46 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 06/14] sun4i/drm: engine: Add mode_set callback Date: Sun, 24 Apr 2022 11:26:24 -0500 Message-Id: <20220424162633.12369-7-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jernej Skrabec This optional callback is useful for setting properties which depends only on current mode. Such properties are width, height and interlaced output. These properties are currently set in update layer callback for primary plane which is less than ideal. More about that in follow up patches, which will migrate that code to this newly defined callback. Signed-off-by: Jernej Skrabec Signed-off-by: Samuel Holland --- (no changes since v2) Changes in v2: - Use Jernej's patches for mixer mode setting. drivers/gpu/drm/sun4i/sun4i_crtc.c | 1 + drivers/gpu/drm/sun4i/sunxi_engine.h | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun= 4i_crtc.c index 45d9eb552d86..c06d7cd45388 100644 --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c @@ -146,6 +146,7 @@ static void sun4i_crtc_mode_set_nofb(struct drm_crtc *c= rtc) struct sun4i_crtc *scrtc =3D drm_crtc_to_sun4i_crtc(crtc); =20 sun4i_tcon_mode_set(scrtc->tcon, encoder, mode); + sunxi_engine_mode_set(scrtc->engine, mode); } =20 static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs =3D { diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/s= unxi_engine.h index 548710a936d5..ec8cf9b2bda4 100644 --- a/drivers/gpu/drm/sun4i/sunxi_engine.h +++ b/drivers/gpu/drm/sun4i/sunxi_engine.h @@ -9,6 +9,7 @@ struct drm_plane; struct drm_device; struct drm_crtc_state; +struct drm_display_mode; =20 struct sunxi_engine; =20 @@ -108,6 +109,17 @@ struct sunxi_engine_ops { * This function is optional. */ void (*vblank_quirk)(struct sunxi_engine *engine); + + /** + * @mode_set + * + * This callback is used to set mode related parameters + * like interlacing, screen size, etc. once per mode set. + * + * This function is optional. + */ + void (*mode_set)(struct sunxi_engine *engine, + const struct drm_display_mode *mode); }; =20 /** @@ -181,4 +193,19 @@ sunxi_engine_disable_color_correction(struct sunxi_eng= ine *engine) if (engine->ops && engine->ops->disable_color_correction) engine->ops->disable_color_correction(engine); } + +/** + * sunxi_engine_mode_set - Inform engine of a new mode + * @engine: pointer to the engine + * @mode: new mode + * + * Engine can use this functionality to set specifics once per mode change. + */ +static inline void +sunxi_engine_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) +{ + if (engine->ops && engine->ops->mode_set) + engine->ops->mode_set(engine, mode); +} #endif /* _SUNXI_ENGINE_H_ */ --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E39F5C43217 for ; Sun, 24 Apr 2022 16:27:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234965AbiDXQaJ (ORCPT ); Sun, 24 Apr 2022 12:30:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234593AbiDXQ3w (ORCPT ); Sun, 24 Apr 2022 12:29:52 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82B9E86E1A; Sun, 24 Apr 2022 09:26:49 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E749B5C006B; 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Sun, 24 Apr 2022 12:26:48 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 07/14] sun4i/drm: backend: use mode_set engine callback Date: Sun, 24 Apr 2022 11:26:25 -0500 Message-Id: <20220424162633.12369-8-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jernej Skrabec Newly introduced mode_set callback in engine structure is a much better place for setting backend output size and interlace mode for following reasons: 1. Aforementioned properties change only when mode changes, so it's enough to be set only once per mode set. Currently it's done whenever properties of primary plane are changed. 2. It's assumed that primary plane will always cover whole screen. While this is true most of the time, it's not always. Planes are universal. There is no reason to add artificial limitation to primary plane. Signed-off-by: Jernej Skrabec [Samuel: drop unused 'interlaced' variable] Signed-off-by: Samuel Holland --- (no changes since v2) Changes in v2: - Use Jernej's patches for mixer mode setting. drivers/gpu/drm/sun4i/sun4i_backend.c | 40 +++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/= sun4i_backend.c index f52ff4e6c662..decd95ad519d 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -172,14 +172,6 @@ int sun4i_backend_update_layer_coord(struct sun4i_back= end *backend, =20 DRM_DEBUG_DRIVER("Updating layer %d\n", layer); =20 - if (plane->type =3D=3D DRM_PLANE_TYPE_PRIMARY) { - DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", - state->crtc_w, state->crtc_h); - regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG, - SUN4I_BACKEND_DISSIZE(state->crtc_w, - state->crtc_h)); - } - /* Set height and width */ DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", state->crtc_w, state->crtc_h); @@ -259,7 +251,6 @@ int sun4i_backend_update_layer_formats(struct sun4i_bac= kend *backend, { struct drm_plane_state *state =3D plane->state; struct drm_framebuffer *fb =3D state->fb; - bool interlaced =3D false; u32 val; int ret; =20 @@ -267,17 +258,6 @@ int sun4i_backend_update_layer_formats(struct sun4i_ba= ckend *backend, regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); =20 - if (plane->state->crtc) - interlaced =3D plane->state->crtc->state->adjusted_mode.flags - & DRM_MODE_FLAG_INTERLACE; - - regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, - SUN4I_BACKEND_MODCTL_ITLMOD_EN, - interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); - - DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", - interlaced ? "on" : "off"); - val =3D SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); if (state->alpha !=3D DRM_BLEND_ALPHA_OPAQUE) val |=3D SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; @@ -654,6 +634,25 @@ static void sun4i_backend_vblank_quirk(struct sunxi_en= gine *engine) spin_unlock(&backend->frontend_lock); }; =20 +static void sun4i_backend_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) +{ + bool interlaced =3D !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + + DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", + mode->hdisplay, mode->vdisplay); + + regmap_write(engine->regs, SUN4I_BACKEND_DISSIZE_REG, + SUN4I_BACKEND_DISSIZE(mode->hdisplay, mode->vdisplay)); + + regmap_update_bits(engine->regs, SUN4I_BACKEND_MODCTL_REG, + SUN4I_BACKEND_MODCTL_ITLMOD_EN, + interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); + + DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", + interlaced ? "on" : "off"); +} + static int sun4i_backend_init_sat(struct device *dev) { struct sun4i_backend *backend =3D dev_get_drvdata(dev); int ret; @@ -765,6 +764,7 @@ static const struct sunxi_engine_ops sun4i_backend_engi= ne_ops =3D { .apply_color_correction =3D sun4i_backend_apply_color_correction, .disable_color_correction =3D sun4i_backend_disable_color_correction, .vblank_quirk =3D sun4i_backend_vblank_quirk, + .mode_set =3D sun4i_backend_mode_set, }; =20 static const struct regmap_config sun4i_backend_regmap_config =3D { --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A456C433F5 for ; Sun, 24 Apr 2022 16:27:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235159AbiDXQah (ORCPT ); Sun, 24 Apr 2022 12:30:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234782AbiDXQ3x (ORCPT ); Sun, 24 Apr 2022 12:29:53 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ED0D86E33; Sun, 24 Apr 2022 09:26:51 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id AAD6F5C00D0; Sun, 24 Apr 2022 12:26:50 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Sun, 24 Apr 2022 12:26:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817610; x=1650904010; bh=VA bSZxVzIGNAQAD06Zb2HEHcQCKmbXdF4OwgsGA6Zho=; b=XnuLBhQ1TaMX7ScUVL TnOoKFKEFJM5ss6c76CB9h7/Yo8Ilg9R4YBv6aOz99t3ooiibmuG9wIfzX3DlY3f ejCw8fCRVtkKCbnSpFpVIq995dLxKyXMAZIRxNMV9a47yO3CdIJPwhwrszhqyEb7 h7BnlTgwlLIny5wc/GadgisnR3bR36nnJsd5vcW25EuDZUv17QQgsoen9tyE6BNx 0pqFJRQNUmL5UFJgdzmSbNc0WWwZ2cssg8TTIXEpsgqhvx00M8tFEQMO55BA31Jw cY1pmvPg6sIzXsGxDWaRxmcnAMw/SKiThivZIzUU0SM2vhJw4osMokUdG0Y4U8N2 vveQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817610; x=1650904010; bh=VAbSZxVzIGNAQAD06Zb2HEHcQCKmbXdF4Ow gsGA6Zho=; b=MWHxoS6DPWO/ht0YNT6BOjE8h5LKFrlIRiqGXuH4fYfmkjTaf+U eVlXbqjrupUJTdEXUejtchDuHIqE6DxdL5rlv+ggQcP+0drb/Xhk59bs4ySljy1Z S326/ZuCyafh4Kr1/QAW/ZJtrhospb9fBts7ehq9OX7ud0aSAd9gG6kJ5+fBPZAM o1G00diM4nH6L4IZ6NjaUzCPeCdgM4hK/VOx8xaLh/3enZhSuXyd9xg3XxkLTf8t L7iMfz81MdvBRiwUnAW2JtP20nZWUynpEjIkqHa4bSkaFFoIRnqmA80xN+o75ulf mk8wF+Eb+TQEzDBgM3ZiJnwxjgtR18N/TRQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutdefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:50 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 08/14] sun4i/drm: sun8i: use mode_set engine callback Date: Sun, 24 Apr 2022 11:26:26 -0500 Message-Id: <20220424162633.12369-9-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jernej Skrabec Newly introduced mode_set callback in engine structure is a much better place for setting mixer output size and interlace mode for the following reasons: 1. Aforementioned properties change only when mode changes, so it's enough to be set only once per mode set. Currently it's done whenever properties of primary plane are changed. 2. It's assumed that primary plane will always cover whole screen. While this is true most of the time, it's not always. DE2/3 planes are universal and mostly equal in functionality. There is no reason to add artificial limitation to primary planes. 3. The current code only works for UI layers, but some mixers do not have any UI layers. Signed-off-by: Jernej Skrabec [Samuel: update commit message] Signed-off-by: Samuel Holland --- (no changes since v2) Changes in v2: - Use Jernej's patches for mixer mode setting. drivers/gpu/drm/sun4i/sun8i_mixer.c | 30 ++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 30 -------------------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index f5e8aeaa3cdf..6b1711a9a71f 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -298,9 +298,39 @@ static struct drm_plane **sun8i_layers_init(struct drm= _device *drm, return planes; } =20 +static void sun8i_mixer_mode_set(struct sunxi_engine *engine, + const struct drm_display_mode *mode) +{ + struct sun8i_mixer *mixer =3D engine_to_sun8i_mixer(engine); + u32 bld_base, size, val; + bool interlaced; + + bld_base =3D sun8i_blender_base(mixer); + interlaced =3D !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + size =3D SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); + + DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", + mode->hdisplay, mode->vdisplay); + + regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size); + regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + + if (interlaced) + val =3D SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; + else + val =3D 0; + + regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), + SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); + + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", + interlaced ? "on" : "off"); +} + static const struct sunxi_engine_ops sun8i_engine_ops =3D { .commit =3D sun8i_mixer_commit, .layers_init =3D sun8i_layers_init, + .mode_set =3D sun8i_mixer_mode_set, }; =20 static const struct regmap_config sun8i_mixer_regmap_config =3D { diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i= /sun8i_ui_layer.c index 7845c2a53a7f..4632dea2dc1e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -120,36 +120,6 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mi= xer *mixer, int channel, insize =3D SUN8I_MIXER_SIZE(src_w, src_h); outsize =3D SUN8I_MIXER_SIZE(dst_w, dst_h); =20 - if (plane->type =3D=3D DRM_PLANE_TYPE_PRIMARY) { - bool interlaced =3D false; - u32 val; - - DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", - dst_w, dst_h); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_GLOBAL_SIZE, - outsize); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize); - - if (state->crtc) - interlaced =3D state->crtc->state->adjusted_mode.flags - & DRM_MODE_FLAG_INTERLACE; - - if (interlaced) - val =3D SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; - else - val =3D 0; - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTCTL(bld_base), - SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, - val); - - DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", - interlaced ? "on" : "off"); - } - /* Set height and width */ DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", state->src.x1 >> 16, state->src.y1 >> 16); --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3241CC433EF for ; Sun, 24 Apr 2022 16:27:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230413AbiDXQac (ORCPT ); Sun, 24 Apr 2022 12:30:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234844AbiDXQ37 (ORCPT ); Sun, 24 Apr 2022 12:29:59 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32D1A85968; Sun, 24 Apr 2022 09:26:53 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 8D56C5C006B; Sun, 24 Apr 2022 12:26:52 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Sun, 24 Apr 2022 12:26:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817612; x=1650904012; bh=g8 9iiFras6Fywfob3dR/6hth32NBYwFj8sDvkhiHsjA=; b=RGjja/ali5jtreS3KA pWDXSOeLUHxxsXebUNIxWfhSgm6/P+l2WvTJjYlJSht+0+V1fAFRn1FHlM6rFagj 1t5NRSh/OHVCG/Sq1b1g7KNtgWSIwGa8o9DHtzYHNKll7qkZbW99T3YEQ5hzCVMt jahA34fZ+4dqOOQJjjjgiZWaFBO66DIwoPtnEDHKL4FAsadpSID+c/numkaxi6no rTga8LIT6dqcZeTgmhCjZ/J1D0mFcmAN/pnJJu3MJiHwn9/GfiMpdm39tuQb3vms n9wZJ17S4Ycl1YzfhRNA0rF09rH26gzpfFeNXLllq6WouJSnFqwsaaIaKMQhLdc6 lssw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817612; x=1650904012; bh=g89iiFras6Fywfob3dR/6hth32NBYwFj8sD vkhiHsjA=; b=QdVvXijDkgZgFVCX30CUPBUFQyEROnl0GnMqR5YbijQublorVuR 72zOmwqlIXfHp4Nx1cRMDnIu92UMWQB1lT4SGaKhNQMu/T/qu1qds3ukRxRPWfKt RUDM90iVup/8hzJv1j6cYKExHQSnqs0AgL4yiJr7gZYbmvUSGhrRAJ+qxCo9Vffp WJaaaumL6kS1bTDwhR7y2ZgyY5TQ8+FEKZ6stzxGThMLXsJQyO8UzHyllwyoSr0m hwhWUM/Ryx7pGhCUzQd8x5vgDxCyqgkOY1KtAa2hyJM3k0i8vn8+MxTjhuvR0qRy lBRA3I+obRICKhgY7dowc3J2Qq3W3A8EPfw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutdefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:51 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 09/14] drm/sun4i: Allow VI layers to be primary planes Date: Sun, 24 Apr 2022 11:26:27 -0500 Message-Id: <20220424162633.12369-10-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1's mixer 1 has no UI layers, only a single VI layer. That means the mixer can only be used if the primary plane comes from this VI layer. Add the code to handle this case. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v2) Changes in v2: - Use Jernej's patches for mixer mode setting. drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i= /sun8i_vi_layer.c index bb7c43036dfa..f7d0b082d634 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -542,6 +542,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct d= rm_device *drm, struct sun8i_mixer *mixer, int index) { + enum drm_plane_type type =3D DRM_PLANE_TYPE_OVERLAY; u32 supported_encodings, supported_ranges; unsigned int plane_cnt, format_count; struct sun8i_vi_layer *layer; @@ -560,12 +561,15 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct= drm_device *drm, format_count =3D ARRAY_SIZE(sun8i_vi_layer_formats); } =20 + if (!mixer->cfg->ui_num && index =3D=3D 0) + type =3D DRM_PLANE_TYPE_PRIMARY; + /* possible crtcs are set later */ ret =3D drm_universal_plane_init(drm, &layer->plane, 0, &sun8i_vi_layer_funcs, formats, format_count, sun8i_layer_modifiers, - DRM_PLANE_TYPE_OVERLAY, NULL); + type, NULL); if (ret) { dev_err(drm->dev, "Couldn't initialize layer\n"); return ERR_PTR(ret); --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A083C433F5 for ; Sun, 24 Apr 2022 16:27:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234593AbiDXQaZ (ORCPT ); Sun, 24 Apr 2022 12:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234862AbiDXQaA (ORCPT ); Sun, 24 Apr 2022 12:30:00 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B12D86E3B; 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Sun, 24 Apr 2022 12:26:53 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 10/14] drm/sun4i: csc: Add support for the new MMIO layout Date: Sun, 24 Apr 2022 11:26:28 -0500 Message-Id: <20220424162633.12369-11-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 changes the MMIO offsets for the CSC blocks in the first mixer. The mixers' ccsc property is used as an index into the ccsc_base array. Use an enumeration to describe this index, and add the new set of offsets. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v2) Changes in v2: - Use an enumeration for the ccsc value. drivers/gpu/drm/sun4i/sun8i_csc.c | 7 ++++--- drivers/gpu/drm/sun4i/sun8i_csc.h | 1 + drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 +++++++++--------- drivers/gpu/drm/sun4i/sun8i_mixer.h | 14 ++++++++++---- 4 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8= i_csc.c index 9bd62de0c288..58480d8e4f70 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -8,9 +8,10 @@ #include "sun8i_csc.h" #include "sun8i_mixer.h" =20 -static const u32 ccsc_base[2][2] =3D { - {CCSC00_OFFSET, CCSC01_OFFSET}, - {CCSC10_OFFSET, CCSC11_OFFSET}, +static const u32 ccsc_base[][2] =3D { + [CCSC_MIXER0_LAYOUT] =3D {CCSC00_OFFSET, CCSC01_OFFSET}, + [CCSC_MIXER1_LAYOUT] =3D {CCSC10_OFFSET, CCSC11_OFFSET}, + [CCSC_D1_MIXER0_LAYOUT] =3D {CCSC00_OFFSET, CCSC01_D1_OFFSET}, }; =20 /* diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8= i_csc.h index 022cafa6c06c..828b86fd0cab 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.h +++ b/drivers/gpu/drm/sun4i/sun8i_csc.h @@ -13,6 +13,7 @@ struct sun8i_mixer; /* VI channel CSC units offsets */ #define CCSC00_OFFSET 0xAA050 #define CCSC01_OFFSET 0xFA050 +#define CCSC01_D1_OFFSET 0xFA000 #define CCSC10_OFFSET 0xA0000 #define CCSC11_OFFSET 0xF0000 =20 diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index 6b1711a9a71f..4ce593c99807 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -564,7 +564,7 @@ static int sun8i_mixer_remove(struct platform_device *p= dev) } =20 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg =3D { - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .scaler_mask =3D 0xf, .scanline_yuv =3D 2048, .ui_num =3D 3, @@ -572,7 +572,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg =3D { - .ccsc =3D 1, + .ccsc =3D CCSC_MIXER1_LAYOUT, .scaler_mask =3D 0x3, .scanline_yuv =3D 2048, .ui_num =3D 1, @@ -580,7 +580,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg =3D { - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .mod_rate =3D 432000000, .scaler_mask =3D 0xf, .scanline_yuv =3D 2048, @@ -589,7 +589,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg= =3D { }; =20 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg =3D { - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .mod_rate =3D 297000000, .scaler_mask =3D 0xf, .scanline_yuv =3D 2048, @@ -598,7 +598,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cf= g =3D { }; =20 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg =3D { - .ccsc =3D 1, + .ccsc =3D CCSC_MIXER1_LAYOUT, .mod_rate =3D 297000000, .scaler_mask =3D 0x3, .scanline_yuv =3D 2048, @@ -611,12 +611,12 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_c= fg =3D { .ui_num =3D 1, .scaler_mask =3D 0x3, .scanline_yuv =3D 2048, - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .mod_rate =3D 150000000, }; =20 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg =3D { - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .mod_rate =3D 297000000, .scaler_mask =3D 0xf, .scanline_yuv =3D 4096, @@ -625,7 +625,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg =3D { - .ccsc =3D 1, + .ccsc =3D CCSC_MIXER1_LAYOUT, .mod_rate =3D 297000000, .scaler_mask =3D 0x3, .scanline_yuv =3D 2048, @@ -634,7 +634,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_c= fg =3D { }; =20 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg =3D { - .ccsc =3D 0, + .ccsc =3D CCSC_MIXER0_LAYOUT, .is_de3 =3D true, .mod_rate =3D 600000000, .scaler_mask =3D 0xf, diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/su= n8i_mixer.h index 5b3fbee18671..85c94884fb9a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -141,6 +141,15 @@ #define SUN50I_MIXER_CDC0_EN 0xd0000 #define SUN50I_MIXER_CDC1_EN 0xd8000 =20 +enum { + /* First mixer or second mixer with VEP support. */ + CCSC_MIXER0_LAYOUT, + /* Second mixer without VEP support. */ + CCSC_MIXER1_LAYOUT, + /* First mixer with the MMIO layout found in the D1 SoC. */ + CCSC_D1_MIXER0_LAYOUT, +}; + /** * struct sun8i_mixer_cfg - mixer HW configuration * @vi_num: number of VI channels @@ -149,10 +158,7 @@ * First, scaler supports for VI channels is defined and after that, scaler * support for UI channels. For example, if mixer has 2 VI channels without * scaler and 2 UI channels with scaler, bitmask would be 0xC. - * @ccsc: select set of CCSC base addresses - * Set value to 0 if this is first mixer or second mixer with VEP support. - * Set value to 1 if this is second mixer without VEP support. Other values - * are invalid. + * @ccsc: select set of CCSC base addresses from the enumeration above. * @mod_rate: module clock rate that needs to be set in order to have * a functional block. * @is_de3: true, if this is next gen display engine 3.0, false otherwise. --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E446EC433EF for ; Sun, 24 Apr 2022 16:27:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235006AbiDXQaP (ORCPT ); Sun, 24 Apr 2022 12:30:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234868AbiDXQaA (ORCPT ); Sun, 24 Apr 2022 12:30:00 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24F1288785; Sun, 24 Apr 2022 09:26:56 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id 58E755C006B; Sun, 24 Apr 2022 12:26:56 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Sun, 24 Apr 2022 12:26:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1650817616; x=1650904016; bh=Qk iqJQsRMBNjDm556z2E8TzPBn5kwgUgalPVUN5j18M=; b=Q/c5IPmxsggKWmRxpq +C+jTeClr+XKPnylCa22/GBMsnOYOtyPreGQdSBqQgVBXEeXAyXCadGdddFXzNBc ld1cAyWBkd7ls04A/kWdMKiz/TdraQN96zBfVl3cbNvN4pjZ1kFRTiiY9mt63A0v uYnrblMrEc8hdbC8nfTPy2ciTulsiRn7ygK6mJ+/7sf7Ye+e2r44bAwG1zaVemyF VvqLlv8PA3k4bLjMSZ7VedxAvIP7yjGeqkTzIRWe4GKKdcFxwuGjOS/imn4r3Gks WUW/m7tcll42Lu/3JImRgZyjy5SkHYbbExeAUGL/9+j6BT4sFpzFb31GoqwpYFCk z7yw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650817616; x=1650904016; bh=QkiqJQsRMBNjDm556z2E8TzPBn5kwgUgalP VUN5j18M=; b=L6qCzV1y0/apGCUEP0lR+3CD/yl0nVhR+xFgGuvMyHGuUFeoBmS kLUFZUEYYa1NIcbshTL/dbDRgPERDNLT5npUkedKOzeofZrIj+2ws6JQVDx6xMvR RS/47Y83XFwiGHWBxsAhdAWQ8ktRmgzvvL1XLGWPdmblLZ1Ez0sfoblIQ+cPmBy2 60CEdax7UzyMs+mbljFnVzqUTAoMIROqN752nBI+vIHLUiLEL85v3i4aauXuS2Cx RxqVNixVCL8XHLANkbcjeLZEs6VS6UmXO2o730ktS6x2LOfDDwVg99s6hK1A3iHz n0lA4jVVNMRRS760ZwAaNX70b79WJQaekOw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrtdelgddutdefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 12:26:55 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 11/14] drm/sun4i: Add support for D1 mixers Date: Sun, 24 Apr 2022 11:26:29 -0500 Message-Id: <20220424162633.12369-12-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 has a display engine with the usual pair of mixers, albeit with relatively few layers. In fact, D1 appears to be the first SoC to have a mixer without any UI layers. Add support for these new variants. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland --- (no changes since v1) drivers/gpu/drm/sun4i/sun8i_mixer.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/su= n8i_mixer.c index 4ce593c99807..875a1156c04e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -615,6 +615,24 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cf= g =3D { .mod_rate =3D 150000000, }; =20 +static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg =3D { + .ccsc =3D CCSC_D1_MIXER0_LAYOUT, + .mod_rate =3D 297000000, + .scaler_mask =3D 0x3, + .scanline_yuv =3D 2048, + .ui_num =3D 1, + .vi_num =3D 1, +}; + +static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg =3D { + .ccsc =3D CCSC_MIXER1_LAYOUT, + .mod_rate =3D 297000000, + .scaler_mask =3D 0x1, + .scanline_yuv =3D 1024, + .ui_num =3D 0, + .vi_num =3D 1, +}; + static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg =3D { .ccsc =3D CCSC_MIXER0_LAYOUT, .mod_rate =3D 297000000, @@ -668,6 +686,14 @@ static const struct of_device_id sun8i_mixer_of_table[= ] =3D { .compatible =3D "allwinner,sun8i-v3s-de2-mixer", .data =3D &sun8i_v3s_mixer_cfg, }, + { + .compatible =3D "allwinner,sun20i-d1-de2-mixer-0", + .data =3D &sun20i_d1_mixer0_cfg, + }, + { + .compatible =3D "allwinner,sun20i-d1-de2-mixer-1", + .data =3D &sun20i_d1_mixer1_cfg, + }, { .compatible =3D "allwinner,sun50i-a64-de2-mixer-0", .data =3D &sun50i_a64_mixer0_cfg, --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEC8CC433EF for ; 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Sun, 24 Apr 2022 12:26:57 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 12/14] drm/sun4i: Add support for D1 TCON TOP Date: Sun, 24 Apr 2022 11:26:30 -0500 Message-Id: <20220424162633.12369-13-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 has a TCON TOP with TCON TV0 and DSI, but no TCON TV1. This puts the DSI clock name at index 1 in clock-output-names. Support this by only incrementing the index for clocks that are actually supported. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v1) drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i= /sun8i_tcon_top.c index 1b9b8b48f4a7..da97682b6835 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -189,22 +189,23 @@ static int sun8i_tcon_top_bind(struct device *dev, st= ruct device *master, * if TVE is active on each TCON TV. If it is, mux should be switched * to TVE clock parent. */ + i =3D 0; clk_data->hws[CLK_TCON_TOP_TV0] =3D sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV0_GATE, 0); + TCON_TOP_TCON_TV0_GATE, i++); =20 if (quirks->has_tcon_tv1) clk_data->hws[CLK_TCON_TOP_TV1] =3D sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV1_GATE, 1); + TCON_TOP_TCON_TV1_GATE, i++); =20 if (quirks->has_dsi) clk_data->hws[CLK_TCON_TOP_DSI] =3D sun8i_tcon_top_register_gate(dev, "dsi", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_DSI_GATE, 2); + TCON_TOP_TCON_DSI_GATE, i++); =20 for (i =3D 0; i < CLK_NUM; i++) if (IS_ERR(clk_data->hws[i])) { @@ -272,6 +273,10 @@ static const struct sun8i_tcon_top_quirks sun8i_r40_tc= on_top_quirks =3D { .has_dsi =3D true, }; =20 +static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks =3D { + .has_dsi =3D true, +}; + static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks =3D { /* Nothing special */ }; @@ -282,6 +287,10 @@ const struct of_device_id sun8i_tcon_top_of_table[] = =3D { .compatible =3D "allwinner,sun8i-r40-tcon-top", .data =3D &sun8i_r40_tcon_top_quirks }, + { + .compatible =3D "allwinner,sun20i-d1-tcon-top", + .data =3D &sun20i_d1_tcon_top_quirks + }, { .compatible =3D "allwinner,sun50i-h6-tcon-top", .data =3D &sun50i_h6_tcon_top_quirks --=20 2.35.1 From nobody Sun May 10 20:33:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B05C433F5 for ; Sun, 24 Apr 2022 16:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234943AbiDXQaS (ORCPT ); Sun, 24 Apr 2022 12:30:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234882AbiDXQaB (ORCPT ); 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Sun, 24 Apr 2022 12:26:59 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 13/14] drm/sun4i: Add support for D1 TCONs Date: Sun, 24 Apr 2022 11:26:31 -0500 Message-Id: <20220424162633.12369-14-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" D1 has a TCON TOP, so its quirks are similar to those for the R40 TCONs. While there are some register changes, the part of the TCON TV supported by the driver matches the R40 quirks, so that quirks structure can be reused. D1 has the first supported TCON LCD with a TCON TOP, so the TCON LCD needs a new quirks structure. D1's TCON LCD hardware supports LVDS; in fact it provides dual-link LVDS from a single TCON. However, it comes with a brand new LVDS PHY. Since this PHY has not been tested, leave out LVDS driver support for now. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v1) drivers/gpu/drm/sun4i/sun4i_tcon.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index 88db2d2a9336..2ee158aaeb9e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -1542,6 +1542,12 @@ static const struct sun4i_tcon_quirks sun9i_a80_tcon= _tv_quirks =3D { .needs_edp_reset =3D true, }; =20 +static const struct sun4i_tcon_quirks sun20i_d1_lcd_quirks =3D { + .has_channel_0 =3D true, + .dclk_min_div =3D 1, + .set_mux =3D sun8i_r40_tcon_tv_set_mux, +}; + /* sun4i_drv uses this list to check if a device node is a TCON */ const struct of_device_id sun4i_tcon_of_table[] =3D { { .compatible =3D "allwinner,sun4i-a10-tcon", .data =3D &sun4i_a10_quirks= }, @@ -1559,6 +1565,8 @@ const struct of_device_id sun4i_tcon_of_table[] =3D { { .compatible =3D "allwinner,sun8i-v3s-tcon", .data =3D &sun8i_v3s_quirks= }, { .compatible =3D "allwinner,sun9i-a80-tcon-lcd", .data =3D &sun9i_a80_tc= on_lcd_quirks }, { .compatible =3D "allwinner,sun9i-a80-tcon-tv", .data =3D &sun9i_a80_tco= n_tv_quirks }, + { .compatible =3D "allwinner,sun20i-d1-tcon-lcd", .data =3D &sun20i_d1_lc= d_quirks }, + { .compatible =3D "allwinner,sun20i-d1-tcon-tv", .data =3D &sun8i_r40_tv_= quirks }, { } }; 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Sun, 24 Apr 2022 12:27:01 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard Cc: Samuel Holland , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v3 14/14] drm/sun4i: Add compatible for D1 display engine Date: Sun, 24 Apr 2022 11:26:32 -0500 Message-Id: <20220424162633.12369-15-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424162633.12369-1-samuel@sholland.org> References: <20220424162633.12369-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that the various blocks in the D1 display engine pipeline are supported, we can enable the overall engine. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland --- (no changes since v1) drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4= i_drv.c index 6a9ba8a77c77..275f7e4a03ae 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -418,6 +418,7 @@ static const struct of_device_id sun4i_drv_of_table[] = =3D { { .compatible =3D "allwinner,sun8i-r40-display-engine" }, { .compatible =3D "allwinner,sun8i-v3s-display-engine" }, { .compatible =3D "allwinner,sun9i-a80-display-engine" }, + { .compatible =3D "allwinner,sun20i-d1-display-engine" }, { .compatible =3D "allwinner,sun50i-a64-display-engine" }, { .compatible =3D "allwinner,sun50i-h6-display-engine" }, { } --=20 2.35.1