From nobody Sun Sep 22 04:41:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2CCAC433EF for ; Sun, 24 Apr 2022 08:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238744AbiDXIxa (ORCPT ); Sun, 24 Apr 2022 04:53:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237601AbiDXIx2 (ORCPT ); Sun, 24 Apr 2022 04:53:28 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1842C1CFD6; Sun, 24 Apr 2022 01:50:28 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id w16so2894369ejb.13; Sun, 24 Apr 2022 01:50:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9hGLWJes4t+4tQMjv3m5RoPb2lvXCIf1ih3dR2aQ4Qc=; b=anaLUvD7MuN2zlKzDM7sN/GC+fVdQNLICiJb/sPF1fU8HlUvcyUizTZbHybv+PT4KK tO+dpwAc45opffGIyePpf3pm7WtM2xvqQ2IVVk+9MiS+DM3APDdmhuOjW9HTvfCTK8WR INcFWxBxztZHMSBcAysEUfq4kcgduFwx4yWcvSWCjD+AzeaO+7/wjwiO6/4LwZPEdjLO 9p1QrVYJ4s96hA8dov3IkIqWp5yU7rfXNE0ln8rGC7pr/ObS2GaQp6/uCUmQMq9LrUcw ilYAvsQ3LPxy18gTQnGbs7UCK/SaRwzpBvEoSd6RdZdqDM7OGZkDkru6YYUxjUC185on vKfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9hGLWJes4t+4tQMjv3m5RoPb2lvXCIf1ih3dR2aQ4Qc=; b=3xAPqaWQE3WkBOHQOPxbCV/lguifGb9YUUMwZSo/mwln5H9OJDR2jvOv8uFYDobmf9 iYQ+ebjjrrb/PJDfsg5Gc+ydJXuoREKoDbNxysCnJitWpi038ialJcoxNZdATX3JYJuC O4MMILK9FUBruvcQm9vXJVl8iuv+SQudibpg/3KbeAdi4WevdMSfoWrloo5yRTBpoGPB EuwzTQVZ8TmWfrdZGhMzfH8V4/9ieWWupMte/4YwS/zjzxzzMU1JCUBOiMbtXXvlyjAL QaIv0xsxpKLhdoDUcZdkBwCkaPbtXFvTwJfqswTuDQrN75fXJFZyNTaaTs7bNzO210Sp eFyw== X-Gm-Message-State: AOAM5300LQPDGK937CfuQQJHVlV/IrEuHS2NckM7dT7cMlXuOQMaP4QQ XRy+TBsC8Eo5U25HBBPWMKA= X-Google-Smtp-Source: ABdhPJwBtC5p5qrhVd/u7qXx7lSPfmACDBIYD3HWFPMHT5rAadi8AQ5JK+DpO9egTuehUQK3iKG09g== X-Received: by 2002:a17:907:7f8f:b0:6f0:e67:e3a7 with SMTP id qk15-20020a1709077f8f00b006f00e67e3a7mr11700601ejc.517.1650790226555; Sun, 24 Apr 2022 01:50:26 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.245]) by smtp.gmail.com with ESMTPSA id gy10-20020a170906f24a00b006e894144707sm2435971ejb.53.2022.04.24.01.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 01:50:26 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Sam Shih , Ryder Lee , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yassine Oudjana , Yassine Oudjana Subject: [PATCH v2 1/3] dt-bindings: arm: mediatek: topckgen: Convert to DT schema Date: Sun, 24 Apr 2022 12:46:45 +0400 Message-Id: <20220424084647.76577-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220424084647.76577-1-y.oudjana@protonmail.com> References: <20220424084647.76577-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert topckgen bindings to DT schema format. MT2701, MT7623 and MT7629 device trees currently have the syscon compatible without it being mentioned in the old DT bindings file which introduces dtbs_check errors when converting to DT schema as-is, so mediatek,mt2701-topckgen and mediatek,mt7629-topckgen are placed in the last items list with the syscon compatible, and syscon is added to the mediatek,mt7623-topckgen list. Signed-off-by: Yassine Oudjana Reviewed-by: Krzysztof Kozlowski --- .../arm/mediatek/mediatek,topckgen.txt | 35 ----------- .../bindings/clock/mediatek,topckgen.yaml | 61 +++++++++++++++++++ 2 files changed, 61 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,topckgen.txt create mode 100644 Documentation/devicetree/bindings/clock/mediatek,topckg= en.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckg= en.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.t= xt deleted file mode 100644 index b82422bb717f..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek topckgen controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -The Mediatek topckgen controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-topckgen" - - "mediatek,mt2712-topckgen", "syscon" - - "mediatek,mt6765-topckgen", "syscon" - - "mediatek,mt6779-topckgen", "syscon" - - "mediatek,mt6797-topckgen" - - "mediatek,mt7622-topckgen" - - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - - "mediatek,mt7629-topckgen" - - "mediatek,mt7986-topckgen", "syscon" - - "mediatek,mt8135-topckgen" - - "mediatek,mt8167-topckgen", "syscon" - - "mediatek,mt8173-topckgen" - - "mediatek,mt8183-topckgen", "syscon" - - "mediatek,mt8516-topckgen" -- #clock-cells: Must be 1 - -The topckgen controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -topckgen: power-controller@10000000 { - compatible =3D "mediatek,mt8173-topckgen"; - reg =3D <0 0x10000000 0 0x1000>; - #clock-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml= b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml new file mode 100644 index 000000000000..5b8b37a2e594 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Top Clock Generator Controller + +maintainers: + - Michael Turquette + - Stephen Boyd + +description: + The Mediatek topckgen controller provides various clocks to the system. + The clock values can be found in . + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt6797-topckgen + - mediatek,mt7622-topckgen + - mediatek,mt8135-topckgen + - mediatek,mt8173-topckgen + - mediatek,mt8516-topckgen + - items: + - const: mediatek,mt7623-topckgen + - const: mediatek,mt2701-topckgen + - const: syscon + - items: + - enum: + - mediatek,mt2701-topckgen + - mediatek,mt2712-topckgen + - mediatek,mt6765-topckgen + - mediatek,mt6779-topckgen + - mediatek,mt7629-topckgen + - mediatek,mt7986-topckgen + - mediatek,mt8167-topckgen + - mediatek,mt8183-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + topckgen: clock-controller@10000000 { + compatible =3D "mediatek,mt8173-topckgen"; + reg =3D <0x10000000 0x1000>; + #clock-cells =3D <1>; + }; --=20 2.36.0 From nobody Sun Sep 22 04:41:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50049C433EF for ; Sun, 24 Apr 2022 08:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238764AbiDXIxo (ORCPT ); Sun, 24 Apr 2022 04:53:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238753AbiDXIxj (ORCPT ); Sun, 24 Apr 2022 04:53:39 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5B7A1EAF4; Sun, 24 Apr 2022 01:50:37 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id y21so8276565edo.2; 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Sun, 24 Apr 2022 01:50:36 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.245]) by smtp.gmail.com with ESMTPSA id gy10-20020a170906f24a00b006e894144707sm2435971ejb.53.2022.04.24.01.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 01:50:36 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Sam Shih , Ryder Lee , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yassine Oudjana , Yassine Oudjana Subject: [PATCH v2 2/3] dt-bindings: arm: mediatek: apmixedsys: Convert to DT schema Date: Sun, 24 Apr 2022 12:46:46 +0400 Message-Id: <20220424084647.76577-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220424084647.76577-1-y.oudjana@protonmail.com> References: <20220424084647.76577-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert apmixedsys bindings to DT schema format. MT2701, MT7623 and MT7629 device trees currently have the syscon compatible without it being mentioned in the old DT bindings file which introduces dtbs_check errors when converting to DT schema as-is, so mediatek,mt2701-apmixedsys and mediatek,mt7629-apmixedsys are placed in the last items list with the syscon compatible, and syscon is added to the mediatek,mt7623-apmixedsys list. Signed-off-by: Yassine Oudjana Reviewed-by: Krzysztof Kozlowski --- .../arm/mediatek/mediatek,apmixedsys.txt | 35 ----------- .../bindings/clock/mediatek,apmixedsys.yaml | 61 +++++++++++++++++++ 2 files changed, 61 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,apmixedsys.txt create mode 100644 Documentation/devicetree/bindings/clock/mediatek,apmixe= dsys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixe= dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixeds= ys.txt deleted file mode 100644 index 3fa755866528..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek apmixedsys controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D - -The Mediatek apmixedsys controller provides the PLLs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-apmixedsys" - - "mediatek,mt2712-apmixedsys", "syscon" - - "mediatek,mt6765-apmixedsys", "syscon" - - "mediatek,mt6779-apmixedsys", "syscon" - - "mediatek,mt6797-apmixedsys" - - "mediatek,mt7622-apmixedsys" - - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - - "mediatek,mt7629-apmixedsys" - - "mediatek,mt7986-apmixedsys" - - "mediatek,mt8135-apmixedsys" - - "mediatek,mt8167-apmixedsys", "syscon" - - "mediatek,mt8173-apmixedsys" - - "mediatek,mt8183-apmixedsys", "syscon" - - "mediatek,mt8516-apmixedsys" -- #clock-cells: Must be 1 - -The apmixedsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -apmixedsys: clock-controller@10209000 { - compatible =3D "mediatek,mt8173-apmixedsys"; - reg =3D <0 0x10209000 0 0x1000>; - #clock-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.ya= ml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml new file mode 100644 index 000000000000..770546195fb5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek AP Mixedsys Controller + +maintainers: + - Michael Turquette + - Stephen Boyd + +description: + The Mediatek apmixedsys controller provides PLLs to the system. + The clock values can be found in . + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt6797-apmixedsys + - mediatek,mt7622-apmixedsys + - mediatek,mt7986-apmixedsys + - mediatek,mt8135-apmixedsys + - mediatek,mt8173-apmixedsys + - mediatek,mt8516-apmixedsys + - items: + - const: mediatek,mt7623-apmixedsys + - const: mediatek,mt2701-apmixedsys + - const: syscon + - items: + - enum: + - mediatek,mt2701-apmixedsys + - mediatek,mt2712-apmixedsys + - mediatek,mt6765-apmixedsys + - mediatek,mt6779-apmixedsys + - mediatek,mt7629-apmixedsys + - mediatek,mt8167-apmixedsys + - mediatek,mt8183-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apmixedsys: clock-controller@10209000 { + compatible =3D "mediatek,mt8173-apmixedsys"; + reg =3D <0x10209000 0x1000>; + #clock-cells =3D <1>; + }; --=20 2.36.0 From nobody Sun Sep 22 04:41:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA82C433F5 for ; Sun, 24 Apr 2022 08:51:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233945AbiDXIyC (ORCPT ); Sun, 24 Apr 2022 04:54:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238767AbiDXIxq (ORCPT ); Sun, 24 Apr 2022 04:53:46 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EAFA1EAF4; Sun, 24 Apr 2022 01:50:46 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id r13so24163567ejd.5; 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Sun, 24 Apr 2022 01:50:44 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.245]) by smtp.gmail.com with ESMTPSA id gy10-20020a170906f24a00b006e894144707sm2435971ejb.53.2022.04.24.01.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 01:50:44 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Sam Shih , Ryder Lee , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yassine Oudjana , Yassine Oudjana Subject: [PATCH v2 3/3] dt-bindings: arm: mediatek: infracfg: Convert to DT schema Date: Sun, 24 Apr 2022 12:46:47 +0400 Message-Id: <20220424084647.76577-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220424084647.76577-1-y.oudjana@protonmail.com> References: <20220424084647.76577-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert infracfg bindings to DT schema format. Not all drivers currently implement resets, so #reset-cells is made a required property only for those that do. Using power-controller in the example node name makes #power-domain-cells required causing a dt_binding_check error. To solve this, the node is renamed to syscon@10001000. Signed-off-by: Yassine Oudjana Reviewed-by: Krzysztof Kozlowski --- .../arm/mediatek/mediatek,infracfg.txt | 42 ---------- .../arm/mediatek/mediatek,infracfg.yaml | 81 +++++++++++++++++++ 2 files changed, 81 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,infracfg.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,infracfg.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.t= xt deleted file mode 100644 index f66bd720571d..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek infracfg controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt7986-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible =3D "mediatek,mt8173-infracfg", "syscon"; - reg =3D <0 0x10001000 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.= yaml new file mode 100644 index 000000000000..8681b785ed6d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Infrastructure System Configuration Controller + +maintainers: + - Matthias Brugger + +description: + The Mediatek infracfg controller provides various clocks and reset outpu= ts + to the system. The clock values can be found in , + and reset values in and + . + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6765-infracfg + - mediatek,mt6779-infracfg_ao + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg + - mediatek,mt8516-infracfg + - const: syscon + - items: + - const: mediatek,mt7623-infracfg + - const: mediatek,mt2701-infracfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + infracfg: clock-controller@10001000 { + compatible =3D "mediatek,mt8173-infracfg", "syscon"; + reg =3D <0x10001000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.36.0