From nobody Sun May 10 21:19:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 430BDC433EF for ; Sat, 23 Apr 2022 12:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235391AbiDWMMY (ORCPT ); Sat, 23 Apr 2022 08:12:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235379AbiDWMMT (ORCPT ); Sat, 23 Apr 2022 08:12:19 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79C05229ED2 for ; Sat, 23 Apr 2022 05:09:21 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id s18so21146463ejr.0 for ; Sat, 23 Apr 2022 05:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ul8xsTObKq7dxqXoQV8EI09Hux8ap60oboJuoV8LAW0=; b=LSUia2p58gc1dfhUGH1PJMFheVOjwroaUmlgzniFrkbYBhuGWBDk+B7Iv9WplY0336 a0as++9UuzYctPIX3rhw7aIWxs2Xk3T9yRkpdil0rMMeWfSlO4PFREFoNIwXqw0XPAuJ q+xBynMJP6MZVlczjrhH+zWmpeNYKbpMcF7TE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ul8xsTObKq7dxqXoQV8EI09Hux8ap60oboJuoV8LAW0=; b=5qkYkRdfURS+sSYrOF47sZKum1nU6GB+asNZyPeQ+kUCk15xC7hM7xC5AaEK+Wrtfb 8AeNVEfLHW23Z8JLuGPq3Orb7Em3uB7+Op6UKxjh1EO31yx/J8vKH2q+vrVm0w7UUW+T CiKGi44GaBvyDDhMdO/FYB7Y+QvcyDewq/GSk1um6M+AQxw0hsnNVAoDjO8O6E/GjiIy sKHog0NC7uPoUAwWAYQexEs6TcqPUn4wwakaOnDQ9qFJk43iAf/9OfvtKBrx+HaFq5sh 0bYezrROvOu191s/N3Ji0r8VWeDULQpsWdIDcglGfaWPVy6As1uXZpdzb0eHpGWSa0IU 95QQ== X-Gm-Message-State: AOAM531n+gPa/AeipFxbA1srgQjHehsJjogrLgeroWSTSXwpjqWAtcY/ 2Rar/qFbvqp3toPbB2miz8RQkA== X-Google-Smtp-Source: ABdhPJxs/w+J//eja9Fb7hXl/nc1YqFmIlFoGP9adBbpZUPaD6iHXBPpaUOzLdBJMBPwFbyA3K8rEg== X-Received: by 2002:a17:906:3919:b0:6e8:688d:5fd9 with SMTP id f25-20020a170906391900b006e8688d5fd9mr7961042eje.263.1650715760057; Sat, 23 Apr 2022 05:09:20 -0700 (PDT) Received: from capella.. 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[109.58.122.219]) by smtp.gmail.com with ESMTPSA id hz24-20020a1709072cf800b006f383a4d56bsm24902ejc.4.2022.04.23.05.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 05:09:19 -0700 (PDT) From: =?UTF-8?q?Alvin=20=C5=A0ipraga?= To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter Cc: =?UTF-8?q?Alvin=20=C5=A0ipraga?= , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] drm: bridge: adv7511: enable CEC support for ADV7535 Date: Sat, 23 Apr 2022 14:08:52 +0200 Message-Id: <20220423120854.1503163-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423120854.1503163-1-alvin@pqrs.dk> References: <20220423120854.1503163-1-alvin@pqrs.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alvin =C5=A0ipraga Like the ADV7533, the ADV7535 has an offset for the CEC register map, and it is the same value (ADV7533_REG_CEC_OFFSET =3D 0x70). Rather than testing for numerous chip types in the offset calculations throughout the driver, just compute it during driver probe and put it in the private adv7511 data structure. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Robert Foss --- drivers/gpu/drm/bridge/adv7511/adv7511.h | 1 + drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 18 ++++++------------ drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 5 +++-- 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bri= dge/adv7511/adv7511.h index 6a882891d91c..da6d8ee2cd84 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -335,6 +335,7 @@ struct adv7511 { =20 struct regmap *regmap; struct regmap *regmap_cec; + unsigned int reg_cec_offset; enum drm_connector_status status; bool powered; =20 diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm= /bridge/adv7511/adv7511_cec.c index 28d9becc939c..1f619389e201 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c @@ -21,8 +21,7 @@ =20 static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_statu= s) { - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; unsigned int val; =20 if (regmap_read(adv7511->regmap_cec, @@ -73,8 +72,7 @@ static void adv_cec_tx_raw_status(struct adv7511 *adv7511= , u8 tx_raw_status) =20 void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1) { - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; const u32 irq_tx_mask =3D ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | ADV7511_INT1_CEC_TX_RETRY_TIMEOUT; @@ -118,8 +116,7 @@ void adv7511_cec_irq_process(struct adv7511 *adv7511, u= nsigned int irq1) static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable) { struct adv7511 *adv7511 =3D cec_get_drvdata(adap); - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; =20 if (adv7511->i2c_cec =3D=3D NULL) return -EIO; @@ -165,8 +162,7 @@ static int adv7511_cec_adap_enable(struct cec_adapter *= adap, bool enable) static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr) { struct adv7511 *adv7511 =3D cec_get_drvdata(adap); - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; unsigned int i, free_idx =3D ADV7511_MAX_ADDRS; =20 if (!adv7511->cec_enabled_adap) @@ -235,8 +231,7 @@ static int adv7511_cec_adap_transmit(struct cec_adapter= *adap, u8 attempts, u32 signal_free_time, struct cec_msg *msg) { struct adv7511 *adv7511 =3D cec_get_drvdata(adap); - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; u8 len =3D msg->len; unsigned int i; =20 @@ -289,8 +284,7 @@ static int adv7511_cec_parse_dt(struct device *dev, str= uct adv7511 *adv7511) =20 int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511) { - unsigned int offset =3D adv7511->type =3D=3D ADV7533 ? - ADV7533_REG_CEC_OFFSET : 0; + unsigned int offset =3D adv7511->reg_cec_offset; int ret =3D adv7511_cec_parse_dt(dev, adv7511); =20 if (ret) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm= /bridge/adv7511/adv7511_drv.c index b3f10c54e064..556ba1b447ba 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -1027,8 +1027,7 @@ static bool adv7511_cec_register_volatile(struct devi= ce *dev, unsigned int reg) struct i2c_client *i2c =3D to_i2c_client(dev); struct adv7511 *adv7511 =3D i2c_get_clientdata(i2c); =20 - if (adv7511->type =3D=3D ADV7533 || adv7511->type =3D=3D ADV7535) - reg -=3D ADV7533_REG_CEC_OFFSET; + reg -=3D adv7511->reg_cec_offset; =20 switch (reg) { case ADV7511_REG_CEC_RX_FRAME_HDR: @@ -1073,6 +1072,8 @@ static int adv7511_init_cec_regmap(struct adv7511 *ad= v) ret =3D adv7533_patch_cec_registers(adv); if (ret) goto err; + + adv->reg_cec_offset =3D ADV7533_REG_CEC_OFFSET; } =20 return 0; --=20 2.35.1 From nobody Sun May 10 21:19:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F79FC433EF for ; Sat, 23 Apr 2022 12:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235410AbiDWMM1 (ORCPT ); Sat, 23 Apr 2022 08:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235374AbiDWMMU (ORCPT ); Sat, 23 Apr 2022 08:12:20 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB32A229EDA for ; Sat, 23 Apr 2022 05:09:23 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id i27so21012280ejd.9 for ; Sat, 23 Apr 2022 05:09:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t074mnfEprPk+Vw6axHsXlIYvMupjvMD/CwCAB3T5xQ=; b=OG5oZB+vyMSReXGxuLXWzO+jYzlYCzDcMT99lc3FzgT3o3MB5erPoJoTs0TjnMrfs8 vHgAnRDG4LRRBeuQruXPBwWBuLS677+DQNHPnQnPmDLf1zh+5TBuykxSHNQXKd+ZMURM mxqO8oZCbeslYADcSe6SUghC/ETsgl1eKYW3w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t074mnfEprPk+Vw6axHsXlIYvMupjvMD/CwCAB3T5xQ=; b=vjGzYyafmzdamGaeBUhu/DOxOYiAfuWauZKTLlNqN/P8pOZonDA1zm1YvQVBfrxs8T qZjAnUxKLSLbyq0mtU2zvCR188Yt3BvGURMW8aPaLIw6DEILioEjhnXcF4ch9cMNbT5z VmRe6ZM6W71fPG01i0FzFvhd78lYtuLNzFGeknCIyi7ZYHwPzTmXQ6MOeHE2C1Ft6eT/ le86mxieQOGO8gb6f5GxhUQi/vrNq42DKNovsCD9auJ6NfXR6PBfq+20xwD1E7DnIlUz rtc3xpDwboctquhzSHSENk/ff24t6gAXbfs9lYfVeF174ABFfOIElq5yMj+WVluyJcd4 oUvg== X-Gm-Message-State: AOAM533Q1siS7tAmzgcbUr5r13SjM3yAUOb5MSlDUW9DkkhSslxXzxKQ ZvSxlYPsi7ls9GNbxeSQuW9nnA== X-Google-Smtp-Source: ABdhPJyHXKYOCALDmYqYqgRoTwTkxXyq6wEHBPcQ4PSKn9Ls5UIBVylwIM7h5Tq0mpBB+IBrQQ+59g== X-Received: by 2002:a17:906:a089:b0:6ef:e9e6:1368 with SMTP id q9-20020a170906a08900b006efe9e61368mr8224891ejy.626.1650715762263; Sat, 23 Apr 2022 05:09:22 -0700 (PDT) Received: from capella.. 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[109.58.122.219]) by smtp.gmail.com with ESMTPSA id hz24-20020a1709072cf800b006f383a4d56bsm24902ejc.4.2022.04.23.05.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Apr 2022 05:09:21 -0700 (PDT) From: =?UTF-8?q?Alvin=20=C5=A0ipraga?= To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter Cc: =?UTF-8?q?Alvin=20=C5=A0ipraga?= , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] drm: bridge: adv7511: use non-legacy mode for CEC RX Date: Sat, 23 Apr 2022 14:08:53 +0200 Message-Id: <20220423120854.1503163-3-alvin@pqrs.dk> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220423120854.1503163-1-alvin@pqrs.dk> References: <20220423120854.1503163-1-alvin@pqrs.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alvin =C5=A0ipraga The ADV7511 family of bridges supports two modes for CEC RX: legacy and non-legacy mode. The only difference is whether the chip uses a single CEC RX buffer, or uses all three available RX buffers. Currently the adv7511 driver uses legacy mode. While debugging a stall in CEC RX on an ADV7535, we reached out to Analog Devices, who suggested to use non-legacy mode instead. According to the programming guide for the ADV7511 [1], and the register control manual of the ADV7535 [2], this is the default behaviour on reset. As previously stated, the adv7511 driver currently overrides this to legacy mode. This patch updates the adv7511 driver to instead use non-legacy mode with all three CEC RX buffers. As a result of this change, we no longer experience any stalling of CEC RX with the ADV7535. It is not known why non-legacy mode solves this particular issue, but besides this, no functional change is to be expected by this patch. Please note that this has only been tested on an ADV7535. What follows is a brief description of the non-legacy mode interrupt handling behaviour. The programming guide in [1] gives a more detailed explanation. With three RX buffers, the interrupt handler checks the CEC_RX_STATUS register (renamed from CEC_RX_ENABLE in this patch), which contains 2-bit psuedo-timestamps for each of the RX buffers. The RX timestamps for each buffer represent the time of arrival for the CEC frame held in a given buffer, with lower timestamp values indicating chronologically older frames. A special value of 0 indicates that the given RX buffer is inactive and should be skipped. The interrupt handler parses these timestamps and then reads the active RX buffers in the prescribed order using the same logic as before. Changes have been made to ensure that the correct RX buffer is cleared after processing. This clearing procesure also sets the timestamp of the given RX buffer to 0 to mark it as inactive. [1] https://www.analog.com/media/en/technical-documentation/user-guides/ADV= 7511_Programming_Guide.pdf cf. CEC Map, register 0x4A, bit 3, default value 1: 0 =3D Use only buffer 0 to store CEC frames (Legacy mode) 1 =3D Use all 3 buffers to stores the CEC frames (Non-legacy mode) [2] The ADV7535 register control manual is under NDA, but trust me when I say that non-legacy CEC RX mode is the default here too. Here the register is offset by 0x70 and has an address of 0xBA in the DSI_CEC regiser map. Signed-off-by: Alvin =C5=A0ipraga Reviewed-by: Robert Foss --- drivers/gpu/drm/bridge/adv7511/adv7511.h | 26 +++++- drivers/gpu/drm/bridge/adv7511/adv7511_cec.c | 98 +++++++++++++++----- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 14 ++- 3 files changed, 106 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bri= dge/adv7511/adv7511.h index da6d8ee2cd84..9e3bb8a8ee40 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -209,10 +209,16 @@ #define ADV7511_REG_CEC_TX_ENABLE 0x11 #define ADV7511_REG_CEC_TX_RETRY 0x12 #define ADV7511_REG_CEC_TX_LOW_DRV_CNT 0x14 -#define ADV7511_REG_CEC_RX_FRAME_HDR 0x15 -#define ADV7511_REG_CEC_RX_FRAME_DATA0 0x16 -#define ADV7511_REG_CEC_RX_FRAME_LEN 0x25 -#define ADV7511_REG_CEC_RX_ENABLE 0x26 +#define ADV7511_REG_CEC_RX1_FRAME_HDR 0x15 +#define ADV7511_REG_CEC_RX1_FRAME_DATA0 0x16 +#define ADV7511_REG_CEC_RX1_FRAME_LEN 0x25 +#define ADV7511_REG_CEC_RX_STATUS 0x26 +#define ADV7511_REG_CEC_RX2_FRAME_HDR 0x27 +#define ADV7511_REG_CEC_RX2_FRAME_DATA0 0x28 +#define ADV7511_REG_CEC_RX2_FRAME_LEN 0x37 +#define ADV7511_REG_CEC_RX3_FRAME_HDR 0x38 +#define ADV7511_REG_CEC_RX3_FRAME_DATA0 0x39 +#define ADV7511_REG_CEC_RX3_FRAME_LEN 0x48 #define ADV7511_REG_CEC_RX_BUFFERS 0x4a #define ADV7511_REG_CEC_LOG_ADDR_MASK 0x4b #define ADV7511_REG_CEC_LOG_ADDR_0_1 0x4c @@ -220,6 +226,18 @@ #define ADV7511_REG_CEC_CLK_DIV 0x4e #define ADV7511_REG_CEC_SOFT_RESET 0x50 =20 +static const u8 ADV7511_REG_CEC_RX_FRAME_HDR[] =3D { + ADV7511_REG_CEC_RX1_FRAME_HDR, + ADV7511_REG_CEC_RX2_FRAME_HDR, + ADV7511_REG_CEC_RX3_FRAME_HDR, +}; + +static const u8 ADV7511_REG_CEC_RX_FRAME_LEN[] =3D { + ADV7511_REG_CEC_RX1_FRAME_LEN, + ADV7511_REG_CEC_RX2_FRAME_LEN, + ADV7511_REG_CEC_RX3_FRAME_LEN, +}; + #define ADV7533_REG_CEC_OFFSET 0x70 =20 enum adv7511_input_clock { diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm= /bridge/adv7511/adv7511_cec.c index 1f619389e201..399f625a50c8 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c @@ -17,7 +17,8 @@ =20 #define ADV7511_INT1_CEC_MASK \ (ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \ - ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1) + ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1 | \ + ADV7511_INT1_CEC_RX_READY2 | ADV7511_INT1_CEC_RX_READY3) =20 static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_statu= s) { @@ -70,25 +71,16 @@ static void adv_cec_tx_raw_status(struct adv7511 *adv75= 11, u8 tx_raw_status) } } =20 -void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1) +static void adv7511_cec_rx(struct adv7511 *adv7511, int rx_buf) { unsigned int offset =3D adv7511->reg_cec_offset; - const u32 irq_tx_mask =3D ADV7511_INT1_CEC_TX_READY | - ADV7511_INT1_CEC_TX_ARBIT_LOST | - ADV7511_INT1_CEC_TX_RETRY_TIMEOUT; struct cec_msg msg =3D {}; unsigned int len; unsigned int val; u8 i; =20 - if (irq1 & irq_tx_mask) - adv_cec_tx_raw_status(adv7511, irq1); - - if (!(irq1 & ADV7511_INT1_CEC_RX_READY1)) - return; - if (regmap_read(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_FRAME_LEN + offset, &len)) + ADV7511_REG_CEC_RX_FRAME_LEN[rx_buf] + offset, &len)) return; =20 msg.len =3D len & 0x1f; @@ -101,18 +93,76 @@ void adv7511_cec_irq_process(struct adv7511 *adv7511, = unsigned int irq1) =20 for (i =3D 0; i < msg.len; i++) { regmap_read(adv7511->regmap_cec, - i + ADV7511_REG_CEC_RX_FRAME_HDR + offset, &val); + i + ADV7511_REG_CEC_RX_FRAME_HDR[rx_buf] + offset, + &val); msg.msg[i] =3D val; } =20 - /* toggle to re-enable rx 1 */ - regmap_write(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_BUFFERS + offset, 1); - regmap_write(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_BUFFERS + offset, 0); + /* Toggle RX Ready Clear bit to re-enable this RX buffer */ + regmap_update_bits(adv7511->regmap_cec, + ADV7511_REG_CEC_RX_BUFFERS + offset, BIT(rx_buf), + BIT(rx_buf)); + regmap_update_bits(adv7511->regmap_cec, + ADV7511_REG_CEC_RX_BUFFERS + offset, BIT(rx_buf), 0); + cec_received_msg(adv7511->cec_adap, &msg); } =20 +void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1) +{ + unsigned int offset =3D adv7511->reg_cec_offset; + const u32 irq_tx_mask =3D ADV7511_INT1_CEC_TX_READY | + ADV7511_INT1_CEC_TX_ARBIT_LOST | + ADV7511_INT1_CEC_TX_RETRY_TIMEOUT; + const u32 irq_rx_mask =3D ADV7511_INT1_CEC_RX_READY1 | + ADV7511_INT1_CEC_RX_READY2 | + ADV7511_INT1_CEC_RX_READY3; + unsigned int rx_status; + int rx_order[3] =3D { -1, -1, -1 }; + int i; + + if (irq1 & irq_tx_mask) + adv_cec_tx_raw_status(adv7511, irq1); + + if (!(irq1 & irq_rx_mask)) + return; + + if (regmap_read(adv7511->regmap_cec, + ADV7511_REG_CEC_RX_STATUS + offset, &rx_status)) + return; + + /* + * ADV7511_REG_CEC_RX_STATUS[5:0] contains the reception order of RX + * buffers 0, 1, and 2 in bits [1:0], [3:2], and [5:4] respectively. + * The values are to be interpreted as follows: + * + * 0 =3D buffer unused + * 1 =3D buffer contains oldest received frame (if applicable) + * 2 =3D buffer contains second oldest received frame (if applicable) + * 3 =3D buffer contains third oldest received frame (if applicable) + * + * Fill rx_order with the sequence of RX buffer indices to + * read from in order, where -1 indicates that there are no + * more buffers to process. + */ + for (i =3D 0; i < 3; i++) { + unsigned int timestamp =3D (rx_status >> (2 * i)) & 0x3; + + if (timestamp) + rx_order[timestamp - 1] =3D i; + } + + /* Read CEC RX buffers in the appropriate order as prescribed above */ + for (i =3D 0; i < 3; i++) { + int rx_buf =3D rx_order[i]; + + if (rx_buf < 0) + break; + + adv7511_cec_rx(adv7511, rx_buf); + } +} + static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable) { struct adv7511 *adv7511 =3D cec_get_drvdata(adap); @@ -126,11 +176,11 @@ static int adv7511_cec_adap_enable(struct cec_adapter= *adap, bool enable) regmap_update_bits(adv7511->regmap_cec, ADV7511_REG_CEC_CLK_DIV + offset, 0x03, 0x01); - /* legacy mode and clear all rx buffers */ + /* non-legacy mode and clear all rx buffers */ regmap_write(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_BUFFERS + offset, 0x07); + ADV7511_REG_CEC_RX_BUFFERS + offset, 0x0f); regmap_write(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_BUFFERS + offset, 0); + ADV7511_REG_CEC_RX_BUFFERS + offset, 0x08); /* initially disable tx */ regmap_update_bits(adv7511->regmap_cec, ADV7511_REG_CEC_TX_ENABLE + offset, 1, 0); @@ -138,7 +188,7 @@ static int adv7511_cec_adap_enable(struct cec_adapter *= adap, bool enable) /* tx: ready */ /* tx: arbitration lost */ /* tx: retry timeout */ - /* rx: ready 1 */ + /* rx: ready 1-3 */ regmap_update_bits(adv7511->regmap, ADV7511_REG_INT_ENABLE(1), 0x3f, ADV7511_INT1_CEC_MASK); @@ -304,9 +354,9 @@ int adv7511_cec_init(struct device *dev, struct adv7511= *adv7511) regmap_write(adv7511->regmap_cec, ADV7511_REG_CEC_SOFT_RESET + offset, 0x00); =20 - /* legacy mode */ + /* non-legacy mode - use all three RX buffers */ regmap_write(adv7511->regmap_cec, - ADV7511_REG_CEC_RX_BUFFERS + offset, 0x00); + ADV7511_REG_CEC_RX_BUFFERS + offset, 0x08); =20 regmap_write(adv7511->regmap_cec, ADV7511_REG_CEC_CLK_DIV + offset, diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm= /bridge/adv7511/adv7511_drv.c index 556ba1b447ba..5bb9300040dd 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -1030,10 +1030,16 @@ static bool adv7511_cec_register_volatile(struct de= vice *dev, unsigned int reg) reg -=3D adv7511->reg_cec_offset; =20 switch (reg) { - case ADV7511_REG_CEC_RX_FRAME_HDR: - case ADV7511_REG_CEC_RX_FRAME_DATA0... - ADV7511_REG_CEC_RX_FRAME_DATA0 + 14: - case ADV7511_REG_CEC_RX_FRAME_LEN: + case ADV7511_REG_CEC_RX1_FRAME_HDR: + case ADV7511_REG_CEC_RX1_FRAME_DATA0 ... ADV7511_REG_CEC_RX1_FRAME_DATA0 = + 14: + case ADV7511_REG_CEC_RX1_FRAME_LEN: + case ADV7511_REG_CEC_RX2_FRAME_HDR: + case ADV7511_REG_CEC_RX2_FRAME_DATA0 ... ADV7511_REG_CEC_RX2_FRAME_DATA0 = + 14: + case ADV7511_REG_CEC_RX2_FRAME_LEN: + case ADV7511_REG_CEC_RX3_FRAME_HDR: + case ADV7511_REG_CEC_RX3_FRAME_DATA0 ... ADV7511_REG_CEC_RX3_FRAME_DATA0 = + 14: + case ADV7511_REG_CEC_RX3_FRAME_LEN: + case ADV7511_REG_CEC_RX_STATUS: case ADV7511_REG_CEC_RX_BUFFERS: case ADV7511_REG_CEC_TX_LOW_DRV_CNT: return true; --=20 2.35.1