From nobody Sun Sep 22 05:44:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69200C433EF for ; Fri, 22 Apr 2022 06:03:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1444210AbiDVGGb (ORCPT ); Fri, 22 Apr 2022 02:06:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1444137AbiDVGFM (ORCPT ); Fri, 22 Apr 2022 02:05:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 819EC4FC60; Thu, 21 Apr 2022 23:02:19 -0700 (PDT) X-UUID: 588a78cbe81547249a0fb7a2b7e5971c-20220422 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:6489da25-fe07-41cb-af9c-efcc5ba62608,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:f124bdef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 588a78cbe81547249a0fb7a2b7e5971c-20220422 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1486043969; Fri, 22 Apr 2022 14:02:13 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Apr 2022 14:01:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 14:01:58 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V3 08/17] clk: mediatek: reset: Add new register reset function with device Date: Fri, 22 Apr 2022 14:01:43 +0800 Message-ID: <20220422060152.13534-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220422060152.13534-1-rex-bc.chen@mediatek.com> References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's a proper implementation using device to register reset controller. Howerver, some clock drviers of MediaTeks only provide device_node. Therefore, we still remain register reset function with device_node and add a function with device to register reset controller. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mt2712.c | 4 +- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +- drivers/clk/mediatek/clk-mt7622.c | 4 +- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/reset.c | 53 +++++++++++++++++++++++++++ drivers/clk/mediatek/reset.h | 2 + 13 files changed, 71 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index b651f3878267..90d662d955a9 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -64,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *p= dev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 7696870f6f23..fc6563e29da7 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -58,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index 57fa63c47452..13acc15de2e3 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -63,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *p= dev) return r; } =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 496afc7483ae..76662d1810ab 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -800,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return 0; } @@ -923,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 04ff9b1327d2..664d56d665fe 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1376,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_dev= ice *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return r; } @@ -1398,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_devi= ce *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 3bf7f4610ad1..88462698c2af 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -88,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 88fe9b447158..bb23a88a7810 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -99,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } @@ -121,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 3f937723b211..8f2003dd1e75 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -678,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return 0; } @@ -729,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) =20 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index 079b8facf63f..32f035822a9a 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -98,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 69a2ecf8d3df..e4a5b66ac005 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -94,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } @@ -116,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index c957249d4cdf..b8884e94604d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1245,7 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_dev= ice *pdev) return r; } =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 03d865f3308e..fe917b2eeab4 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -149,4 +149,57 @@ int mtk_register_reset_controller(struct device_node *= np, return 0; } =20 +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc) +{ + struct device_node *np =3D dev->of_node; + struct regmap *regmap; + const struct reset_control_ops *rcops =3D NULL; + struct mtk_clk_rst_data *data; + int ret; + + if (!desc) { + dev_err(dev, "mtk clock reset desc is NULL\n"); + return -EINVAL; + } + + switch (desc->version) { + case MTK_RST_SIMPLE: + rcops =3D &mtk_reset_ops; + break; + case MTK_RST_SET_CLR: + rcops =3D &mtk_reset_ops_set_clr; + break; + default: + dev_err(dev, "Unknown reset version %d\n", desc->version); + return -EINVAL; + } + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) { + dev_err(dev, "Cannot find regmap %pe\n", regmap); + return -EINVAL; + } + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc =3D desc; + data->regmap =3D regmap; + data->rcdev.owner =3D THIS_MODULE; + data->rcdev.nr_resets =3D desc->rst_set_nr * 32; + data->rcdev.ops =3D rcops; + data->rcdev.of_node =3D np; + data->rcdev.dev =3D dev; + + ret =3D devm_reset_controller_register(dev, &data->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller: %d\n", ret); + return ret; + } + + return 0; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index c3a2f2a4f486..79efbea37c9b 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -29,5 +29,7 @@ struct mtk_clk_rst_data { =20 int mtk_register_reset_controller(struct device_node *np, const struct mtk_clk_rst_desc *desc); +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc); =20 #endif /* __DRV_CLK_MTK_RESET_H */ --=20 2.18.0