From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2950C433EF for ; Thu, 21 Apr 2022 10:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388147AbiDUKN7 (ORCPT ); Thu, 21 Apr 2022 06:13:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231376AbiDUKNp (ORCPT ); Thu, 21 Apr 2022 06:13:45 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BBE8E31 for ; Thu, 21 Apr 2022 03:10:56 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id t4so4265562pgc.1 for ; Thu, 21 Apr 2022 03:10:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tuFN4GoodRCoG0JXqpv/xpJ28l/3+jmqR5oJQdyxXWQ=; b=cuPC+hTe+2ouqxhRuHZqyj7MCQ2K4ZZQ9IiNAcXkSMhX8QTBajy8n9iSkZYOGancSM HXzxZA0OqUHlkXdBZaU6IK7gAZC7Pj6KBtzLtGiSnxS4n67msptf2TRGSLTNappcT5x6 fPhZWNqZ/B5LFQNhTJzvfAZyPNnTdO6EN8FUloqSYJIpnDEkWg3u/p5/H8xATbxuEobX kLJqrAF5fevSN7tuMNV/p8M+FTzyfEb6DJmUsPDnr+dQJZnjHEx7NEN6LpPDYrEXMMH8 uB1NMg+A2b6KuoK+5Q6Q7pQzX3mE/cu2NbTyrnLre4h0QjDm5cuyEsBr3U6CKhqz+2cq gVQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tuFN4GoodRCoG0JXqpv/xpJ28l/3+jmqR5oJQdyxXWQ=; b=K7z1dRygcM0gb05SfPOywONjBCJvTgJMbOpS+7oMSJZ9eKSnjtljt/Imn+yI8uublR TfrzW3FB7wtwNUFu/d1VzkswThi+unBsSMvF9skJvZjrrnF6itL5CJT+jb9x7yVH7yHB ZD+ycA2qSjWu5ZiZIg4feyIdm7qzLMtZHJQyYSmoPwQ4O/UEGLfmapXFEc7BWm9B2DtK SIO3hw0TTBxDfyihUGdULQYeFpOpz9CRK8RgenTkwf32uTr6aHlVcbMHI9hF/DieJKLG rIR03/Cn3HXUK7SolTheIbrgH6qOJvNgsCHAo+yuWzXKNVvhl3XbiSIUvh58e0hwCM3N a6yw== X-Gm-Message-State: AOAM532AnpwAvSYBDJ1hL/1+ZGtpO8vkCbjMzyP5NqkedAOitAsYcnNY kUDM/iuUjCiaizHVbEpa2LE= X-Google-Smtp-Source: ABdhPJxErW+PvY3TDLlcay6TKXoRjeJ3IwhowfTYGjmmGZwW5q9Lz1CBtJtxRiFdXuiscjz95btgXg== X-Received: by 2002:a63:2266:0:b0:39c:f643:ee69 with SMTP id t38-20020a632266000000b0039cf643ee69mr22819993pgm.288.1650535855684; Thu, 21 Apr 2022 03:10:55 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:10:54 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 01/10] xtensa: clean up function declarations in traps.c Date: Thu, 21 Apr 2022 03:10:24 -0700 Message-Id: <20220421101033.216394-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop 'extern' from all function declarations and move those that need to be visible from traps.c to traps.h. Add 'asmlinkage' to declarations of fucntions defined in assembly. Add 'static' to declarations and definitions only used locally. Add argument names in declarations. Drop unused second argument from do_multihit and do_page_fault. Signed-off-by: Max Filippov --- Changes v1->v2: - move declarations to traps.h and add 'asmlinkage' annotations arch/xtensa/include/asm/traps.h | 18 +++++++++++-- arch/xtensa/kernel/traps.c | 46 ++++++++++++--------------------- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index 6fa47cd8e02d..fc63217232a4 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -39,8 +39,22 @@ struct exc_table { * void (*)(struct pt_regs *regs, unsigned long exccause); */ extern void * __init trap_set_handler(int cause, void *handler); -extern void do_unhandled(struct pt_regs *regs, unsigned long exccause); -void fast_second_level_miss(void); + +asmlinkage void fast_illegal_instruction_user(void); +asmlinkage void fast_syscall_user(void); +asmlinkage void fast_alloca(void); +asmlinkage void fast_unaligned(void); +asmlinkage void fast_second_level_miss(void); +asmlinkage void fast_store_prohibited(void); +asmlinkage void fast_coprocessor(void); + +asmlinkage void kernel_exception(void); +asmlinkage void user_exception(void); +asmlinkage void system_call(struct pt_regs *regs); + +void do_IRQ(int hwirq, struct pt_regs *regs); +void do_page_fault(struct pt_regs *regs); +void do_unhandled(struct pt_regs *regs, unsigned long exccause); =20 /* Initialize minimal exc_table structure sufficient for basic paging */ static inline void __init early_trap_init(void) diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 515719c7e750..b6bb5911ec7f 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -48,25 +48,16 @@ * Machine specific interrupt handlers */ =20 -extern void kernel_exception(void); -extern void user_exception(void); - -extern void fast_illegal_instruction_user(void); -extern void fast_syscall_user(void); -extern void fast_alloca(void); -extern void fast_unaligned(void); -extern void fast_second_level_miss(void); -extern void fast_store_prohibited(void); -extern void fast_coprocessor(void); - -extern void do_illegal_instruction (struct pt_regs*); -extern void do_interrupt (struct pt_regs*); -extern void do_nmi(struct pt_regs *); -extern void do_unaligned_user (struct pt_regs*); -extern void do_multihit (struct pt_regs*, unsigned long); -extern void do_page_fault (struct pt_regs*, unsigned long); -extern void do_debug (struct pt_regs*); -extern void system_call (struct pt_regs*); +static void do_illegal_instruction(struct pt_regs *regs); +static void do_interrupt(struct pt_regs *regs); +#if XTENSA_FAKE_NMI +static void do_nmi(struct pt_regs *regs); +#endif +#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION +static void do_unaligned_user(struct pt_regs *regs); +#endif +static void do_multihit(struct pt_regs *regs); +static void do_debug(struct pt_regs *regs); =20 /* * The vector table must be preceded by a save area (which @@ -197,7 +188,7 @@ void do_unhandled(struct pt_regs *regs, unsigned long e= xccause) * Multi-hit exception. This if fatal! */ =20 -void do_multihit(struct pt_regs *regs, unsigned long exccause) +static void do_multihit(struct pt_regs *regs) { die("Caught multihit exception", regs, SIGKILL); } @@ -206,8 +197,6 @@ void do_multihit(struct pt_regs *regs, unsigned long ex= ccause) * IRQ handler. */ =20 -extern void do_IRQ(int, struct pt_regs *); - #if XTENSA_FAKE_NMI =20 #define IS_POW2(v) (((v) & ((v) - 1)) =3D=3D 0) @@ -240,7 +229,7 @@ irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_i= d); =20 DEFINE_PER_CPU(unsigned long, nmi_count); =20 -void do_nmi(struct pt_regs *regs) +static void do_nmi(struct pt_regs *regs) { struct pt_regs *old_regs =3D set_irq_regs(regs); =20 @@ -253,7 +242,7 @@ void do_nmi(struct pt_regs *regs) } #endif =20 -void do_interrupt(struct pt_regs *regs) +static void do_interrupt(struct pt_regs *regs) { static const unsigned int_level_mask[] =3D { 0, @@ -303,8 +292,7 @@ void do_interrupt(struct pt_regs *regs) * Illegal instruction. Fatal if in kernel space. */ =20 -void -do_illegal_instruction(struct pt_regs *regs) +static void do_illegal_instruction(struct pt_regs *regs) { __die_if_kernel("Illegal instruction in kernel", regs, SIGKILL); =20 @@ -324,8 +312,7 @@ do_illegal_instruction(struct pt_regs *regs) */ =20 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION -void -do_unaligned_user (struct pt_regs *regs) +static void do_unaligned_user(struct pt_regs *regs) { __die_if_kernel("Unhandled unaligned exception in kernel", regs, SIGKILL); @@ -346,8 +333,7 @@ do_unaligned_user (struct pt_regs *regs) * breakpoint structures to debug registers intact, so that * DEBUGCAUSE.DBNUM could be used in case of data breakpoint hit. */ -void -do_debug(struct pt_regs *regs) +static void do_debug(struct pt_regs *regs) { #ifdef CONFIG_HAVE_HW_BREAKPOINT int ret =3D check_hw_breakpoint(regs); --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D427AC433EF for ; Thu, 21 Apr 2022 10:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388162AbiDUKOH (ORCPT ); Thu, 21 Apr 2022 06:14:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387973AbiDUKNr (ORCPT ); Thu, 21 Apr 2022 06:13:47 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7407F0B for ; Thu, 21 Apr 2022 03:10:57 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id g3so3621421pgg.3 for ; Thu, 21 Apr 2022 03:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zKmvG5lJapAQ9lDEo7MY00QMdh+x4EBTY4Sy6sMzD7o=; b=X8uknKHZcBU6r3jnBw07u1EPP3qYMedxnlZDHplc9a4JmCO2RfDOD7i+Hx89/DqEan Fp0lbIXo8IE3TM/hphytWfEjlrDXcrFiw3OGSf9J9pg4WrvDsnhphvzm1r/82zaHSP4A phHU7zzWttbb79IapD9rgEVMkdikEbnp2SRpYuQi1FkQGeoCBVbpZIG4hUS2ayLXcX9H zNk+fgkdbbiziZOaNBcUjqk5Kv7G5Slo4IgtzOIUlyIQkaKC3UL2FTBsMYGOzOkfUTXY cqNzGaITm2iuqjfEUlO7A2aazPKy2+ipwBxdzxql2erl7TuLuaM8UCP+2cSGBuU+07xU inAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zKmvG5lJapAQ9lDEo7MY00QMdh+x4EBTY4Sy6sMzD7o=; b=slR59CFK+qmckZ5X1iEobpA59f+btisYQieRp5tzYdaArkwCZFmY/hReo7CdYvG17z y5QhOlT/WtPT44hk0X5uvmsAOqb7vf5yblUt9mcZuhP+IBuJg7zhd7xOxbe/txMC5fwf zmUbQQjXevDSD7K9owhTpyKEe95Drlu/NWAW0xS1cd0ajzfoFQqTBy6JNQ+gdcavwgUU OX1zvQgAV/E/Ne1qmjwSILx39oLBY2x903PWm4qB1m712elnCrRT/UgvsmV2D0Ujn20Q WYTtghPM5Q5QFoAGnpJ3E+2ZDRm1VqX3o902rnLa0tCGIMAsukA3ac0lRpbn2xamjjPF 56gw== X-Gm-Message-State: AOAM530d5L7dtIkW0Xv5t3glaoc/PoRJZL4dP16Hk/5/CKTIEOIvJYtH Wqgz+IiXk98IheMui1LndGA= X-Google-Smtp-Source: ABdhPJxr/FUChNNj8WRhFaSf+GSMSw9wBZrDtia42yQBMMdt3wUzWSmUEkLZpey8ysp1Ud4CoW/9eA== X-Received: by 2002:a05:6a00:cd2:b0:50a:7685:8055 with SMTP id b18-20020a056a000cd200b0050a76858055mr20559622pfv.37.1650535857204; Thu, 21 Apr 2022 03:10:57 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:10:56 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 02/10] xtensa: clean up exception handler prototypes Date: Thu, 21 Apr 2022 03:10:25 -0700 Message-Id: <20220421101033.216394-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Exception handlers are currently passed as void pointers because they may have one or two parameters. Only two handlers uses the second parameter and it is available in the struct pt_regs anyway. Make all handlers have only one parameter, introduce xtensa_exception_handler type for handlers and use it in trap_set_handler. Signed-off-by: Max Filippov --- Changes v1->v2: - new patch arch/xtensa/include/asm/traps.h | 14 ++++++-------- arch/xtensa/kernel/s32c1i_selftest.c | 7 +++---- arch/xtensa/kernel/traps.c | 7 ++++--- 3 files changed, 13 insertions(+), 15 deletions(-) diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index fc63217232a4..bfdb0af61b07 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -12,6 +12,8 @@ =20 #include =20 +typedef void xtensa_exception_handler(struct pt_regs *regs); + /* * Per-CPU exception handling data structure. * EXCSAVE1 points to it. @@ -30,15 +32,11 @@ struct exc_table { /* Fast kernel exception handlers */ void *fast_kernel_handler[EXCCAUSE_N]; /* Default C-Handlers */ - void *default_handler[EXCCAUSE_N]; + xtensa_exception_handler *default_handler[EXCCAUSE_N]; }; =20 -/* - * handler must be either of the following: - * void (*)(struct pt_regs *regs); - * void (*)(struct pt_regs *regs, unsigned long exccause); - */ -extern void * __init trap_set_handler(int cause, void *handler); +xtensa_exception_handler * +__init trap_set_handler(int cause, xtensa_exception_handler *handler); =20 asmlinkage void fast_illegal_instruction_user(void); asmlinkage void fast_syscall_user(void); @@ -54,7 +52,7 @@ asmlinkage void system_call(struct pt_regs *regs); =20 void do_IRQ(int hwirq, struct pt_regs *regs); void do_page_fault(struct pt_regs *regs); -void do_unhandled(struct pt_regs *regs, unsigned long exccause); +void do_unhandled(struct pt_regs *regs); =20 /* Initialize minimal exc_table structure sufficient for basic paging */ static inline void __init early_trap_init(void) diff --git a/arch/xtensa/kernel/s32c1i_selftest.c b/arch/xtensa/kernel/s32c= 1i_selftest.c index 07e56e3a9a8b..8362388c8719 100644 --- a/arch/xtensa/kernel/s32c1i_selftest.c +++ b/arch/xtensa/kernel/s32c1i_selftest.c @@ -40,14 +40,13 @@ static inline int probed_compare_swap(int *v, int cmp, = int set) =20 /* Handle probed exception */ =20 -static void __init do_probed_exception(struct pt_regs *regs, - unsigned long exccause) +static void __init do_probed_exception(struct pt_regs *regs) { if (regs->pc =3D=3D rcw_probe_pc) { /* exception on s32c1i ? */ regs->pc +=3D 3; /* skip the s32c1i instruction */ - rcw_exc =3D exccause; + rcw_exc =3D regs->exccause; } else { - do_unhandled(regs, exccause); + do_unhandled(regs); } } =20 diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index b6bb5911ec7f..d6b1a0c3e319 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -170,7 +170,7 @@ __die_if_kernel(const char *str, struct pt_regs *regs, = long err) * Unhandled Exceptions. Kill user task or panic if in kernel space. */ =20 -void do_unhandled(struct pt_regs *regs, unsigned long exccause) +void do_unhandled(struct pt_regs *regs) { __die_if_kernel("Caught unhandled exception - should not happen", regs, SIGKILL); @@ -180,7 +180,7 @@ void do_unhandled(struct pt_regs *regs, unsigned long e= xccause) "(pid =3D %d, pc =3D %#010lx) - should not happen\n" "\tEXCCAUSE is %ld\n", current->comm, task_pid_nr(current), regs->pc, - exccause); + regs->exccause); force_sig(SIGILL); } =20 @@ -360,7 +360,8 @@ static void do_debug(struct pt_regs *regs) =20 /* Set exception C handler - for temporary use when probing exceptions */ =20 -void * __init trap_set_handler(int cause, void *handler) +xtensa_exception_handler * +__init trap_set_handler(int cause, xtensa_exception_handler *handler) { void *previous =3D per_cpu(exc_table, 0).default_handler[cause]; =20 --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFA5BC433F5 for ; Thu, 21 Apr 2022 10:11:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388177AbiDUKOL (ORCPT ); Thu, 21 Apr 2022 06:14:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388111AbiDUKNs (ORCPT ); Thu, 21 Apr 2022 06:13:48 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585E1F6B for ; Thu, 21 Apr 2022 03:10:59 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id q1so3227156plx.13 for ; Thu, 21 Apr 2022 03:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B7FHzMluexVIsqE1V6kW5pfW6b+ReTL+xQGzEDyIhFU=; b=kjChlxe8VgxE69b7ApaQ9rh9eBMJrVErU/WvoNjea/mBJgU00BBPN84LnSuKDz6tV2 cfBdsrBP1RSkgl0uOoTOX5kdSp99GZN60D1zCdqE38rT7q/DHSjgYD6S4PTnKIiiw9mF mIc/+nhe/SYvf2LSYs2f8ea8h2pmoyX5g8g21KtUgcRTwE+UIS/xTr+DBgOuuxj3OigW cmrDVt5aPS4pRvphKSwnYdOqbE9ZzY+dvyeurA0+iYqKOb1JjOth3DHYyCLJvwqCFVkR ZuE/o/MGJEYlzxBWt0mlxypekFk5w2yXD/oulg4/Ea1dLZ+87PiWKYsWD76/oANz97gP t2wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B7FHzMluexVIsqE1V6kW5pfW6b+ReTL+xQGzEDyIhFU=; b=fdHeTzQNPZRZzlE5Hu3/0RFQu3rAR8uMLAPgUEgArkmCzNmxspviN9gIFOzfqQAroA y/DYErkl1U5x6btzoFLO7SKFsIXv2jMqZAVll7uR478GCh1L5RYXS/ohWdLvmhSrFqAT BxuUDlS0ui2mS8gP+uaVkPWRx4uaQzLF6FkDRnhjrEZC+RYnyfnd2jrib3B8L52Gfv3v RHE3YJfuEaX54/pVDzFwTvnExTudHUlVsI8+QgGguELcmnjCb5iUp88JyKBjRzbtHolb ADDkBs0Twc7Hmst2O4PWtSxkehsJrsCyR8J1pcMuKkmuJ3/8pCOqxrDtJo9lnf4Ec4aG L2zw== X-Gm-Message-State: AOAM531zwIISC8oymXplOUPkpgELmDTwgAEZfwu/apqtAI/7ZwzTLZDh uWjLEUcSQjbqYLuETWA+q9s= X-Google-Smtp-Source: ABdhPJxb94NYpExDFY4CbV2v7r3MsQKhZOz394WqSve1CnQS1Vqb1f6BadHKuN58Ai+KR2vqO6Cl4w== X-Received: by 2002:a17:902:6ac7:b0:150:24d6:b2ee with SMTP id i7-20020a1709026ac700b0015024d6b2eemr24843852plt.168.1650535858700; Thu, 21 Apr 2022 03:10:58 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:10:58 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 03/10] xtensa: clean up declarations in coprocessor.h Date: Thu, 21 Apr 2022 03:10:26 -0700 Message-Id: <20220421101033.216394-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop 'extern' from all function declarations. Add parameter names in declarations. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/coprocessor.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/as= m/coprocessor.h index 0fbe2a740b8d..a360efced7e7 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -143,10 +143,9 @@ typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); =20 extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; -extern void coprocessor_flush(struct thread_info*, int); - -extern void coprocessor_release_all(struct thread_info*); -extern void coprocessor_flush_all(struct thread_info*); +void coprocessor_flush(struct thread_info *ti, int cp_index); +void coprocessor_release_all(struct thread_info *ti); +void coprocessor_flush_all(struct thread_info *ti); =20 #endif /* XTENSA_HAVE_COPROCESSORS */ =20 --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 582BEC433F5 for ; Thu, 21 Apr 2022 10:11:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388184AbiDUKOR (ORCPT ); Thu, 21 Apr 2022 06:14:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388116AbiDUKNt (ORCPT ); Thu, 21 Apr 2022 06:13:49 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 986CBBB9 for ; Thu, 21 Apr 2022 03:11:00 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id z6-20020a17090a398600b001cb9fca3210so4750370pjb.1 for ; Thu, 21 Apr 2022 03:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RX5iF0HtvkRBM2maUvoUXLZ+1rzQwjz1rJUJGgTLGgc=; b=CfVifOM3cHI3CnnB7pbqZiEHrIUZ8KSh9YgMU/iUgsbkX7GgNVDDJLuPLghfXfxVJs ALTUPSzGkgsuJL4opQTNkoYHM19lwWShNsrgXPD9cAB42eHfBT6BtsD0nM1dnOGTv2i+ R4QarCAmnTq5xHAe7JAbH5TLeZDGIgYbrAhSmhftQYtByfNYyOP3y1Dvsduf+x543P/F XuAtVF2tJhlPb3muDxc1j6XDps81zCF4vgztyB3ckWge6o0tRTXYYg2fbx/Dx5yIjl+Z 7RgBB/QB6FeDBN+ATwhcI+zL/uh08jDzOG2gga994WbI83IP7AGzSli6fm1dOBc45l73 RHyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RX5iF0HtvkRBM2maUvoUXLZ+1rzQwjz1rJUJGgTLGgc=; b=Z+kRJmDzkdHbLz4DC30H3SqAZD79tE/2Ggny5krqZDr2auEHjlchUs5ANc2Ji45Euz 0sdlVzm5SRQZ2YoJ2BtJdnCUI3CBZUiwN53DOO0Xc9S+7qCf5gPKmPP9rgNaUSFfNqFE TJaenKgdkjQuP4MTUpUl0+7kUBSUHezruVi0ml/Um8ucU94cjQGjYBlxnrDyCw7301mC 86iKTc8nVUAco1w2hIbD/Gkef8aYi+wZdK8xOyy+qclCC90FMZjPWIqblA+SgdR2EBiV 3gV/wGQCO4mdUfhhttWzNomokfh3H0udODwp1HbXid4xUW5lgJmWMAK+yRbOaqA7xIfD vrcA== X-Gm-Message-State: AOAM530YJbbawdDJT3x/sSBmrRjqblWVNkPlIliNRsLwP5rYaCrTrcmo a6VFF/cF9thPCbeZR4XDy0w= X-Google-Smtp-Source: ABdhPJznA9iYGQjenX1DRqkxmGXQFzHF3/OwRD34uEMoP0v3Tsdgg86q7k0I/Y4qTXbPYQnka7aTAw== X-Received: by 2002:a17:902:9a0a:b0:158:a22a:5448 with SMTP id v10-20020a1709029a0a00b00158a22a5448mr25546443plp.20.1650535860130; Thu, 21 Apr 2022 03:11:00 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.10.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:10:59 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 04/10] xtensa: clean up excsave1 initialization Date: Thu, 21 Apr 2022 03:10:27 -0700 Message-Id: <20220421101033.216394-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use xtensa_set_sr instead of inline assembly. Rename local variable exc_table in early_trap_init to avoid conflict with per-CPU variable of the same name. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/traps.h | 4 ++-- arch/xtensa/kernel/traps.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index bfdb0af61b07..514376eff58c 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -57,11 +57,11 @@ void do_unhandled(struct pt_regs *regs); /* Initialize minimal exc_table structure sufficient for basic paging */ static inline void __init early_trap_init(void) { - static struct exc_table exc_table __initdata =3D { + static struct exc_table init_exc_table __initdata =3D { .fast_kernel_handler[EXCCAUSE_DTLB_MISS] =3D fast_second_level_miss, }; - __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (&exc_table)); + xtensa_set_sr(&init_exc_table, excsave1); } =20 void secondary_trap_init(void); diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index d6b1a0c3e319..95903f25e523 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -372,8 +372,7 @@ __init trap_set_handler(int cause, xtensa_exception_han= dler *handler) =20 static void trap_init_excsave(void) { - unsigned long excsave1 =3D (unsigned long)this_cpu_ptr(&exc_table); - __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1)); + xtensa_set_sr(this_cpu_ptr(&exc_table), excsave1); } =20 static void trap_init_debug(void) --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47ACEC433F5 for ; Thu, 21 Apr 2022 10:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388194AbiDUKOY (ORCPT ); Thu, 21 Apr 2022 06:14:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388126AbiDUKNv (ORCPT ); Thu, 21 Apr 2022 06:13:51 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2294CC27 for ; Thu, 21 Apr 2022 03:11:02 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id md20-20020a17090b23d400b001cb70ef790dso7320605pjb.5 for ; Thu, 21 Apr 2022 03:11:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Y9Xga+Vf57beXiQKhYl2BdatYUIL77DBx/0ziFkle0=; b=JAZkFfJ7+0JGkIeYyVaeB4LmiW1XmZaU1cmKe9i/k7EtpF4WNVWAe+hmsZtaqwDuuJ cQPTRZ9jeBGZs4CE9oC/1fUOZ1YmuMXCY2KuUaSwPrEK8ogBw27qVe/kMNx6Z0pU8tXE qp+opEdKWZu84NT+UiVddz0MQa8WRKrFDx8pguYw6eC33C64paxkTleeLgmLQpNrOOgV VesmXJwKStxbpeGvktVyD4k10LP2nGwzbMjQc2Z4XRUwooUIjHKQuqfYsHWykeWEdn6W DF2MqLmkcjuiD74Z73OaVUp2vzH/cqxv1o3eEcP5+WocHhYbQ+vR+nQ5MOrN0I8l39eJ NbEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Y9Xga+Vf57beXiQKhYl2BdatYUIL77DBx/0ziFkle0=; b=472h9yx5xlju0QnXL42YU3v0KLknNtbwg09XiOe3LkM+U6QU08CfCDIl3Zj2V2SOWI +vk+dW0ZfvWroU4+bv1n+XbfpaRVMBkc8j/+u3FYpKgKVgQsCQWUuvoh6JW98wHCq13l R3a6FyZBD3765DWY+JMo+q46QYgXE8N3tUhy+B7V2TmNqPr55NR5OxXD8rzF7bTRXPe1 B2qHOWTKP4mARMyHcRADoZ6Eu83OcRwgbaRyH/doJ32W0+Rge0sRzPjGWCmJ1wmpLtv1 CganNAk4wy6abLv+rP/IzAHqd3kRidoh0ttahQIrD5L5FWbozNrHwtboNkk5mIrFpsMa Uq4g== X-Gm-Message-State: AOAM531R7URzv2MpGZP2f/8OeXT1JiCJ2EjdZ/k0AAsWDbiIhJaF9cFN +4EjsMuXd6lVI55tEqbX2rE= X-Google-Smtp-Source: ABdhPJzDlEFinDzLXl/+1GHFwxgQ1sobpE8CWAYcP+aW02BO7FA1aci6p8DesCOcdNqYD9ybZuEBJA== X-Received: by 2002:a17:903:2302:b0:158:cef1:79b9 with SMTP id d2-20020a170903230200b00158cef179b9mr25232476plh.64.1650535861665; Thu, 21 Apr 2022 03:11:01 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:11:00 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 05/10] xtensa: use callx0 opcode in fast_coprocessor Date: Thu, 21 Apr 2022 03:10:28 -0700 Message-Id: <20220421101033.216394-6-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of emulating call0 in fast_coprocessor use that opcode directly. Use 'ret' instead of 'jx a0'. Signed-off-by: Max Filippov --- arch/xtensa/kernel/coprocessor.S | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index c7b9f12896f2..8bcbabbff38a 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -30,7 +30,7 @@ .align 4; \ .Lsave_cp_regs_cp##x: \ xchal_cp##x##_store a2 a3 a4 a5 a6; \ - jx a0; \ + ret; \ .endif =20 #define SAVE_CP_REGS_TAB(x) \ @@ -47,7 +47,7 @@ .align 4; \ .Lload_cp_regs_cp##x: \ xchal_cp##x##_load a2 a3 a4 a5 a6; \ - jx a0; \ + ret; \ .endif =20 #define LOAD_CP_REGS_TAB(x) \ @@ -163,21 +163,20 @@ ENTRY(fast_coprocessor) s32i a5, a4, THREAD_CPENABLE =20 /* - * Get context save area and 'call' save routine.=20 + * Get context save area and call save routine. * (a4 still holds previous owner (thread_info), a3 CP number) */ =20 movi a5, .Lsave_cp_regs_jump_table - movi a0, 2f # a0: 'return' address addx8 a3, a3, a5 # a3: coprocessor number l32i a2, a3, 4 # a2: xtregs offset l32i a3, a3, 0 # a3: jump address add a2, a2, a4 - jx a3 + callx0 a3 =20 /* Note that only a0 and a1 were preserved. */ =20 -2: rsr a3, exccause + rsr a3, exccause addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED movi a0, coprocessor_owner addx4 a0, a3, a0 @@ -187,19 +186,18 @@ ENTRY(fast_coprocessor) 1: GET_THREAD_INFO (a4, a1) s32i a4, a0, 0 =20 - /* Get context save area and 'call' load routine. */ + /* Get context save area and call load routine. */ =20 movi a5, .Lload_cp_regs_jump_table - movi a0, 1f addx8 a3, a3, a5 l32i a2, a3, 4 # a2: xtregs offset l32i a3, a3, 0 # a3: jump address add a2, a2, a4 - jx a3 + callx0 a3 =20 /* Restore all registers and return from exception handler. */ =20 -1: l32i a6, a1, PT_AREG6 + l32i a6, a1, PT_AREG6 l32i a5, a1, PT_AREG5 l32i a4, a1, PT_AREG4 =20 --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36D74C433EF for ; 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Thu, 21 Apr 2022 03:11:02 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 06/10] xtensa: handle coprocessor exceptions in kernel mode Date: Thu, 21 Apr 2022 03:10:29 -0700 Message-Id: <20220421101033.216394-7-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to let drivers use xtensa coprocessors on behalf of the calling process the kernel must handle coprocessor exceptions from the kernel mode the same way as from the user mode. This is not sufficient to allow using coprocessors transparently in IRQ or softirq context. Should such users exist they must be aware of the context and do the right thing, e.g. preserve the coprocessor state and resore it after use. Signed-off-by: Max Filippov --- arch/xtensa/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 95903f25e523..62c497605128 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -69,7 +69,7 @@ static void do_debug(struct pt_regs *regs); #define USER 0x02 =20 #define COPROCESSOR(x) \ -{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER|KRNL, fast_coprocessor } =20 typedef struct { int cause; --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E276C433F5 for ; Thu, 21 Apr 2022 10:11:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388173AbiDUKOh (ORCPT ); Thu, 21 Apr 2022 06:14:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388132AbiDUKNx (ORCPT ); Thu, 21 Apr 2022 06:13:53 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29B111A5 for ; Thu, 21 Apr 2022 03:11:05 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id h12so728838plf.12 for ; Thu, 21 Apr 2022 03:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ncZocJ5Upo0Tlz4v6e6Y6+ABw2qemtuw7eXleVpkeo=; b=GxeC1J4vIS2+nci1FssatJn2cr0PL2yiEEkCFTAXrc6vp/Hdak0blA8sEU7aaUiQZO iY0df4KkxlBC2WdN751BCw+N2+eyltOv4WK0jnbD39oL2OpbAEu6KxN69JZahH7VmJdN k/bg8N2AmEbhcHMv//taWra5dbJC5yHokEa13D0vHBuFbH2KVWyzazzaWPWf75R6hm+q UfWHYxZWC5aNG6WFkhWSgUIlHxeIvBU0OJo3SR5LBeQtjlR/MYTcWnHOajkiCqH4naiR oBC4iVbVs44xhsxoY3b86g3jJUXgsgl6o/ybA0aIIvelm5smPoDF/g2guC5M1h5k3GU7 IN2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ncZocJ5Upo0Tlz4v6e6Y6+ABw2qemtuw7eXleVpkeo=; b=G18XFqvCTUKG7wsujZPCUhHKQvXuKXvTPoH8+04sppPCzd1ATTC/hysRpY9AzJvqZn JZD8sFoJ1pBLHkb639NjgQ+QKv4orAMAbyUWlYt2RngLncdm94n8da+le0tV4YKqTYGa nOcGsrTEip0S3bSiq+1LFeH3cYIYuAKGiYiSCplA38i39G65t8eG+eibGiOGfAbZNDkZ RXif8ZLUBb2hfjHg6WjjbWLsMP2Xt1hZoTfvZHgK9OFe3S47C6hmYnKwjKKDrRUl684S 2Dnvd5/nRZMerVBUcVAWkCuNSMEzFM+enbomeA18Ps/QhVxFAT8Nu0zMb6cVb9+pbBtM 8m8Q== X-Gm-Message-State: AOAM531Zd4ucLLsb++0weaT7Q++JiCQiWzCXWWvYtIULABHgpralzn2R TenfTl2D2q4NBWyKTZjLEVoqX9jluikOMfl9 X-Google-Smtp-Source: ABdhPJw5iQLhLc0cXQJtig5GDsbvs6FR4G2vZL4RO7TETYS+6jdWbG3N3AmwhGxg2lJGYpUToXV/Bw== X-Received: by 2002:a17:902:ab96:b0:159:1ff:4ea0 with SMTP id f22-20020a170902ab9600b0015901ff4ea0mr18414042plr.60.1650535864712; Thu, 21 Apr 2022 03:11:04 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:11:04 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 07/10] xtensa: add xtensa_xsr macro Date: Thu, 21 Apr 2022 03:10:30 -0700 Message-Id: <20220421101033.216394-8-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtensa_xsr does the XSR instruction for the specified special register. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/processor.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/= processor.h index 4489a27d527a..76bc63127c66 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -246,6 +246,13 @@ extern unsigned long __get_wchan(struct task_struct *p= ); v; \ }) =20 +#define xtensa_xsr(x, sr) \ + ({ \ + unsigned int __v__ =3D (unsigned int)(x); \ + __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \ + __v__; \ + }) + #if XCHAL_HAVE_EXTERN_REGS =20 static inline void set_er(unsigned long value, unsigned long addr) --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15358C433F5 for ; Thu, 21 Apr 2022 10:11:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388211AbiDUKOk (ORCPT ); Thu, 21 Apr 2022 06:14:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388131AbiDUKNz (ORCPT ); Thu, 21 Apr 2022 06:13:55 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5A0E1A5 for ; Thu, 21 Apr 2022 03:11:06 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id z6-20020a17090a398600b001cb9fca3210so4750591pjb.1 for ; Thu, 21 Apr 2022 03:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VxZux9BdzX/r+vazMsFAOpjkFd5uZiNaQDWJenis350=; b=LDIF1fzxOKHhl/FoV+IMx/1IhqC/0rv6y6Nhi+tB1GwQUno4ZTj6+fhoWrL2J+EPeR OA11O1oQ1oaSAGBvuVIAvPhIs3Tu3RtWSYp2JkWSvmgEPu6EVD7oMEgl4m9/njZmGI11 syQrMN/zklIA85R/DIQkdbfNprv3/VLNoIR/7ZX0VM/3o+czMt3d99Iqw/7q6OcQV0Sd xnYb994yx5FfsBdtDiXIFaGdjhE9dWbcinTS4eIaB8BTfv8wcS7Bwho7csNkc0GZAO4k HrrnVnciqUaAdPZFO2AeshzxOYpYFsjbFm66gAay2RFuJnL6GdGHV5Wk+uzOjkyUfV7X DZgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VxZux9BdzX/r+vazMsFAOpjkFd5uZiNaQDWJenis350=; b=N1r7ozAZi68/gOHemi/KOiV29j07YiBknjzk0mtG6uT64XBiPiQ6ER8au8611fyuJ+ AbfNgcCMhr4eO+1kCDcN7p0Mq6lZtqVBeFxnQuE3zh+OJdmfmpaJ5mJ78zeePeaKcntL jwrC8cZ23gtbZAxoQCrKtqDrcdwpjDH+WQeeICnluQUPD/sSJI0j+9eUXZO5H5ktql+M vkD17TCNLWBjwfendDuH7zk2k9C9H5g5Cicnox8Cin1QzOmtUxQj49lChbuiM/L0cqoJ vt0OMlGuVrL8X9bxBtHbARt0K/R/SnHUM60Bm4qn4mZ60LDoeIXxLLlVTVMNoIaIaMiI Le1w== X-Gm-Message-State: AOAM532Hr/xw5+7MuBHjEO9381MdTBs1L9dqb+R4XTropAsYYlq0+yMu pwHD6dOtVeBRqf4ssE+NoLtEyPdWgABM0YEI X-Google-Smtp-Source: ABdhPJy7UPcmP1vlczwNIWMgrOXHcllTCABZ2O7TEblNpI50IuDBUx/aqKMbKmcOPPao4NPvdF6W9w== X-Received: by 2002:a17:902:8487:b0:158:f82d:e39e with SMTP id c7-20020a170902848700b00158f82de39emr20126943plo.52.1650535866191; Thu, 21 Apr 2022 03:11:06 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:11:05 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 08/10] xtensa: merge SAVE_CP_REGS_TAB and LOAD_CP_REGS_TAB Date: Thu, 21 Apr 2022 03:10:31 -0700 Message-Id: <20220421101033.216394-9-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Both tables share the same offset field but the different function pointers. Merge them into single table with 3-element entries to reduce code and data duplication. Signed-off-by: Max Filippov --- Changes v1->v2: - new patch arch/xtensa/kernel/coprocessor.S | 85 ++++++++++++++------------------ 1 file changed, 37 insertions(+), 48 deletions(-) diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index 8bcbabbff38a..af11ddaa8c5f 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -33,15 +33,6 @@ ret; \ .endif =20 -#define SAVE_CP_REGS_TAB(x) \ - .if XTENSA_HAVE_COPROCESSOR(x); \ - .long .Lsave_cp_regs_cp##x; \ - .else; \ - .long 0; \ - .endif; \ - .long THREAD_XTREGS_CP##x - - #define LOAD_CP_REGS(x) \ .if XTENSA_HAVE_COPROCESSOR(x); \ .align 4; \ @@ -50,14 +41,19 @@ ret; \ .endif =20 -#define LOAD_CP_REGS_TAB(x) \ +#define CP_REGS_TAB(x) \ .if XTENSA_HAVE_COPROCESSOR(x); \ + .long .Lsave_cp_regs_cp##x; \ .long .Lload_cp_regs_cp##x; \ .else; \ - .long 0; \ + .long 0, 0; \ .endif; \ .long THREAD_XTREGS_CP##x =20 +#define CP_REGS_TAB_SAVE 0 +#define CP_REGS_TAB_LOAD 4 +#define CP_REGS_TAB_OFFSET 8 + __XTENSA_HANDLER =20 SAVE_CP_REGS(0) @@ -79,25 +75,15 @@ LOAD_CP_REGS(7) =20 .align 4 -.Lsave_cp_regs_jump_table: - SAVE_CP_REGS_TAB(0) - SAVE_CP_REGS_TAB(1) - SAVE_CP_REGS_TAB(2) - SAVE_CP_REGS_TAB(3) - SAVE_CP_REGS_TAB(4) - SAVE_CP_REGS_TAB(5) - SAVE_CP_REGS_TAB(6) - SAVE_CP_REGS_TAB(7) - -.Lload_cp_regs_jump_table: - LOAD_CP_REGS_TAB(0) - LOAD_CP_REGS_TAB(1) - LOAD_CP_REGS_TAB(2) - LOAD_CP_REGS_TAB(3) - LOAD_CP_REGS_TAB(4) - LOAD_CP_REGS_TAB(5) - LOAD_CP_REGS_TAB(6) - LOAD_CP_REGS_TAB(7) +.Lcp_regs_jump_table: + CP_REGS_TAB(0) + CP_REGS_TAB(1) + CP_REGS_TAB(2) + CP_REGS_TAB(3) + CP_REGS_TAB(4) + CP_REGS_TAB(5) + CP_REGS_TAB(6) + CP_REGS_TAB(7) =20 /* * Entry condition: @@ -125,13 +111,12 @@ ENTRY(fast_coprocessor) rsr a2, depc s32i a2, a1, PT_AREG2 =20 - /* - * The hal macros require up to 4 temporary registers. We use a3..a6. - */ + /* The hal macros require up to 4 temporary registers. We use a3..a6. */ =20 s32i a4, a1, PT_AREG4 s32i a5, a1, PT_AREG5 s32i a6, a1, PT_AREG6 + s32i a7, a1, PT_AREG7 =20 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ =20 @@ -148,6 +133,12 @@ ENTRY(fast_coprocessor) wsr a0, cpenable rsync =20 + /* Get coprocessor save/load table entry (a7). */ + + movi a7, .Lcp_regs_jump_table + addx8 a7, a3, a7 + addx4 a7, a3, a7 + /* Retrieve previous owner. (a3 still holds CP number) */ =20 movi a0, coprocessor_owner # list of owners @@ -167,10 +158,8 @@ ENTRY(fast_coprocessor) * (a4 still holds previous owner (thread_info), a3 CP number) */ =20 - movi a5, .Lsave_cp_regs_jump_table - addx8 a3, a3, a5 # a3: coprocessor number - l32i a2, a3, 4 # a2: xtregs offset - l32i a3, a3, 0 # a3: jump address + l32i a2, a7, CP_REGS_TAB_OFFSET + l32i a3, a7, CP_REGS_TAB_SAVE add a2, a2, a4 callx0 a3 =20 @@ -188,15 +177,14 @@ ENTRY(fast_coprocessor) =20 /* Get context save area and call load routine. */ =20 - movi a5, .Lload_cp_regs_jump_table - addx8 a3, a3, a5 - l32i a2, a3, 4 # a2: xtregs offset - l32i a3, a3, 0 # a3: jump address + l32i a2, a7, CP_REGS_TAB_OFFSET + l32i a3, a7, CP_REGS_TAB_LOAD add a2, a2, a4 callx0 a3 =20 /* Restore all registers and return from exception handler. */ =20 + l32i a7, a1, PT_AREG7 l32i a6, a1, PT_AREG6 l32i a5, a1, PT_AREG5 l32i a4, a1, PT_AREG4 @@ -232,13 +220,14 @@ ENTRY(coprocessor_flush) abi_entry(4) =20 s32i a0, a1, 0 - movi a0, .Lsave_cp_regs_jump_table - addx8 a3, a3, a0 - l32i a4, a3, 4 - l32i a3, a3, 0 - add a2, a2, a4 - beqz a3, 1f - callx0 a3 + movi a4, .Lcp_regs_jump_table + addx8 a4, a3, a4 + addx4 a3, a3, a4 + l32i a4, a3, CP_REGS_TAB_SAVE + beqz a4, 1f + l32i a3, a3, CP_REGS_TAB_OFFSET + add a2, a2, a3 + callx0 a4 1: l32i a0, a1, 0 =20 abi_ret(4) --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC1AEC433EF for ; Thu, 21 Apr 2022 10:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388231AbiDUKOv (ORCPT ); Thu, 21 Apr 2022 06:14:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388138AbiDUKN5 (ORCPT ); Thu, 21 Apr 2022 06:13:57 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17EBEF6B for ; Thu, 21 Apr 2022 03:11:08 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id bo5so4573216pfb.4 for ; Thu, 21 Apr 2022 03:11:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hdnqgvQUKM2bZrGrKVDmt9RrjK+aAWvXbMuv7vTUtfE=; b=cbo5rNoZILL/PF4xvaUy1JfZC8M8NOp0uxlPNB8cgum7YnNXqEeLQMfcFU6K3fCUKz bI79klpOhBfZS9m6xyE/aZbbiUNtunfi4g1i1+FpRJuAIuwAgAsWgq3I7wBuRHCZeRlf 5SdJZ9YI+dzv1DlZzHG2wJVB7Tpd5s7lYZCg0lvze3MH5cnQ+vj3+gg10MIvMDQmGajH hqwFRVhqUvk/eCxvg3xxZUrgy1EeMT95c7zSHVBOUeCSsglXP9yXTM/sj2xrVbV4OAan 98c8/Q3HdNSmHQE6hC+UwmJGKRWWaE7y4yXkLImH7G97LOETjzfv7063gpRCw3GzMfCm RKHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hdnqgvQUKM2bZrGrKVDmt9RrjK+aAWvXbMuv7vTUtfE=; b=6S8jrZf4CM+i27BVZ4go0ZnfXhWrm+mkxvlTcNtXQXOmmAFGoI9CA3XyEbn479wAuK 2r/7CA3Eq5j9vtwpaBCPE8JEnEqONj+T0iZOd5aVy695rUUMYWlh9dPnhMn2p0/YybuV aGp6SxfI5JWqjBwa3VdiYehnOa1ylyoEH0Bkk/zxwWciCU+rgE/HItTOEIT6smB/RXZ9 sn/hpV+KB7Rs0uDJ6hpDlYW4W2wWmeDWgOoNOMswrRFC59E+YFoabOWcPZtvRjVS7ovu Af/tyDohJJBgj1aQsO3wJ3ugBhi3gXpv43FRkhxFs5URkjoQ2I8KcJIlxIKkzxGs37zW plgg== X-Gm-Message-State: AOAM533o41lEgqs0C7v7Ojaw/dp18nKEIvl0G7hLjCSZGZRQk4/EiAIZ cHOzxrRLFc+p5KBChpuQqy8= X-Google-Smtp-Source: ABdhPJzkJD3TIf9slREdnMuLeJHCgp6CgU05+02Url1Fw+VtyLcJN6X4kVhTTd7i7Xj7SDvObNEzRw== X-Received: by 2002:a63:f147:0:b0:399:2b1f:7aff with SMTP id o7-20020a63f147000000b003992b1f7affmr23531374pgk.341.1650535867681; Thu, 21 Apr 2022 03:11:07 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:11:06 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 09/10] xtensa: get rid of stack frame in coprocessor_flush Date: Thu, 21 Apr 2022 03:10:32 -0700 Message-Id: <20220421101033.216394-10-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" coprocessor_flush is an ordinary function, it can use all registers. Don't reserve stack frame for it and use a7 to preserve a0 around the context saving call. Signed-off-by: Max Filippov --- Changes v1->v2: - new patch arch/xtensa/kernel/coprocessor.S | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index af11ddaa8c5f..95412409c49e 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -216,10 +216,8 @@ ENDPROC(fast_coprocessor) =20 ENTRY(coprocessor_flush) =20 - /* reserve 4 bytes on stack to save a0 */ - abi_entry(4) + abi_entry_default =20 - s32i a0, a1, 0 movi a4, .Lcp_regs_jump_table addx8 a4, a3, a4 addx4 a3, a3, a4 @@ -227,10 +225,11 @@ ENTRY(coprocessor_flush) beqz a4, 1f l32i a3, a3, CP_REGS_TAB_OFFSET add a2, a2, a3 + mov a7, a0 callx0 a4 -1: l32i a0, a1, 0 - - abi_ret(4) + mov a0, a7 +1: + abi_ret_default =20 ENDPROC(coprocessor_flush) =20 --=20 2.30.2 From nobody Sun May 10 23:26:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 078D4C433F5 for ; Thu, 21 Apr 2022 10:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388196AbiDUKOp (ORCPT ); Thu, 21 Apr 2022 06:14:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388148AbiDUKN7 (ORCPT ); Thu, 21 Apr 2022 06:13:59 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F33041A5 for ; Thu, 21 Apr 2022 03:11:09 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id x1so4585114pfj.2 for ; Thu, 21 Apr 2022 03:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sTfshzxRTEMLQRI/J9G1hMPuN37PhOfpR9h2SvwiA7U=; b=fSR+WpWR2pxnicfYIxtyhNCG+5HgYKNAkxNjVaLnUpu1lHUYS20kIsk0iEGaw1VDvU H9YAPpGbuxt+0rJzq1wZXn0BzwrxOBChbpgD+ljl95c9/CN5DJjKEAqD+UNG5InjGyx2 Kri2akuAxVKU9kL+BkjqE0jLOzugXLZ3xhUdUQI6RiJnLot0eGQc1lxGfoh12/dA7BQW te/PNEBLhTkUIEAHiJ7dhA9sn2q+gbmpcHXEbhqQ17oY6aCsJSW+HaSczMCCCfBRqRX8 EuYNGxSoS6O+wWRdwqmrN7TEHRHR3N1MdkB00BzWausdEMlmvgwh/xDxqk5+Zv/B7TRM ZaGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sTfshzxRTEMLQRI/J9G1hMPuN37PhOfpR9h2SvwiA7U=; b=1IvQmCv+PS//PeMuUWHPfTGKVC88LQBDJfL9+JGSMY58USh+kC8eN4b1Qn8mfxRx1h uqmLkaCXpZkXVMYKxiFoxTSVxBRUaLLvjtJur0/E35/eZlF0JIovVDrKcICXXMY2AwOA vm0YDezwuRj8vWhBaXsaVbT3z40tOgrZTWf66w6knwAxgdAKcknWoBYAdqH/8wtvOMdX J58LOJHkLnMEUdfqk1mz74erDwuywCk1WS7i2vwAbNJGf9vIpfMZwoJsGUmcACZ+mNF3 BSv0+07uaPZUAMY8ja7GGKf+NHGfUgIc7oMl9t6FYy/SIEleQAeS0WrhF34djayjJHM/ yJJw== X-Gm-Message-State: AOAM533qN0sQCfThLJvfdvmPjI9X7QIOlaTnlD0bbopb9vyD0RZ7cGyd vKymI/BLaQ6FlWHMMoph1QM= X-Google-Smtp-Source: ABdhPJxPOBfaSmTnfbIRkPCPXCFoT7pTrMdW2VLdXuy4w8kdYZVClGWS715Mpos24ZgSEgg00HqVRA== X-Received: by 2002:a63:1114:0:b0:3aa:30b3:dd5f with SMTP id g20-20020a631114000000b003aa30b3dd5fmr12072366pgl.222.1650535869284; Thu, 21 Apr 2022 03:11:09 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:df13:3d47:8c92:6576]) by smtp.gmail.com with ESMTPSA id w196-20020a6282cd000000b0050ada022940sm2407806pfd.183.2022.04.21.03.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 03:11:08 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH v2 10/10] xtensa: support coprocessors on SMP Date: Thu, 21 Apr 2022 03:10:33 -0700 Message-Id: <20220421101033.216394-11-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220421101033.216394-1-jcmvbkbc@gmail.com> References: <20220421101033.216394-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current coprocessor support on xtensa only works correctly on uniprocessor configurations. Make it work on SMP too and keep it lazy. Make coprocessor_owner array per-CPU and move it to struct exc_table for easy access from the fast_coprocessor exception handler. Allow task to have live coprocessors only on single CPU, record this CPU number in the struct thread_info::cp_owner_cpu. Change struct thread_info::cpenable meaning to be 'coprocessors live on cp_owner_cpu'. Introduce C-level coprocessor exception handler that flushes and releases live coprocessors of the task taking 'coprocessor disabled' exception and call it from the fast_coprocessor handler when the task has live coprocessors on other CPU. Make coprocessor_flush_all and coprocessor_release_all work correctly when called from any CPU by sending IPI to the cp_owner_cpu. Add function coprocessor_flush_release_all to do flush followed by release atomically. Add function local_coprocessors_flush_release_all to flush and release all coprocessors on the local CPU and use it to flush coprocessor contexts from the CPU that goes offline. Signed-off-by: Max Filippov --- Changes v1->v2: - document rules for coprocessor context management - clean up context management from the LKMM point of view, introduce and document barriers - support CPU hotplug arch/xtensa/include/asm/coprocessor.h | 4 +- arch/xtensa/include/asm/thread_info.h | 7 +- arch/xtensa/include/asm/traps.h | 6 ++ arch/xtensa/kernel/asm-offsets.c | 8 +- arch/xtensa/kernel/coprocessor.S | 122 +++++++++++++++++++------- arch/xtensa/kernel/entry.S | 12 ++- arch/xtensa/kernel/process.c | 112 +++++++++++++++++------ arch/xtensa/kernel/ptrace.c | 3 +- arch/xtensa/kernel/signal.c | 3 +- arch/xtensa/kernel/smp.c | 7 ++ arch/xtensa/kernel/traps.c | 13 ++- 11 files changed, 230 insertions(+), 67 deletions(-) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/as= m/coprocessor.h index a360efced7e7..3b1a0d5d2169 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -142,10 +142,12 @@ typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); =20 -extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; +struct thread_info; void coprocessor_flush(struct thread_info *ti, int cp_index); void coprocessor_release_all(struct thread_info *ti); void coprocessor_flush_all(struct thread_info *ti); +void coprocessor_flush_release_all(struct thread_info *ti); +void local_coprocessors_flush_release_all(void); =20 #endif /* XTENSA_HAVE_COPROCESSORS */ =20 diff --git a/arch/xtensa/include/asm/thread_info.h b/arch/xtensa/include/as= m/thread_info.h index f6fcbba1d02f..52974317a6b6 100644 --- a/arch/xtensa/include/asm/thread_info.h +++ b/arch/xtensa/include/asm/thread_info.h @@ -52,12 +52,17 @@ struct thread_info { __u32 cpu; /* current CPU */ __s32 preempt_count; /* 0 =3D> preemptable,< 0 =3D> BUG*/ =20 - unsigned long cpenable; #if XCHAL_HAVE_EXCLUSIVE /* result of the most recent exclusive store */ unsigned long atomctl8; #endif =20 + /* + * If i-th bit is set then coprocessor state is loaded into the + * coprocessor i on CPU cp_owner_cpu. + */ + unsigned long cpenable; + u32 cp_owner_cpu; /* Allocate storage for extra user states and coprocessor states. */ #if XTENSA_HAVE_COPROCESSORS xtregs_coprocessor_t xtregs_cp; diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index 514376eff58c..6f74ccc0c7ea 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -27,6 +27,10 @@ struct exc_table { void *fixup; /* For passing a parameter to fixup */ void *fixup_param; +#if XTENSA_HAVE_COPROCESSORS + /* Pointers to owner struct thread_info */ + struct thread_info *coprocessor_owner[XCHAL_CP_MAX]; +#endif /* Fast user exception handlers */ void *fast_user_handler[EXCCAUSE_N]; /* Fast kernel exception handlers */ @@ -35,6 +39,8 @@ struct exc_table { xtensa_exception_handler *default_handler[EXCCAUSE_N]; }; =20 +DECLARE_PER_CPU(struct exc_table, exc_table); + xtensa_exception_handler * __init trap_set_handler(int cause, xtensa_exception_handler *handler); =20 diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offs= ets.c index 37278e2785fb..e3b9cf4c2289 100644 --- a/arch/xtensa/kernel/asm-offsets.c +++ b/arch/xtensa/kernel/asm-offsets.c @@ -91,10 +91,12 @@ int main(void) /* struct thread_info (offset from start_struct) */ DEFINE(THREAD_RA, offsetof (struct task_struct, thread.ra)); DEFINE(THREAD_SP, offsetof (struct task_struct, thread.sp)); - DEFINE(THREAD_CPENABLE, offsetof (struct thread_info, cpenable)); #if XCHAL_HAVE_EXCLUSIVE DEFINE(THREAD_ATOMCTL8, offsetof (struct thread_info, atomctl8)); #endif + DEFINE(THREAD_CPENABLE, offsetof(struct thread_info, cpenable)); + DEFINE(THREAD_CPU, offsetof(struct thread_info, cpu)); + DEFINE(THREAD_CP_OWNER_CPU, offsetof(struct thread_info, cp_owner_cpu)); #if XTENSA_HAVE_COPROCESSORS DEFINE(THREAD_XTREGS_CP0, offsetof(struct thread_info, xtregs_cp.cp0)); DEFINE(THREAD_XTREGS_CP1, offsetof(struct thread_info, xtregs_cp.cp1)); @@ -137,6 +139,10 @@ int main(void) DEFINE(EXC_TABLE_DOUBLE_SAVE, offsetof(struct exc_table, double_save)); DEFINE(EXC_TABLE_FIXUP, offsetof(struct exc_table, fixup)); DEFINE(EXC_TABLE_PARAM, offsetof(struct exc_table, fixup_param)); +#if XTENSA_HAVE_COPROCESSORS + DEFINE(EXC_TABLE_COPROCESSOR_OWNER, + offsetof(struct exc_table, coprocessor_owner)); +#endif DEFINE(EXC_TABLE_FAST_USER, offsetof(struct exc_table, fast_user_handler)); DEFINE(EXC_TABLE_FAST_KERNEL, diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index 95412409c49e..ef33e76e07d8 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -19,6 +19,26 @@ #include #include =20 +/* + * Rules for coprocessor state manipulation on SMP: + * + * - a task may have live coprocessors only on one CPU. + * + * - whether coprocessor context of task T is live on some CPU is + * denoted by T's thread_info->cpenable. + * + * - non-zero thread_info->cpenable means that thread_info->cp_owner_cpu + * is valid in the T's thread_info. Zero thread_info->cpenable means that + * coprocessor context is valid in the T's thread_info. + * + * - if a coprocessor context of task T is live on CPU X, only CPU X chang= es + * T's thread_info->cpenable, cp_owner_cpu and coprocessor save area. + * This is done by making sure that for the task T with live coprocessor + * on CPU X cpenable SR is 0 when T runs on any other CPU Y. + * When fast_coprocessor exception is taken on CPU Y it goes to the + * C-level do_coprocessor that uses IPI to make CPU X flush T's coproces= sors. + */ + #if XTENSA_HAVE_COPROCESSORS =20 /* @@ -101,9 +121,37 @@ =20 ENTRY(fast_coprocessor) =20 + s32i a3, a2, PT_AREG3 + +#ifdef CONFIG_SMP + /* + * Check if any coprocessor context is live on another CPU + * and if so go through the C-level coprocessor exception handler + * to flush it to memory. + */ + GET_THREAD_INFO (a0, a2) + l32i a3, a0, THREAD_CPENABLE + beqz a3, .Lload_local + + /* + * Pairs with smp_wmb in local_coprocessor_release_all + * and with both memws below. + */ + memw + l32i a3, a0, THREAD_CPU + l32i a0, a0, THREAD_CP_OWNER_CPU + beq a0, a3, .Lload_local + + rsr a0, ps + l32i a3, a2, PT_AREG3 + bbci.l a0, PS_UM_BIT, 1f + call0 user_exception +1: call0 kernel_exception +#endif + /* Save remaining registers a1-a3 and SAR */ =20 - s32i a3, a2, PT_AREG3 +.Lload_local: rsr a3, sar s32i a1, a2, PT_AREG1 s32i a3, a2, PT_SAR @@ -117,6 +165,9 @@ ENTRY(fast_coprocessor) s32i a5, a1, PT_AREG5 s32i a6, a1, PT_AREG6 s32i a7, a1, PT_AREG7 + s32i a8, a1, PT_AREG8 + s32i a9, a1, PT_AREG9 + s32i a10, a1, PT_AREG10 =20 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ =20 @@ -139,51 +190,66 @@ ENTRY(fast_coprocessor) addx8 a7, a3, a7 addx4 a7, a3, a7 =20 - /* Retrieve previous owner. (a3 still holds CP number) */ + /* Retrieve previous owner (a8). */ =20 - movi a0, coprocessor_owner # list of owners + rsr a0, excsave1 # exc_table addx4 a0, a3, a0 # entry for CP - l32i a4, a0, 0 + l32i a8, a0, EXC_TABLE_COPROCESSOR_OWNER =20 - beqz a4, 1f # skip 'save' if no previous owner + /* Set new owner (a9). */ =20 - /* Disable coprocessor for previous owner. (a2 =3D 1 << CP number) */ + GET_THREAD_INFO (a9, a1) + l32i a4, a9, THREAD_CPU + s32i a9, a0, EXC_TABLE_COPROCESSOR_OWNER + s32i a4, a9, THREAD_CP_OWNER_CPU =20 - l32i a5, a4, THREAD_CPENABLE - xor a5, a5, a2 # (1 << cp-id) still in a2 - s32i a5, a4, THREAD_CPENABLE + /* + * Enable coprocessor for the new owner. (a2 =3D 1 << CP number) + * This can be done before loading context into the coprocessor. + */ + l32i a4, a9, THREAD_CPENABLE + or a4, a4, a2 =20 /* - * Get context save area and call save routine. - * (a4 still holds previous owner (thread_info), a3 CP number) + * Make sure THREAD_CP_OWNER_CPU is in memory before updating + * THREAD_CPENABLE */ + memw # (2) + s32i a4, a9, THREAD_CPENABLE =20 - l32i a2, a7, CP_REGS_TAB_OFFSET - l32i a3, a7, CP_REGS_TAB_SAVE - add a2, a2, a4 - callx0 a3 + beqz a8, 1f # skip 'save' if no previous owner =20 - /* Note that only a0 and a1 were preserved. */ + /* Disable coprocessor for previous owner. (a2 =3D 1 << CP number) */ =20 - rsr a3, exccause - addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED - movi a0, coprocessor_owner - addx4 a0, a3, a0 + l32i a10, a8, THREAD_CPENABLE + xor a10, a10, a2 =20 - /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ + /* Get context save area and call save routine. */ =20 -1: GET_THREAD_INFO (a4, a1) - s32i a4, a0, 0 + l32i a2, a7, CP_REGS_TAB_OFFSET + l32i a3, a7, CP_REGS_TAB_SAVE + add a2, a2, a8 + callx0 a3 =20 + /* + * Make sure coprocessor context and THREAD_CP_OWNER_CPU are in memory + * before updating THREAD_CPENABLE + */ + memw # (3) + s32i a10, a8, THREAD_CPENABLE +1: /* Get context save area and call load routine. */ =20 l32i a2, a7, CP_REGS_TAB_OFFSET l32i a3, a7, CP_REGS_TAB_LOAD - add a2, a2, a4 + add a2, a2, a9 callx0 a3 =20 /* Restore all registers and return from exception handler. */ =20 + l32i a10, a1, PT_AREG10 + l32i a9, a1, PT_AREG9 + l32i a8, a1, PT_AREG8 l32i a7, a1, PT_AREG7 l32i a6, a1, PT_AREG6 l32i a5, a1, PT_AREG5 @@ -233,12 +299,4 @@ ENTRY(coprocessor_flush) =20 ENDPROC(coprocessor_flush) =20 - .data - -ENTRY(coprocessor_owner) - - .fill XCHAL_CP_MAX, 4, 0 - -END(coprocessor_owner) - #endif /* XTENSA_HAVE_COPROCESSORS */ diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index f2c789a5a92a..3255d4f61844 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -2071,8 +2071,16 @@ ENTRY(_switch_to) =20 #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS) l32i a3, a5, THREAD_CPENABLE - xsr a3, cpenable - s32i a3, a4, THREAD_CPENABLE +#ifdef CONFIG_SMP + beqz a3, 1f + memw # pairs with memw (2) in fast_coprocessor + l32i a6, a5, THREAD_CP_OWNER_CPU + l32i a7, a5, THREAD_CPU + beq a6, a7, 1f # load 0 into CPENABLE if current CPU is not the owner + movi a3, 0 +1: +#endif + wsr a3, cpenable #endif =20 #if XCHAL_HAVE_EXCLUSIVE diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index e8bfbca5f001..7e38292dd07a 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c @@ -47,6 +47,7 @@ #include #include #include +#include =20 extern void ret_from_fork(void); extern void ret_from_kernel_thread(void); @@ -63,52 +64,114 @@ EXPORT_SYMBOL(__stack_chk_guard); =20 #if XTENSA_HAVE_COPROCESSORS =20 -void coprocessor_release_all(struct thread_info *ti) +void local_coprocessors_flush_release_all(void) { - unsigned long cpenable; - int i; + struct thread_info **coprocessor_owner; + struct thread_info *unique_owner[XCHAL_CP_MAX]; + int n =3D 0; + int i, j; =20 - /* Make sure we don't switch tasks during this operation. */ + coprocessor_owner =3D this_cpu_ptr(&exc_table)->coprocessor_owner; + xtensa_set_sr(XCHAL_CP_MASK, cpenable); =20 - preempt_disable(); + for (i =3D 0; i < XCHAL_CP_MAX; i++) { + struct thread_info *ti =3D coprocessor_owner[i]; =20 - /* Walk through all cp owners and release it for the requested one. */ + if (ti) { + coprocessor_flush(ti, i); =20 - cpenable =3D ti->cpenable; + for (j =3D 0; j < n; j++) + if (unique_owner[j] =3D=3D ti) + break; + if (j =3D=3D n) + unique_owner[n++] =3D ti; =20 - for (i =3D 0; i < XCHAL_CP_MAX; i++) { - if (coprocessor_owner[i] =3D=3D ti) { - coprocessor_owner[i] =3D 0; - cpenable &=3D ~(1 << i); + coprocessor_owner[i] =3D NULL; } } + for (i =3D 0; i < n; i++) { + /* pairs with memw (1) in fast_coprocessor and memw in switch_to */ + smp_wmb(); + unique_owner[i]->cpenable =3D 0; + } + xtensa_set_sr(0, cpenable); +} =20 - ti->cpenable =3D cpenable; +static void local_coprocessor_release_all(void *info) +{ + struct thread_info *ti =3D info; + struct thread_info **coprocessor_owner; + int i; + + coprocessor_owner =3D this_cpu_ptr(&exc_table)->coprocessor_owner; + + /* Walk through all cp owners and release it for the requested one. */ + + for (i =3D 0; i < XCHAL_CP_MAX; i++) { + if (coprocessor_owner[i] =3D=3D ti) + coprocessor_owner[i] =3D NULL; + } + /* pairs with memw (1) in fast_coprocessor and memw in switch_to */ + smp_wmb(); + ti->cpenable =3D 0; if (ti =3D=3D current_thread_info()) xtensa_set_sr(0, cpenable); +} =20 - preempt_enable(); +void coprocessor_release_all(struct thread_info *ti) +{ + if (ti->cpenable) { + /* pairs with memw (2) in fast_coprocessor */ + smp_rmb(); + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_release_all, + ti, true); + } } =20 -void coprocessor_flush_all(struct thread_info *ti) +static void local_coprocessor_flush_all(void *info) { - unsigned long cpenable, old_cpenable; + struct thread_info *ti =3D info; + struct thread_info **coprocessor_owner; + unsigned long old_cpenable; int i; =20 - preempt_disable(); - - old_cpenable =3D xtensa_get_sr(cpenable); - cpenable =3D ti->cpenable; - xtensa_set_sr(cpenable, cpenable); + coprocessor_owner =3D this_cpu_ptr(&exc_table)->coprocessor_owner; + old_cpenable =3D xtensa_xsr(ti->cpenable, cpenable); =20 for (i =3D 0; i < XCHAL_CP_MAX; i++) { - if ((cpenable & 1) !=3D 0 && coprocessor_owner[i] =3D=3D ti) + if (coprocessor_owner[i] =3D=3D ti) coprocessor_flush(ti, i); - cpenable >>=3D 1; } xtensa_set_sr(old_cpenable, cpenable); +} =20 - preempt_enable(); +void coprocessor_flush_all(struct thread_info *ti) +{ + if (ti->cpenable) { + /* pairs with memw (2) in fast_coprocessor */ + smp_rmb(); + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_flush_all, + ti, true); + } +} + +static void local_coprocessor_flush_release_all(void *info) +{ + local_coprocessor_flush_all(info); + local_coprocessor_release_all(info); +} + +void coprocessor_flush_release_all(struct thread_info *ti) +{ + if (ti->cpenable) { + /* pairs with memw (2) in fast_coprocessor */ + smp_rmb(); + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_flush_release_all, + ti, true); + } } =20 #endif @@ -140,8 +203,7 @@ void flush_thread(void) { #if XTENSA_HAVE_COPROCESSORS struct thread_info *ti =3D current_thread_info(); - coprocessor_flush_all(ti); - coprocessor_release_all(ti); + coprocessor_flush_release_all(ti); #endif flush_ptrace_hw_breakpoint(current); } diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c index 323c678a691f..22cdaa6729d3 100644 --- a/arch/xtensa/kernel/ptrace.c +++ b/arch/xtensa/kernel/ptrace.c @@ -171,8 +171,7 @@ static int tie_set(struct task_struct *target, =20 #if XTENSA_HAVE_COPROCESSORS /* Flush all coprocessors before we overwrite them. */ - coprocessor_flush_all(ti); - coprocessor_release_all(ti); + coprocessor_flush_release_all(ti); ti->xtregs_cp.cp0 =3D newregs->cp0; ti->xtregs_cp.cp1 =3D newregs->cp1; ti->xtregs_cp.cp2 =3D newregs->cp2; diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c index 6f68649e86ba..c9ffd42db873 100644 --- a/arch/xtensa/kernel/signal.c +++ b/arch/xtensa/kernel/signal.c @@ -162,8 +162,7 @@ setup_sigcontext(struct rt_sigframe __user *frame, stru= ct pt_regs *regs) return err; =20 #if XTENSA_HAVE_COPROCESSORS - coprocessor_flush_all(ti); - coprocessor_release_all(ti); + coprocessor_flush_release_all(ti); err |=3D __copy_to_user(&frame->xtregs.cp, &ti->xtregs_cp, sizeof (frame->xtregs.cp)); #endif diff --git a/arch/xtensa/kernel/smp.c b/arch/xtensa/kernel/smp.c index ed7c188ebedc..e861ce76ad38 100644 --- a/arch/xtensa/kernel/smp.c +++ b/arch/xtensa/kernel/smp.c @@ -30,6 +30,7 @@ #include =20 #include +#include #include #include #include @@ -273,6 +274,12 @@ int __cpu_disable(void) */ set_cpu_online(cpu, false); =20 +#if XTENSA_HAVE_COPROCESSORS + /* + * Flush coprocessor contexts that are active on the current CPU. + */ + local_coprocessors_flush_release_all(); +#endif /* * OK - migrate IRQs away from this CPU */ diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 62c497605128..138a86fbe9d7 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -57,6 +57,9 @@ static void do_nmi(struct pt_regs *regs); static void do_unaligned_user(struct pt_regs *regs); #endif static void do_multihit(struct pt_regs *regs); +#if XTENSA_HAVE_COPROCESSORS +static void do_coprocessor(struct pt_regs *regs); +#endif static void do_debug(struct pt_regs *regs); =20 /* @@ -69,7 +72,8 @@ static void do_debug(struct pt_regs *regs); #define USER 0x02 =20 #define COPROCESSOR(x) \ -{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER|KRNL, fast_coprocessor } +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER|KRNL, fast_coprocessor },\ +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, 0, do_coprocessor } =20 typedef struct { int cause; @@ -327,6 +331,13 @@ static void do_unaligned_user(struct pt_regs *regs) } #endif =20 +#if XTENSA_HAVE_COPROCESSORS +static void do_coprocessor(struct pt_regs *regs) +{ + coprocessor_flush_release_all(current_thread_info()); +} +#endif + /* Handle debug events. * When CONFIG_HAVE_HW_BREAKPOINT is on this handler is called with * preemption disabled to avoid rescheduling and keep mapping of hardware --=20 2.30.2