From nobody Sun Sep 22 05:31:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2BA3C433EF for ; Thu, 21 Apr 2022 03:51:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1384056AbiDUDyc (ORCPT ); Wed, 20 Apr 2022 23:54:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1384026AbiDUDyN (ORCPT ); Wed, 20 Apr 2022 23:54:13 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 637BBB877; Wed, 20 Apr 2022 20:51:21 -0700 (PDT) X-UUID: a63d77e03b1b46b0b908218653b699d7-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ef3c0007-0422-4d1a-bb1c-ed582f3e78f0,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:ef3c0007-0422-4d1a-bb1c-ed582f3e78f0,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:fbcf6df0-da02-41b4-b6df-58f4ccd36682,C OID:18f69364bfb7,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: a63d77e03b1b46b0b908218653b699d7-20220421 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1896838341; Thu, 21 Apr 2022 11:51:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 21 Apr 2022 11:51:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 11:51:14 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Yong Wu , Allen-KH Cheng Subject: [PATCH 2/4] arm64: dts: mediatek: Get rid of mediatek,larb for MM nodes Date: Thu, 21 Apr 2022 11:51:09 +0800 Message-ID: <20220421035111.7267-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> References: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yong Wu After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ---------------- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------ 2 files changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 848e3f39c8ef..10291b2690ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1010,7 +1010,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,vpu =3D <&vpu>; }; =20 @@ -1021,7 +1020,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb =3D <&larb4>; }; =20 mdp_rsz0: rsz@14003000 { @@ -1051,7 +1049,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WDMA>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb =3D <&larb0>; }; =20 mdp_wrot0: wrot@14007000 { @@ -1060,7 +1057,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WROT0>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb =3D <&larb0>; }; =20 mdp_wrot1: wrot@14008000 { @@ -1069,7 +1065,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WROT1>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb =3D <&larb4>; }; =20 ovl0: ovl@1400c000 { @@ -1079,7 +1074,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_OVL0>; iommus =3D <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; =20 @@ -1090,7 +1084,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_OVL1>; iommus =3D <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; =20 @@ -1101,7 +1094,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 @@ -1112,7 +1104,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; =20 @@ -1123,7 +1114,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA2>; iommus =3D <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0 0x1000>; }; =20 @@ -1134,7 +1124,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_WDMA0>; iommus =3D <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; =20 @@ -1145,7 +1134,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_WDMA1>; iommus =3D <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; =20 @@ -1399,7 +1387,6 @@ <0 0x16027800 0 0x800>, /* VDEC_HWB */ <0 0x16028400 0 0x400>; /* VDEC_HWG */ interrupts =3D ; - mediatek,larb =3D <&larb1>; iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, <&iommu M4U_PORT_HW_VDEC_PP_EXT>, <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, @@ -1467,7 +1454,6 @@ compatible =3D "mediatek,mt8173-vcodec-enc"; reg =3D <0 0x18002000 0 0x1000>; /* VENC_SYS */ interrupts =3D ; - mediatek,larb =3D <&larb3>; iommus =3D <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1495,7 +1481,6 @@ clock-names =3D "jpgdec-smi", "jpgdec"; power-domains =3D <&spm MT8173_POWER_DOMAIN_VENC>; - mediatek,larb =3D <&larb3>; iommus =3D <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; }; @@ -1529,7 +1514,6 @@ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb =3D <&larb5>; mediatek,vpu =3D <&vpu>; clocks =3D <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names =3D "venc_lt_sel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index d1448a0b86cb..be9728526ed3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1396,7 +1396,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL0>; iommus =3D <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; =20 @@ -1407,7 +1406,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; iommus =3D <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; =20 @@ -1418,7 +1416,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL1_2L>; iommus =3D <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; =20 @@ -1429,7 +1426,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <5120>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1441,7 +1437,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <2048>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1598,7 +1593,6 @@ compatible =3D "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg =3D <0 0x17030000 0 0x1000>; interrupts =3D ; - mediatek,larb =3D <&larb4>; iommus =3D <&iommu M4U_PORT_JPGENC_RDMA>, <&iommu M4U_PORT_JPGENC_BSDMA>; power-domains =3D <&spm MT8183_POWER_DOMAIN_VENC>; --=20 2.18.0