From nobody Sun Sep 22 03:39:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AE6FC433F5 for ; Thu, 21 Apr 2022 03:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1384037AbiDUDyR (ORCPT ); Wed, 20 Apr 2022 23:54:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1384024AbiDUDyN (ORCPT ); Wed, 20 Apr 2022 23:54:13 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE186B872; Wed, 20 Apr 2022 20:51:20 -0700 (PDT) X-UUID: 70c9f9118a134c86b17c428359f3fcdb-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:af50ae89-13ea-477c-95bd-dd78c883ff04,OB:20,L OB:20,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham ,ACTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:af50ae89-13ea-477c-95bd-dd78c883ff04,OB:20,LOB :20,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:01d06df0-da02-41b4-b6df-58f4ccd36682,C OID:18f69364bfb7,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: 70c9f9118a134c86b17c428359f3fcdb-20220421 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 913535938; Thu, 21 Apr 2022 11:51:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 11:51:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 11:51:13 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , Chen-Yu Tsai , Ryder Lee , Hui Liu , Yong Wu , Allen-KH Cheng Subject: [PATCH 1/4] arm: dts: mediatek: Get rid of mediatek,larb for MM nodes Date: Thu, 21 Apr 2022 11:51:08 +0800 Message-ID: <20220421035111.7267-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> References: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yong Wu After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Tested-by: Frank Wunderlich # BPI-R2/MT7623 --- arch/arm/boot/dts/mt2701.dtsi | 2 -- arch/arm/boot/dts/mt7623n.dtsi | 5 ----- 2 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 4776f85d6d5b..ef583cfd3baf 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -564,7 +564,6 @@ clock-names =3D "jpgdec-smi", "jpgdec"; power-domains =3D <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb =3D <&larb2>; iommus =3D <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -577,7 +576,6 @@ clocks =3D <&imgsys CLK_IMG_VENC>; clock-names =3D "jpgenc"; power-domains =3D <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb =3D <&larb2>; iommus =3D <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; }; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi index bcb0846e29fd..3adab5cd1fef 100644 --- a/arch/arm/boot/dts/mt7623n.dtsi +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -121,7 +121,6 @@ clock-names =3D "jpgdec-smi", "jpgdec"; power-domains =3D <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb =3D <&larb2>; iommus =3D <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; @@ -144,7 +143,6 @@ interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_OVL>; iommus =3D <&iommu MT2701_M4U_PORT_DISP_OVL_0>; - mediatek,larb =3D <&larb0>; }; =20 rdma0: rdma@14008000 { @@ -154,7 +152,6 @@ interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_RDMA>; iommus =3D <&iommu MT2701_M4U_PORT_DISP_RDMA>; - mediatek,larb =3D <&larb0>; }; =20 wdma@14009000 { @@ -164,7 +161,6 @@ interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_WDMA>; iommus =3D <&iommu MT2701_M4U_PORT_DISP_WDMA>; - mediatek,larb =3D <&larb0>; }; =20 bls: pwm@1400a000 { @@ -215,7 +211,6 @@ interrupts =3D ; clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; iommus =3D <&iommu MT2701_M4U_PORT_DISP_RDMA1>; - mediatek,larb =3D <&larb0>; }; =20 dpi0: dpi@14014000 { --=20 2.18.0 From nobody Sun Sep 22 03:39:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2BA3C433EF for ; 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Thu, 21 Apr 2022 11:51:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 21 Apr 2022 11:51:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 11:51:14 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Yong Wu , Allen-KH Cheng Subject: [PATCH 2/4] arm64: dts: mediatek: Get rid of mediatek,larb for MM nodes Date: Thu, 21 Apr 2022 11:51:09 +0800 Message-ID: <20220421035111.7267-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> References: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yong Wu After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ---------------- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------ 2 files changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 848e3f39c8ef..10291b2690ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1010,7 +1010,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,vpu =3D <&vpu>; }; =20 @@ -1021,7 +1020,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb =3D <&larb4>; }; =20 mdp_rsz0: rsz@14003000 { @@ -1051,7 +1049,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WDMA>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb =3D <&larb0>; }; =20 mdp_wrot0: wrot@14007000 { @@ -1060,7 +1057,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WROT0>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb =3D <&larb0>; }; =20 mdp_wrot1: wrot@14008000 { @@ -1069,7 +1065,6 @@ clocks =3D <&mmsys CLK_MM_MDP_WROT1>; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; iommus =3D <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb =3D <&larb4>; }; =20 ovl0: ovl@1400c000 { @@ -1079,7 +1074,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_OVL0>; iommus =3D <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; =20 @@ -1090,7 +1084,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_OVL1>; iommus =3D <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; =20 @@ -1101,7 +1094,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; =20 @@ -1112,7 +1104,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; =20 @@ -1123,7 +1114,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_RDMA2>; iommus =3D <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0 0x1000>; }; =20 @@ -1134,7 +1124,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_WDMA0>; iommus =3D <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; =20 @@ -1145,7 +1134,6 @@ power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DISP_WDMA1>; iommus =3D <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb =3D <&larb4>; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; =20 @@ -1399,7 +1387,6 @@ <0 0x16027800 0 0x800>, /* VDEC_HWB */ <0 0x16028400 0 0x400>; /* VDEC_HWG */ interrupts =3D ; - mediatek,larb =3D <&larb1>; iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, <&iommu M4U_PORT_HW_VDEC_PP_EXT>, <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, @@ -1467,7 +1454,6 @@ compatible =3D "mediatek,mt8173-vcodec-enc"; reg =3D <0 0x18002000 0 0x1000>; /* VENC_SYS */ interrupts =3D ; - mediatek,larb =3D <&larb3>; iommus =3D <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1495,7 +1481,6 @@ clock-names =3D "jpgdec-smi", "jpgdec"; power-domains =3D <&spm MT8173_POWER_DOMAIN_VENC>; - mediatek,larb =3D <&larb3>; iommus =3D <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; }; @@ -1529,7 +1514,6 @@ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb =3D <&larb5>; mediatek,vpu =3D <&vpu>; clocks =3D <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names =3D "venc_lt_sel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index d1448a0b86cb..be9728526ed3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1396,7 +1396,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL0>; iommus =3D <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; =20 @@ -1407,7 +1406,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; iommus =3D <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; =20 @@ -1418,7 +1416,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_OVL1_2L>; iommus =3D <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; - mediatek,larb =3D <&larb0>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; =20 @@ -1429,7 +1426,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <5120>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1441,7 +1437,6 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb =3D <&larb0>; mediatek,rdma-fifo-size =3D <2048>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1598,7 +1593,6 @@ compatible =3D "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg =3D <0 0x17030000 0 0x1000>; interrupts =3D ; - mediatek,larb =3D <&larb4>; iommus =3D <&iommu M4U_PORT_JPGENC_RDMA>, <&iommu M4U_PORT_JPGENC_BSDMA>; power-domains =3D <&spm MT8183_POWER_DOMAIN_VENC>; --=20 2.18.0 From nobody Sun Sep 22 03:39:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E235EC433F5 for ; Thu, 21 Apr 2022 03:51:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1384045AbiDUDy1 (ORCPT ); Wed, 20 Apr 2022 23:54:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1384025AbiDUDyN (ORCPT ); Wed, 20 Apr 2022 23:54:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67C87B871; Wed, 20 Apr 2022 20:51:23 -0700 (PDT) X-UUID: 33b64b9f6c7448ecafc91beaa82aefa4-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ca88c13c-5520-49e6-86fe-da02fe37694c,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:52d06df0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 33b64b9f6c7448ecafc91beaa82aefa4-20220421 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1035111916; Thu, 21 Apr 2022 11:51:17 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 21 Apr 2022 11:51:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 11:51:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 11:51:15 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Allen-KH Cheng , "Irui Wang" Subject: [PATCH 3/4] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes Date: Thu, 21 Apr 2022 11:51:10 +0800 Message-ID: <20220421035111.7267-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> References: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The power of encoder is not control by mediatek,larb, so we add power domain to encoder nodes for mt8173 SoC. Signed-off-by: Irui Wang Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 10291b2690ab..eebc2d074254 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1470,6 +1470,7 @@ clock-names =3D "venc_sel"; assigned-clocks =3D <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_VCODECPLL>; + power-domains =3D <&scpsys MT8173_POWER_DOMAIN_VENC>; }; =20 jpegdec: jpegdec@18004000 { @@ -1520,6 +1521,7 @@ assigned-clocks =3D <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains =3D <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; }; }; --=20 2.18.0 From nobody Sun Sep 22 03:39:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBF41C433EF for ; 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Thu, 21 Apr 2022 11:51:19 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 11:51:17 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 11:51:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 11:51:17 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , Hui Liu , Irui Wang , Allen-KH Cheng Subject: [PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property Date: Thu, 21 Apr 2022 11:51:11 +0800 Message-ID: <20220421035111.7267-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> References: <20220421035111.7267-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irui Wang Add encoder power domain property Signed-off-by: Irui Wang Signed-off-by: Allen-KH Cheng Reviewed-by: Matthias Brugger --- .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index e7b65a91c92c..de2df6c6352c 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -41,6 +41,9 @@ properties: =20 assigned-clock-parents: true =20 + power-domains: + maxItems: 1 + iommus: minItems: 1 maxItems: 32 @@ -74,6 +77,7 @@ required: - iommus - assigned-clocks - assigned-clock-parents + - power-domains =20 allOf: - if: @@ -135,6 +139,7 @@ examples: #include #include #include + #include =20 vcodec_enc_avc: vcodec@18002000 { compatible =3D "mediatek,mt8173-vcodec-enc"; @@ -156,6 +161,7 @@ examples: clock-names =3D "venc_sel"; assigned-clocks =3D <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_VCODECPLL>; + power-domains =3D <&scpsys MT8173_POWER_DOMAIN_VENC>; }; =20 vcodec_enc_vp8: vcodec@19002000 { @@ -176,4 +182,5 @@ examples: clock-names =3D "venc_lt_sel"; assigned-clocks =3D <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents =3D <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains =3D <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; --=20 2.18.0