From nobody Mon May 11 00:12:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E82ABC433EF for ; Wed, 20 Apr 2022 14:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379576AbiDTOTf (ORCPT ); Wed, 20 Apr 2022 10:19:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380274AbiDTOSr (ORCPT ); Wed, 20 Apr 2022 10:18:47 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56AF143AD9 for ; Wed, 20 Apr 2022 07:16:01 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id m14so2472455wrb.6 for ; Wed, 20 Apr 2022 07:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=buTOea5hGyKVMycb2UNLHy/CmUKsfopnU76jMCLf+w0=; b=DiPpygcsv1FE9XrikGyg1icYH8Svlo4wHN7c1tle/5MzbK5V7gZZJq5zEs1zm+Tr0m hbQ7xTlZD3c3aGUWxVlvLu5rAiJ4fk64EfvWmQNbi2CZyH/3Eoq4iWQGbzXnWCaNJoUY vLauIkmYNo/D2ewIjUpwRwG4OF3kyDl7X8CP4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=buTOea5hGyKVMycb2UNLHy/CmUKsfopnU76jMCLf+w0=; b=hu/i2hzmby9gdI6E6RauCi1ukY6WTQsIOF9U9bKq0vxOtHN+U9DTsLpNsCJgP5Hc1V 0eRZ/yFFhAjo5t9Fv3lJ3/qUhJRinf4mx/vu5pmlTWDqo/5FctJ6VDnd86FsmoJVBFAX Lx5Zt+zT9swpCwPiVst0tKO8Z+8dD+nMcqO5ioiDGhvDmRN6lSj0dy9H9x6s7mKd/vOY EvEg/lizDHtE2vDsnwLkrCGKH3BDdYI7TFBtQlTAwCFUAP85zu5N8rBvLf1bYKeHw0ZI K/MP4QmmaDjyBcqj5CA3uP5ouX7wmiGx5JKWZ7evZXuKN6RxzcSYWGQg+Oa8gqy/mYU9 OAqw== X-Gm-Message-State: AOAM532cA4mOY4UGbmhCTa3gOFQxv7ixaPUvoBANCaAwAjXaXyAKM/6P RAsWWgBSeOtYch9l0VFM9cH0Eg== X-Google-Smtp-Source: ABdhPJyYIA6x9+f8e47TwQBEyU5CfA6Jc7fDHnsVuiVEE4Gn+yDN22VKV/egJHJ1ZcL3RtVt3ILCkg== X-Received: by 2002:a5d:6e85:0:b0:207:a435:d9a7 with SMTP id k5-20020a5d6e85000000b00207a435d9a7mr15785389wrz.217.1650464159946; Wed, 20 Apr 2022 07:15:59 -0700 (PDT) Received: from localhost.localdomain ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id v2-20020adf8b42000000b0020aa790a258sm12447wra.8.2022.04.20.07.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 07:15:59 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri , Rob Herring Subject: [PATCH v5 1/4] dt-bindings: add mfd/cros_ec definitions Date: Wed, 20 Apr 2022 14:15:53 +0000 Message-Id: <20220420141556.681212-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220420141556.681212-1-fabiobaltieri@chromium.org> References: <20220420141556.681212-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri Acked-by: Rob Herring --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cr= os_ec.h new file mode 100644 index 000000000000..3b29cd049578 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif --=20 2.36.0.rc0.470.gd361397f0d-goog From nobody Mon May 11 00:12:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93852C433EF for ; Wed, 20 Apr 2022 14:16:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379488AbiDTOTW (ORCPT ); Wed, 20 Apr 2022 10:19:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380283AbiDTOSt (ORCPT ); Wed, 20 Apr 2022 10:18:49 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9B943AE9 for ; Wed, 20 Apr 2022 07:16:02 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id r187-20020a1c44c4000000b0038ccb70e239so3785363wma.3 for ; Wed, 20 Apr 2022 07:16:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ObecURUna9Qwp1jlmemsZMBt2OPXmb3XIGOTXF8U8Dg=; b=lWkesEjNpEMRFzzmw5mznQmKLYgm0N2fxvFB59LDEX0uBuR4/Y0Y1AdPMcarWTboXw ZXNkCHP3VPUQFHaGIfKKRO+c+s/Nab6N0jjv4hI6vERXlzjp5JShhl43S0xetpflEO7z llsRZBfwYDZuadM9j1syMMUBLT8ohr809s84Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ObecURUna9Qwp1jlmemsZMBt2OPXmb3XIGOTXF8U8Dg=; b=yFGgZ7vNuAoAmF7no3LNZP72OEhSiNjEA146pjlk/MRL1Zx7nqF6I8O9OenqO0Qyba 8TCRugpnbkQolSf6h3Q7V7kl982RWzO1KaGtpaPiRtwXrL8EwiFJNEa3VdVc72f/jIL6 cEsvpkRFRsZIytsVlxZ+iWDTpa84YoU5SGELyfk6BjnbbC4rfRudYl1t8SfC6/gjkn9h v7p3NsyCrwusdjAgyV7G0u1cK3pISOjwekwqUgc+aBbn64h/rkMG4ODSeQ2rLLM6bk8D ClJ5Gy6MKdR7MXiBpZ97yekK1LSbvVpLJXBzkeUHdvtxS8LN6gSZa3V62ShaGEe5W0HG ncLg== X-Gm-Message-State: AOAM531gbAtjzSoI2CHy1Jzc5hT4SQb0iGANJ7yn89VZ7ohYq8XYIZ1c JsvUA7/8A+IfwxVq3hnK+Wuspg== X-Google-Smtp-Source: ABdhPJzI3RZrAS55TPGVfRyM82Jjk72vfI9ZUmQqB6WLQLVpiVXgPr1Z9oTCCSf2Eehukff/l2jVlw== X-Received: by 2002:a05:600c:5025:b0:38f:f782:253c with SMTP id n37-20020a05600c502500b0038ff782253cmr4089853wmr.42.1650464160897; Wed, 20 Apr 2022 07:16:00 -0700 (PDT) Received: from localhost.localdomain ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id v2-20020adf8b42000000b0020aa790a258sm12447wra.8.2022.04.20.07.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 07:16:00 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri , Tzung-Bi Shih Subject: [PATCH v5 2/4] pwm: pwm-cros-ec: add channel type support Date: Wed, 20 Apr 2022 14:15:54 +0000 Message-Id: <20220420141556.681212-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220420141556.681212-1-fabiobaltieri@chromium.org> References: <20220420141556.681212-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. To use it, define the node with the "google,cros-ec-pwm-type" compatible. Signed-off-by: Fabio Baltieri Reviewed-by: Tzung-Bi Shih --- drivers/pwm/pwm-cros-ec.c | 82 ++++++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..7f10f56c3eb6 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -12,17 +12,21 @@ #include #include =20 +#include + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; =20 /** @@ -58,14 +62,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, str= uct pwm_device *pwm) kfree(channel); } =20 -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 d= uty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type =3D EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type =3D EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x, + u16 duty) +{ + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params =3D &buf.params; struct cros_ec_command *msg =3D &buf.msg; + int ret; =20 memset(&buf, 0, sizeof(buf)); =20 @@ -75,14 +96,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *= ec, u8 index, u16 duty) msg->outsize =3D sizeof(*params); =20 params->duty =3D duty; - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 return cros_ec_cmd_xfer_status(ec, msg); } =20 -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x) { + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +134,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device = *ec, u8 index) msg->insize =3D sizeof(*resp); msg->outsize =3D sizeof(*params); =20 - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 ret =3D cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +174,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, */ duty_cycle =3D state->enabled ? state->duty_cycle : 0; =20 - ret =3D cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret =3D cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; =20 @@ -149,7 +190,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip= , struct pwm_device *pwm, struct cros_ec_pwm *channel =3D pwm_get_chip_data(pwm); int ret; =20 - ret =3D cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret =3D cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +245,13 @@ static const struct pwm_ops cros_ec_pwm_ops =3D { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; =20 /* The index field is only 8 bits */ for (i =3D 0; i <=3D U8_MAX; i++) { - ret =3D cros_ec_pwm_get_duty(ec, i); + ret =3D cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -236,6 +277,7 @@ static int cros_ec_pwm_probe(struct platform_device *pd= ev) { struct cros_ec_device *ec =3D dev_get_drvdata(pdev->dev.parent); struct device *dev =3D &pdev->dev; + struct device_node *np =3D pdev->dev.of_node; struct cros_ec_pwm_device *ec_pwm; struct pwm_chip *chip; int ret; @@ -251,17 +293,26 @@ static int cros_ec_pwm_probe(struct platform_device *= pdev) chip =3D &ec_pwm->chip; ec_pwm->ec =3D ec; =20 + if (of_device_is_compatible(np, "google,cros-ec-pwm-type")) + ec_pwm->use_pwm_type =3D true; + /* PWM chip */ chip->dev =3D dev; chip->ops =3D &cros_ec_pwm_ops; chip->of_xlate =3D cros_ec_pwm_xlate; chip->of_pwm_n_cells =3D 1; - ret =3D cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm =3D CROS_EC_PWM_DT_COUNT; + } else { + ret =3D cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm =3D ret; } - chip->npwm =3D ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); =20 ret =3D pwmchip_add(chip); @@ -288,6 +339,7 @@ static int cros_ec_pwm_remove(struct platform_device *d= ev) #ifdef CONFIG_OF static const struct of_device_id cros_ec_pwm_of_match[] =3D { { .compatible =3D "google,cros-ec-pwm" }, + { .compatible =3D "google,cros-ec-pwm-type" }, {}, }; MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match); --=20 2.36.0.rc0.470.gd361397f0d-goog From nobody Mon May 11 00:12:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F232C433EF for ; Wed, 20 Apr 2022 14:17:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379521AbiDTOUB (ORCPT ); Wed, 20 Apr 2022 10:20:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380288AbiDTOSt (ORCPT ); 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charset="utf-8" Update google,cros-ec-pwm node documentation to mention the google,cros-ec-pwm-type compatible. Signed-off-by: Fabio Baltieri Reviewed-by: Rob Herring --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml = b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 7ab6912a845f..c8577bdf6c94 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -21,7 +21,14 @@ allOf: =20 properties: compatible: - const: google,cros-ec-pwm + oneOf: + - description: PWM controlled using EC_PWM_TYPE_GENERIC channels. + items: + - const: google,cros-ec-pwm + - description: PWM controlled using CROS_EC_PWM_DT_<...> types. + items: + - const: google,cros-ec-pwm-type + "#pwm-cells": description: The cell specifies the PWM index. const: 1 --=20 2.36.0.rc0.470.gd361397f0d-goog From nobody Mon May 11 00:12:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A26C433EF for ; Wed, 20 Apr 2022 14:17:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379616AbiDTOUF (ORCPT ); Wed, 20 Apr 2022 10:20:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380301AbiDTOSw (ORCPT ); Wed, 20 Apr 2022 10:18:52 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F24143AF9 for ; Wed, 20 Apr 2022 07:16:04 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id r19so1322293wmq.0 for ; Wed, 20 Apr 2022 07:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FLizgiXQLrW5SUcbtl0qfCotKUJR31MdMgF2e9s6lCM=; b=ectEvWIV+fIfEL1pyh3xzpGE0k7tOMbXwfGGDW0DZvUXuJu8MOP1VfHYCz0ohZLI9e in2Mcm40Ui//UUDs/nrPf1jDRn+4uJodFCmhj7uRmCIhBp0yTP8PpsHa1dW3/NiZVQo2 7bxCh8CkXW2edDkOef5lt2fpYBQCYQfDGQYFU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FLizgiXQLrW5SUcbtl0qfCotKUJR31MdMgF2e9s6lCM=; b=rAx2I/d7PGhDK8oJdwjoFZB/OaEsIgBpMSk3u6KXsvFWXsJVe8M0wYlixA+nuF/XNH oht6ZK4Jdtw8T9uHrAZCRxS1IU5004Lf/2zqODG7bxm88lyBXauI8rTiS0rc2D84neGL YeLj2Y3ylG3AWB8BxY5yaAj8G1WxAcnB2mfIJS62g4nHCBFVoDJDuBNyJBZre7E0eciX v6btevD+iSuFXpGRM51j7vZVS95pMb5RiAymMFnoLU3Hnmuoj3qCVAQwrb643jP/wQR1 B952FYbXkKn5gB+j67oumJ0e9LwvbuIg0G/veGHSvJcoQSYHZJMZzbQxbub/a4Eev/Z6 Jwxg== X-Gm-Message-State: AOAM5321UcSrsbRHptiZv2sQxq48q5vzlCgpjrLl6gdCi782/4Y50XWo HNZE5etFLfYg2pz452Nx2mQUoYDWyiBR2w== X-Google-Smtp-Source: ABdhPJwHS1696wqCHNU4Knr6WjQDukTMz1A8s013IPivyfP6mm0oqrA+CVruAezjYYdwAeNoWggNxg== X-Received: by 2002:a05:600c:4f88:b0:391:e34e:ca66 with SMTP id n8-20020a05600c4f8800b00391e34eca66mr3939836wmq.16.1650464162954; Wed, 20 Apr 2022 07:16:02 -0700 (PDT) Received: from localhost.localdomain ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id v2-20020adf8b42000000b0020aa790a258sm12447wra.8.2022.04.20.07.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 07:16:02 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v5 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Wed, 20 Apr 2022 14:15:56 +0000 Message-Id: <20220420141556.681212-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220420141556.681212-1-fabiobaltieri@chromium.org> References: <20220420141556.681212-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 +++++---- .../boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 7 ++++--- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 5 +++-- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 13 files changed, 28 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.= dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible =3D "pwm-leds"; keyboard_backlight: keyboard-backlight { label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; }; =20 -&cros_ec_pwm { +&cros_ec_pwm_type { status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/= arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..8474bd3af6eb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,8 +92,8 @@ volume_up { }; =20 &cros_ec { - cros_ec_pwm: ec-pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: ec-pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..aea7c66d95e0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status =3D "okay"; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &camcc { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..6552e0025f84 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include =20 @@ -316,7 +317,7 @@ backlight: backlight { num-interpolated-steps =3D <64>; default-brightness-level =3D <951>; =20 - pwms =3D <&cros_ec_pwm 1>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -354,7 +355,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -637,8 +638,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 1779d96c30f6..628ef990433b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include #include =20 @@ -336,7 +337,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -705,8 +706,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..eb4b0e17adec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ =20 #include #include +#include =20 #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -288,7 +289,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -421,8 +422,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index a7c346aa3b02..a797f09e1328 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,8 +20,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..a57951a50cd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include "sdm845.dtsi" =20 @@ -27,7 +28,7 @@ chosen { =20 backlight: backlight { compatible =3D "pwm-backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -708,8 +709,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/b= oot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature =3D <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch= /arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..28eda361dfe1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply =3D <&pp3300_disp>; pinctrl-names =3D "default"; pinctrl-0 =3D <&bl_en>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us =3D <10000>; }; =20 @@ -462,8 +463,8 @@ ap_i2c_tp: &i2c5 { }; =20 &cros_ec { - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64= /boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names =3D "default"; pinctrl-0 =3D <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi" =20 --=20 2.36.0.rc0.470.gd361397f0d-goog