From nobody Sun Sep 22 07:36:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15E3DC433EF for ; Wed, 20 Apr 2022 13:06:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378858AbiDTNJL (ORCPT ); Wed, 20 Apr 2022 09:09:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378832AbiDTNIr (ORCPT ); Wed, 20 Apr 2022 09:08:47 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75DC8427D6; Wed, 20 Apr 2022 06:05:47 -0700 (PDT) X-UUID: 1b40d179d0b746478f4e4c7697dcf631-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:40768c13-a39f-47a0-8041-f46edf4739bf,OB:-327 68,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-20 X-CID-INFO: VERSION:1.1.4,REQID:40768c13-a39f-47a0-8041-f46edf4739bf,OB:-32768 ,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:f4e55cf0-da02-41b4-b6df-58f4ccd36682,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 1b40d179d0b746478f4e4c7697dcf631-20220420 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1112856766; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Date: Wed, 20 Apr 2022 21:05:17 +0800 Message-ID: <20220420130527.23200-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are two version for clock reset register control of MediaTek SoCs. The reset operations before MT8183 can use simple reset to cover. Therefore, we replace mtk_reset_ops with reset_simple_ops. In addition, we also rename mtk_register_reset_controller to mtk_register_reset_controller_simple. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/Kconfig | 1 + drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +-- drivers/clk/mediatek/clk-mt2712.c | 4 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-- drivers/clk/mediatek/clk-mt7622.c | 4 +-- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-- drivers/clk/mediatek/clk-mt8135.c | 4 +-- drivers/clk/mediatek/clk-mt8173.c | 4 +-- drivers/clk/mediatek/clk-mtk.h | 6 ++-- drivers/clk/mediatek/reset.c | 43 +++------------------------ 15 files changed, 27 insertions(+), 61 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 01ef02c54725..df2cdaa975e4 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -8,6 +8,7 @@ menu "Clock driver for MediaTek SoC" config COMMON_CLK_MEDIATEK tristate select RESET_CONTROLLER + select RESET_SIMPLE help MediaTek SoCs' clock support. =20 diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index 100ff6ca609e..1a6318fbcb32 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *p= dev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 1328c112a38f..0cd6b57657b3 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0xc); + mtk_register_reset_controller_simple(node, 1, 0xc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index 61444881c539..883a23bb024d 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *p= dev) return r; } =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 1eb3e4563c3f..3f6508ff8e7f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); =20 return 0; } @@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) if (r) return r; =20 - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_simple(node, 2, 0x0); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index ff72b9ab945b..9b4470ac7be7 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_dev= ice *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); =20 return r; } @@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_devi= ce *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index c9947dc7ba5a..647bf752a8af 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 628be0c9f888..1287db1e3cc2 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 0e1fb30a1e98..2b744afd9233 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, 1, 0x30); + mtk_register_reset_controller_simple(node, 1, 0x30); =20 return 0; } @@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) =20 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); =20 - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_simple(node, 2, 0x0); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index 88279d0ea1a7..0fb5780ae048 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 5c5b37207afb..6f7d013814ac 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 09ad272d51f1..476c6fb5fc5d 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node= *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init= ); =20 @@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); =20 diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index 46b7655feeaa..92beb45de8a0 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node= *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init= ); =20 @@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); =20 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..f767c9585d8c 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -190,11 +190,11 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_d= ata); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); =20 -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); +void mtk_register_reset_controller_simple(struct device_node *np, + unsigned int num_regs, int regofs); =20 void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); + unsigned int num_regs, int regofs); =20 struct mtk_clk_desc { const struct mtk_gate *clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 834d26e9bdfd..9110d0b4229f 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "clk-mtk.h" @@ -37,36 +38,6 @@ static int mtk_reset_deassert_set_clr(struct reset_contr= oller_dev *rcdev, return regmap_write(data->regmap, reg, BIT(id % 32)); } =20 -static int mtk_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct mtk_reset *data =3D container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), ~0); -} - -static int mtk_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct mtk_reset *data =3D container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), 0); -} - -static int mtk_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - int ret; - - ret =3D mtk_reset_assert(rcdev, id); - if (ret) - return ret; - - return mtk_reset_deassert(rcdev, id); -} - static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, unsigned long id) { @@ -78,12 +49,6 @@ static int mtk_reset_set_clr(struct reset_controller_dev= *rcdev, return mtk_reset_deassert_set_clr(rcdev, id); } =20 -static const struct reset_control_ops mtk_reset_ops =3D { - .assert =3D mtk_reset_assert, - .deassert =3D mtk_reset_deassert, - .reset =3D mtk_reset, -}; - static const struct reset_control_ops mtk_reset_ops_set_clr =3D { .assert =3D mtk_reset_assert_set_clr, .deassert =3D mtk_reset_deassert_set_clr, @@ -123,18 +88,18 @@ static void mtk_register_reset_controller_common(struc= t device_node *np, } } =20 -void mtk_register_reset_controller(struct device_node *np, +void mtk_register_reset_controller_simple(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops); + &reset_simple_ops); } =20 void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); + &mtk_reset_ops_set_clr); } =20 MODULE_LICENSE("GPL"); --=20 2.18.0