From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60661C433F5 for ; Wed, 20 Apr 2022 10:35:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352295AbiDTKhZ (ORCPT ); Wed, 20 Apr 2022 06:37:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352168AbiDTKhT (ORCPT ); Wed, 20 Apr 2022 06:37:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E4173FBD5 for ; Wed, 20 Apr 2022 03:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450874; x=1681986874; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KdL05nOBJPGL4QzjOb2cpc6owjSkTlqs6bWZgqhrLhw=; b=ppjwVIeIho8AUmkU91rkO9u4Hg7eXqysMe2P3oHsYAbRHhSLcpyzDUez xURVQmnfX7jlPiDzoObVFsUDFb400DmKzyezpgxGzmgDZWK+HIhemTgxH yHJaiBvWaHAUCkMFIBr+2R6x7k3RS417sMFw9JWPxVpkF4jRh0SfIAqhA w0gKp4f3S1wrA3BGhGAfO8Coci7X6WJftnikb+ANPeUWca0eTbq26SUjD HsrIzWloHJeKuCedEL1zNZbHXjvVag7n1YDjzI6nt4qf35vYUWdQbdyAU mX3BtSGuQb7YHjhrkhJ2uoFKLVBq+VXfvUmt5I6xndMviSRTbpMxXrUvN w==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091268" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:33 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:31 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 01/11] mtd: spi-nor: Rename method, s/spi_nor_match_id/spi_nor_match_name Date: Wed, 20 Apr 2022 13:34:17 +0300 Message-ID: <20220420103427.47867-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The method is matching a flash_info entry by searching by name. Rename the method for better clarity. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b4f141ad9c9c..214d3a1ac6b0 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2876,8 +2876,8 @@ void spi_nor_restore(struct spi_nor *nor) } EXPORT_SYMBOL_GPL(spi_nor_restore); =20 -static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, - const char *name) +static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, + const char *name) { unsigned int i, j; =20 @@ -2899,7 +2899,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, const struct flash_info *info =3D NULL; =20 if (name) - info =3D spi_nor_match_id(nor, name); + info =3D spi_nor_match_name(nor, name); /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) info =3D spi_nor_read_id(nor); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5728C433F5 for ; Wed, 20 Apr 2022 10:35:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377714AbiDTKhw (ORCPT ); Wed, 20 Apr 2022 06:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352261AbiDTKhW (ORCPT ); Wed, 20 Apr 2022 06:37:22 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E75913FBD3 for ; Wed, 20 Apr 2022 03:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450876; x=1681986876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4wzFQsZmZ98FaEgGawwjLvUzNU/hfRAMoTc4fQNV+FA=; b=ehEK/rAoMiHetC82WEAfGtqwakwBth1bCifIEyiz4nEYqJX05M97ac93 rR7mgXy2RnD2pgMFYSwBSf4f1NgeNjC0DzkTSFQXhgpnMkuNWBzQUIILe PAkbgqOhCjM3co8k3H7BQ+v3v21I4m8asWs39hSs78QoAJqyFgxbl8VB1 GsUSQ4gA/fbAyLBSaTun//fvvFIBHBBl1MxdX3i+VQCv4Tf5ORDEXIdQL KtLAgvOBmZJoFzF9vEd6m9E4i/j4jd1l/m3bRlaLVJDK3+OpcWBNPoEWH UyQU9/Wm5JSM1NLPldOQFVhsDG/gwE5EL+B227K8Y6kGL6xPNYoS1UlNg Q==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091280" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:36 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:35 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:33 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 02/11] mtd: spi-nor: Introduce spi_nor_match_id() Date: Wed, 20 Apr 2022 13:34:18 +0300 Message-ID: <20220420103427.47867-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Similar to spi_nor_match_name() extend the search of flash_info through all the manufacturers, this time doing the match by ID. There's no reason to limit the search per manufacturer yet, do it globally, search the flash in all the parts of all manufacturers in a single method. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 40 ++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 214d3a1ac6b0..b9cc8bbf1f62 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1629,16 +1629,21 @@ static const struct spi_nor_manufacturer *manufactu= rers[] =3D { &spi_nor_xmc, }; =20 -static const struct flash_info * -spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int npa= rts, - const u8 *id) +static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, + const u8 *id) { - unsigned int i; + const struct flash_info *part; + unsigned int i, j; =20 - for (i =3D 0; i < nparts; i++) { - if (parts[i].id_len && - !memcmp(parts[i].id, id, parts[i].id_len)) - return &parts[i]; + for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { + for (j =3D 0; j < manufacturers[i]->nparts; j++) { + part =3D &manufacturers[i]->parts[j]; + if (part->id_len && + !memcmp(part->id, id, part->id_len)) { + nor->manufacturer =3D manufacturers[i]; + return part; + } + } } =20 return NULL; @@ -1648,7 +1653,6 @@ static const struct flash_info *spi_nor_read_id(struc= t spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; - unsigned int i; int ret; =20 if (nor->spimem) { @@ -1668,19 +1672,13 @@ static const struct flash_info *spi_nor_read_id(str= uct spi_nor *nor) return ERR_PTR(ret); } =20 - for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { - info =3D spi_nor_search_part_by_id(manufacturers[i]->parts, - manufacturers[i]->nparts, - id); - if (info) { - nor->manufacturer =3D manufacturers[i]; - return info; - } + info =3D spi_nor_match_id(nor, id); + if (!info) { + dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", + SPI_NOR_MAX_ID_LEN, id); + return ERR_PTR(-ENODEV); } - - dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", - SPI_NOR_MAX_ID_LEN, id); - return ERR_PTR(-ENODEV); + return info; } =20 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34DE6C433EF for ; Wed, 20 Apr 2022 10:35:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377703AbiDTKhr (ORCPT ); Wed, 20 Apr 2022 06:37:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352283AbiDTKhY (ORCPT ); Wed, 20 Apr 2022 06:37:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5768F3FBE0 for ; Wed, 20 Apr 2022 03:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450879; x=1681986879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zRlhInXj/hwNrLMyzPdExzWDA3QtBpUPVqNnBjSLOi4=; b=fmt6jdPS0IYDMMmFTEtI/QqMRNVBM1iZhqkst2YQhaAoD92WrotCSAyJ 5nEJ6M8TjEsqVEaBzxvw8C1RziUHQha98DcLaR9vMDr4f+lwQyNthkj4X ditRIhusVHy5XFUq6wBFvuhZr5ufax/4BpSVhyWgnuU2Uiv4c36nPMPbQ Ns9m65f5xmfwRNyCqGuC+c/g6yd+WdXKBiYm/seZibhXT+0Xi0depx8Ln Ss2kz6XtCe5xxqd++WA5WPwvQ0QMhe+mP+WPKhf1pVvob8HSlHFb4+p7T n7XXWZtOnYsg6dsPJ68VWiDfKoRgc71QXXRkJ5M2nW7UBJbOXLlCms0oT A==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091289" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:38 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:38 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:36 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 03/11] mtd: spi-nor: core: Use auto-detection only once Date: Wed, 20 Apr 2022 13:34:19 +0300 Message-ID: <20220420103427.47867-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In case spi_nor_match_name() returned NULL, the auto detection was issued twice. There's no reason to try to detect the same chip twice, do the auto detection only once. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b9cc8bbf1f62..b55d922d46dd 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2896,13 +2896,14 @@ static const struct flash_info *spi_nor_get_flash_i= nfo(struct spi_nor *nor, { const struct flash_info *info =3D NULL; =20 - if (name) + if (name) { info =3D spi_nor_match_name(nor, name); + if (IS_ERR(info)) + return info; + } /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) - info =3D spi_nor_read_id(nor); - if (IS_ERR_OR_NULL(info)) - return ERR_PTR(-ENOENT); + return spi_nor_read_id(nor); =20 /* * If caller has specified name of flash model that can normally be @@ -2994,7 +2995,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, return -ENOMEM; =20 info =3D spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) + if (!info) + return -ENOENT; + else if (IS_ERR(info)) return PTR_ERR(info); =20 nor->info =3D info; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D97B2C433F5 for ; Wed, 20 Apr 2022 10:35:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377718AbiDTKh4 (ORCPT ); Wed, 20 Apr 2022 06:37:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357782AbiDTKh1 (ORCPT ); Wed, 20 Apr 2022 06:37:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7DC43FBD3 for ; Wed, 20 Apr 2022 03:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450881; x=1681986881; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8j4YRkWjVWV/1ZuDu2r2WbPt7+mjeJU8zN44np+8SxY=; b=tdDz62epLv1mv9bmiEzGC2hC1+8nFz4IfpfU6v21ZFm7ff4cbhy0x/nq fwPX0MhOqCUrONiR2045C5lDINinWEnhqINkDbCVKYEO/Y42p+3aYFvtn Apm3A2+IVSZsZSghDKfKgWXVUsGiFC355xStVUuMTTim2pYlApOETW4Ep qh2vFlsw9Xc4Jm6hLgAcd11I6Zac8ZrdqurFLpyzZyc5c4ZCZvbKv+Wzp JjXoh0lQTrtlhBO7nHUlFYgOADhyWfWN0q4bOeeJcSkJZQIRTd0tqOCJJ GjW0Z5xMcqfr6EJQGbgxU8iVODj1+o1jRxJco4uc/QUH/tlgICOrHX60Q Q==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091291" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:41 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:41 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:38 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 04/11] mtd: spi-nor: core: Introduce method for RDID op Date: Wed, 20 Apr 2022 13:34:20 +0300 Message-ID: <20220420103427.47867-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 50 ++++++++++++++++++++++++++------------ drivers/mtd/spi-nor/core.h | 9 +++++++ 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b55d922d46dd..6165dc7bfd17 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -369,6 +369,37 @@ int spi_nor_write_disable(struct spi_nor *nor) return ret; } =20 +/** + * spi_nor_read_id() - Read the JEDEC ID. + * @nor: pointer to 'struct spi_nor'. + * @naddr: number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @ndummy: number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @id: pointer to a DMA-able buffer where the value of the JEDEC ID + * will be written. + * @proto: the SPI protocol for register operation. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol proto) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN); + + spi_nor_spimem_setup_op(nor, &op, proto); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, + SPI_NOR_MAX_ID_LEN); + } + return ret; +} + /** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. @@ -1649,24 +1680,13 @@ static const struct flash_info *spi_nor_match_id(st= ruct spi_nor *nor, return NULL; } =20 -static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) +static const struct flash_info *spi_nor_detect(struct spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; int ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, - SPI_NOR_MAX_ID_LEN); - } + ret =3D spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); if (ret) { dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); return ERR_PTR(ret); @@ -2903,7 +2923,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, } /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) - return spi_nor_read_id(nor); + return spi_nor_detect(nor); =20 /* * If caller has specified name of flash model that can normally be @@ -2912,7 +2932,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, if (name && info->id_len) { const struct flash_info *jinfo; =20 - jinfo =3D spi_nor_read_id(nor); + jinfo =3D spi_nor_detect(nor); if (IS_ERR(jinfo)) { return jinfo; } else if (jinfo !=3D info) { diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b7fd760e3b47..f952061d5c24 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -11,6 +11,13 @@ =20 #define SPI_NOR_MAX_ID_LEN 6 =20 +/* Standard SPI NOR flash operations. */ +#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ + SPI_MEM_OP_ADDR(naddr, 0, 0), \ + SPI_MEM_OP_DUMMY(ndummy, 0), \ + SPI_MEM_OP_DATA_IN(len, buf, 0)) + enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(0), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), @@ -534,6 +541,8 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); int spi_nor_sr_ready(struct spi_nor *nor); int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8335C433F5 for ; Wed, 20 Apr 2022 10:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377726AbiDTKh7 (ORCPT ); Wed, 20 Apr 2022 06:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359478AbiDTKha (ORCPT ); Wed, 20 Apr 2022 06:37:30 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00C233FBD6 for ; Wed, 20 Apr 2022 03:34:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450886; x=1681986886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QOPdqsb7IX+uNxgIbEEbkjWa7gFF+UyMRRDlspGrMrg=; b=vpapO2n6zNDt84RTFV3noDXD6IhWP3+sqr+XAlvJaGpcA6Mpd08q+SZo 6/CV6M3txS76TjAMszTWaz9tIs7CdQa91MA7uAhNlj0Uv1VuRmtsJB0WD I4BWGPg31vxvo8AOL0sT2IGAfEY1XvOG95dRtJfFX15dIDtJjkZ8tmjh8 Yoyaki6NgiiPXbtZBSpA1K6Z3S5xTkqRsg9QSqYezvLRqGr75NtX81wF9 UK39A82PztZd/KQF9C01ViHa0CEKFCJA/F/bm6HC90aPyQc+/bOP1eku9 qWY/Ap8yYbCFPYY/ahES9vaHdOEGAH8Ca7RliSJYD5QhLJ9kvlO2Eik/c w==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="153206893" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:43 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:41 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 05/11] mtd: spi-nor: manufacturers: Use spi_nor_read_id() core method Date: Wed, 20 Apr 2022 13:34:21 +0300 Message-ID: <20220420103427.47867-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use spi_nor_read_id() core method to avoid duplication of code. Now the ID is read on the full SPI_NOR_MAX_ID_LEN instead of round_up(nor->info->id_len, 2), but it doesn't harm to read more ID bytes, so the change comes with no secondary effects. dev_dbg messages in case spi_nor_read_id() fails, will be added in a further patch after we split the octal DTR enable/disable methods. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/micron-st.c | 13 +++---------- drivers/mtd/spi-nor/spansion.c | 13 +++---------- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 8a20475ce77a..41b87868ecf9 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -91,17 +91,10 @@ static int micron_st_nor_octal_dtr_enable(struct spi_no= r *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_DUMMY(enable ? 8 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index f24e546e04a5..c5988312cc91 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -98,17 +98,10 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor = *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1), - SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA64EC433EF for ; Wed, 20 Apr 2022 10:35:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377683AbiDTKiF (ORCPT ); Wed, 20 Apr 2022 06:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377641AbiDTKhc (ORCPT ); Wed, 20 Apr 2022 06:37:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D09F73FBD5 for ; Wed, 20 Apr 2022 03:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450886; x=1681986886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=maO/ht8L4lItA3cWu+BmhkTcmkuxR6CQ4As+MVnmM84=; b=nO+xkZvqk4ovPJUCKWMM4NED7Y4hY0+K1U6WmH5UZnE4jjQTPhwhA19p bcsQYfHkL2ifRHfICPhAj7jbA/V8Qc4L4oVg8tU/frfOhITLRAdNsan65 7lC81MTPlx6D42qA9Uo4miAxX+QvzprN8DpW8TEDTPZztB9rYv+bzE2p0 bkQHanC2prMlTkF8hituEzpe7sZvD0NpiqJnzt8uqcp+cidwfEFd7fGOb 2GZpUCCWFdov3ECBOpHW/9Ihl40gA1HMyFE3uEegQJkefyfK2e3/eymfr +ck4cEL7fr4EUi0lVRhVj7LWKG5xkAI65kkyJ04OUsccmImSz3cwtg8kO w==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091308" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:46 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:44 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 06/11] mtd: spi-nor: core: Add helpers to read/write any register Date: Wed, 20 Apr 2022 13:34:22 +0300 Message-ID: <20220420103427.47867-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 46 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 4 ++++ 2 files changed, 50 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 6165dc7bfd17..08bf58e5dbd1 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -307,6 +307,52 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t= to, size_t len, return nor->controller_ops->write(nor, to, len, buf); } =20 +/** + * spi_nor_read_any_reg() - read any register from flash memory, nonvolati= le or + * volatile. + * @nor: pointer to 'struct spi_nor'. + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + if (!nor->spimem) + return -EOPNOTSUPP; + + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + +/** + * spi_nor_write_any_volatile_reg() - write any volatile register to flash + * memory. + * @nor: pointer to 'struct spi_nor' + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Writing volatile registers are instant according to some manufacturers + * (Cypress, Micron) and do not need any status polling. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op = *op, + enum spi_nor_protocol proto) +{ + int ret; + + if (!nor->spimem) + return -EOPNOTSUPP; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + /** * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f952061d5c24..62ddadba0c33 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -554,6 +554,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t = from, size_t len, u8 *buf); ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf); +int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); +int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op = *op, + enum spi_nor_protocol proto); int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); =20 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8= *buf); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98E17C433EF for ; Wed, 20 Apr 2022 10:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352271AbiDTKiI (ORCPT ); Wed, 20 Apr 2022 06:38:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377673AbiDTKhf (ORCPT ); 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20 Apr 2022 03:34:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:48 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:46 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 07/11] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Wed, 20 Apr 2022 13:34:23 +0300 Message-ID: <20220420103427.47867-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Add dev_dbg messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/micron-st.c | 111 +++++++++++++++++--------------- 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 41b87868ecf9..ce62e6be8fd2 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -28,75 +28,78 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ =20 -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Micron ST SPI NOR flash operations. */ +#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 20 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - *buf =3D 20; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; - - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - } + /* Use 20 dummy cycles for memory array reads. */ + *buf =3D 20; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_write_enable(nor); + buf[0] =3D SPINOR_MT_OCT_DTR; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_MT_OCT_DTR; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. The next register is the dummy - * cycle configuration register. Since the transaction needs to - * be at least 2 bytes wide, set the next register to its - * default value. This also makes sense because the value was - * changed when enabling 8D-8D-8D mode, it should be reset when - * disabling. - */ - buf[0] =3D SPINOR_MT_EXSPI; - buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mod= e\n", ret); + return ret; } =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_MT_CFR0V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + return 0; +} + +static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. The next register is the dummy cycle configuration + * register. Since the transaction needs to be at least 2 bytes wide, + * set the next register to its default value. This also makes sense + * because the value was changed when enabling 8D-8D-8D mode, it should + * be reset when disabling. + */ + buf[0] =3D SPINOR_MT_EXSPI; + buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); - if (ret) + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mo= de\n", ret); return ret; + } =20 if (memcmp(buf, nor->info->id, nor->info->id_len)) return -EINVAL; @@ -104,6 +107,12 @@ static int micron_st_nor_octal_dtr_enable(struct spi_n= or *nor, bool enable) return 0; } =20 +static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? micron_st_nor_octal_dtr_en(nor) : + micron_st_nor_octal_dtr_dis(nor); +} + static void mt35xu512aba_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D micron_st_nor_octal_dtr_enable; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AB11C433F5 for ; Wed, 20 Apr 2022 10:35:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377685AbiDTKiU (ORCPT ); Wed, 20 Apr 2022 06:38:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377681AbiDTKhh (ORCPT ); Wed, 20 Apr 2022 06:37:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE822DA4 for ; Wed, 20 Apr 2022 03:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450891; x=1681986891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=35s8zzgaSLVt8GRMDwieLQnpD+4vW72LtpsgbSJB94o=; b=Ki+Kwf/9DnMkNJtcjiF/tHhv/HyO84NrmAuMJlWbIzHidV0n7XMTad17 nCZH/2/AqAW6lL5EWpT7XiQ2eAyd1BlO7wAXuZYcswerk51eI4f9dWrTn /v19USaMGwihUAKkPxpyCf1nXFZSNNKtjQfx9K9cKGOTigIfFjS6bamrP P+6G41Sh+wcdwomSoIrYWSHPecgdekW69UfiRSRovblppr0GtYF/HcdTL RsW0XJE9BywMEUWXKJdPcUmAsxoEypNWrCfXKdKRml11MT5zj8earyU6x mWgNGY/5m2QW/j6rb9U9yImTk2cwmvNPIIxwxLeDV8nc+7QUDS4ULgnY4 A==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="161091319" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:51 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:51 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:49 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 08/11] mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable() Date: Wed, 20 Apr 2022 13:34:24 +0300 Message-ID: <20220420103427.47867-9-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Add debug messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/spansion.c | 128 ++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 59 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index c5988312cc91..56b43074ef17 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -23,87 +23,81 @@ #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 #define SPINOR_OP_CYPRESS_RD_FAST 0xee =20 -/** - * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. - * @nor: pointer to a 'struct spi_nor' - * @enable: whether to enable or disable Octal DTR - * - * This also sets the memory access latency cycles to 24 to allow the flas= h to - * run at up to 200MHz. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Cypress SPI NOR flash operations. */ +#define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 24 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; + /* Use 24 dummy cycles for memory array reads. */ + *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf); =20 - *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; + nor->read_dummy =3D 24; =20 - nor->read_dummy =3D 24; - } + /* Set the octal and DTR enable bits. */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf); =20 - /* Set/unset the octal and DTR enable bits. */ - ret =3D spi_nor_write_enable(nor); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. Since there is no register at the - * next location, just initialize the value to 0 and let the - * transaction go on. - */ - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; - buf[1] =3D 0; + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mod= e\n", ret); + return ret; } =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_CYPRESS_CFR5V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + return 0; +} =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. Since there is no register at the next location, + * just initialize the value to 0 and let the transaction go on. + */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[1] =3D 0; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf); + ret =3D spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); - if (ret) + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mo= de\n", ret); return ret; + } =20 if (memcmp(buf, nor->info->id, nor->info->id_len)) return -EINVAL; @@ -111,6 +105,22 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor= *nor, bool enable) return 0; } =20 +/** + * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal DTR + * + * This also sets the memory access latency cycles to 24 to allow the flas= h to + * run at up to 200MHz. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? cypress_nor_octal_dtr_en(nor) : + cypress_nor_octal_dtr_dis(nor); +} + static void s28hs512t_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D cypress_nor_octal_dtr_enable; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC7DC433EF for ; Wed, 20 Apr 2022 10:35:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377712AbiDTKia (ORCPT ); Wed, 20 Apr 2022 06:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377690AbiDTKhl (ORCPT ); Wed, 20 Apr 2022 06:37:41 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C12362676 for ; Wed, 20 Apr 2022 03:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450894; x=1681986894; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tpEy2gHD3aAuDswBbT3iSstEvBWSHcIGyEqbmJDrwEQ=; b=Iv8OJoMXwpNrJ89PFGUJ+QTffTjDD9XwmQX0SJI4hzrLb4+aoQRj4o2V KSV6rm9myN0LAmTdtVeRR5xURFj9Dxkd9kOz3sahGtnJhG2YK/b4oimS0 zuGckC5/7PSnk/AeJDXgdxRrEk/ACwGaEBxzVDOWO27CCzAYMRH3y+9zd 2nGtGSIGRcDwtgcBIjkZ7DuUYPWcEA1YZcNv3i44wUGxGx4CDv3CGG4q4 3nurBEEI28tceGGd+MKF7FftWbXDRgMUapyNxcAeYk5l2mk3LhBC51iC/ y4K6Z5zLyOJrIumkgV3kOMCfAsD2t3U6R/5LLxln5a1OiHDmo8qG3nCSm g==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="92939116" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:53 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:51 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 09/11] mtd: spi-nor: Introduce templates for SPI NOR operations Date: Wed, 20 Apr 2022 13:34:25 +0300 Message-ID: <20220420103427.47867-10-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by: Tudor Ambarus Acked-by: Michael Walle Acked-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 101 ++++++------------------------- drivers/mtd/spi-nor/core.h | 102 ++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/micron-st.c | 24 ++++---- drivers/mtd/spi-nor/spansion.c | 26 +++++--- drivers/mtd/spi-nor/xilinx.c | 12 ++-- 5 files changed, 158 insertions(+), 107 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 08bf58e5dbd1..2bfa84100d38 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -364,11 +364,7 @@ int spi_nor_write_enable(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_WREN_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -395,11 +391,7 @@ int spi_nor_write_disable(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_WRDI_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -459,11 +451,7 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr, 0)); + struct spi_mem_op op =3D SPI_NOR_RDSR_OP(sr); =20 if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; @@ -503,11 +491,7 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, cr, 0)); + struct spi_mem_op op =3D SPI_NOR_RDCR_OP(cr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -536,14 +520,7 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, b= ool enable) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? - SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_EN4B_EX4B_OP(enable); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -577,11 +554,7 @@ static int spansion_set_4byte_addr_mode(struct spi_nor= *nor, bool enable) nor->bouncebuf[0] =3D enable << 7; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); + struct spi_mem_op op =3D SPI_NOR_BRWR_OP(nor->bouncebuf); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -611,11 +584,7 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) nor->bouncebuf[0] =3D ear; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); + struct spi_mem_op op =3D SPI_NOR_WREAR_OP(nor->bouncebuf); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -726,11 +695,7 @@ int spi_nor_global_block_unlock(struct spi_nor *nor) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_GBULK_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -765,11 +730,7 @@ int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr= , size_t len) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(len, sr, 0)); + struct spi_mem_op op =3D SPI_NOR_WRSR_OP(sr, len); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -969,11 +930,7 @@ static int spi_nor_write_sr2(struct spi_nor *nor, cons= t u8 *sr2) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, sr2, 0)); + struct spi_mem_op op =3D SPI_NOR_WRSR2_OP(sr2); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -1005,11 +962,7 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *= sr2) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr2, 0)); + struct spi_mem_op op =3D SPI_NOR_RDSR2_OP(sr2); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -1038,11 +991,7 @@ static int spi_nor_erase_chip(struct spi_nor *nor) dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_CHIP_ERASE_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); =20 @@ -1184,10 +1133,8 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 ad= dr) =20 if (nor->spimem) { struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), - SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, + nor->addr_width, addr); =20 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); =20 @@ -1983,10 +1930,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *n= or, static int spi_nor_spimem_check_readop(struct spi_nor *nor, const struct spi_nor_read_command *read) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), - SPI_MEM_OP_ADDR(3, 0, 0), - SPI_MEM_OP_DUMMY(1, 0), - SPI_MEM_OP_DATA_IN(2, NULL, 0)); + struct spi_mem_op op =3D SPI_NOR_READ_OP(read->opcode); =20 spi_nor_spimem_setup_op(nor, &op, read->proto); =20 @@ -2009,10 +1953,7 @@ static int spi_nor_spimem_check_readop(struct spi_no= r *nor, static int spi_nor_spimem_check_pp(struct spi_nor *nor, const struct spi_nor_pp_command *pp) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), - SPI_MEM_OP_ADDR(3, 0, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(2, NULL, 0)); + struct spi_mem_op op =3D SPI_NOR_PP_OP(pp->opcode); =20 spi_nor_spimem_setup_op(nor, &op, pp->proto); =20 @@ -2836,10 +2777,7 @@ static void spi_nor_soft_reset(struct spi_nor *nor) struct spi_mem_op op; int ret; =20 - op =3D (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DATA); + op =3D (struct spi_mem_op)SPINOR_SRSTEN_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -2849,10 +2787,7 @@ static void spi_nor_soft_reset(struct spi_nor *nor) return; } =20 - op =3D (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DATA); + op =3D (struct spi_mem_op)SPINOR_SRST_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 62ddadba0c33..658ed1779faa 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -18,6 +18,108 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(len, buf, 0)) =20 +#define SPI_NOR_WREN_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_WRDI_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_RDSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPI_NOR_WRSR_OP(buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(len, buf, 0)) + +#define SPI_NOR_RDSR2_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_WRSR2_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_RDCR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPI_NOR_EN4B_EX4B_OP(enable) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_BRWR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_WREAR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_GBULK_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_CHIP_ERASE_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_width, addr) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(addr_width, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_READ_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(3, 0, 0), \ + SPI_MEM_OP_DUMMY(1, 0), \ + SPI_MEM_OP_DATA_IN(2, NULL, 0)) + +#define SPI_NOR_PP_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(3, 0, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(2, NULL, 0)) + +#define SPINOR_SRSTEN_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DATA) + +#define SPINOR_SRST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DATA) + enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(0), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index ce62e6be8fd2..61db4896e327 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -35,6 +35,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) =20 +#define MICRON_ST_RDFSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define MICRON_ST_CLFSR_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; @@ -324,11 +336,7 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor,= u8 *fsr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, fsr, 0)); + struct spi_mem_op op =3D MICRON_ST_RDFSR_OP(fsr); =20 if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; @@ -363,11 +371,7 @@ static void micron_st_nor_clear_fsr(struct spi_nor *no= r) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D MICRON_ST_CLFSR_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 56b43074ef17..7404ca067ca9 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -30,6 +30,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) =20 +#define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPANSION_CLSR_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; @@ -165,12 +177,12 @@ static int s28hs512t_post_bfpt_fixup(struct spi_nor *= nor, * CFR3V[4] and set the correct size. */ struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V, + nor->bouncebuf); int ret; =20 + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + ret =3D spi_mem_exec_op(nor->spimem, &op); if (ret) return ret; @@ -320,11 +332,7 @@ static void spansion_nor_clear_sr(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPANSION_CLSR_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 9459ac2609dc..1d2f5db047bd 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -15,6 +15,12 @@ #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ #define XSR_RDY BIT(7) /* Ready */ =20 +#define XILINX_RDSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ .id =3D { \ ((_jedec_id) >> 16) & 0xff, \ @@ -72,11 +78,7 @@ static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *s= r) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr, 0)); + struct spi_mem_op op =3D XILINX_RDSR_OP(sr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFAE1C433EF for ; Wed, 20 Apr 2022 10:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348828AbiDTKik (ORCPT ); Wed, 20 Apr 2022 06:38:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377695AbiDTKhm (ORCPT ); Wed, 20 Apr 2022 06:37:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 142EA2676 for ; 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Wed, 20 Apr 2022 03:34:56 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:54 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 10/11] mtd: spi-nor: spansion: Remove status polling on volatile registers write Date: Wed, 20 Apr 2022 13:34:26 +0300 Message-ID: <20220420103427.47867-11-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Writing volatile registers are instant according to Cypress and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/spansion.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 7404ca067ca9..43cd6cd92537 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -57,10 +57,6 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) if (ret) return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - nor->read_dummy =3D 24; =20 /* Set the octal and DTR enable bits. */ --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71044C433FE for ; Wed, 20 Apr 2022 10:36:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377717AbiDTKiq (ORCPT ); Wed, 20 Apr 2022 06:38:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351890AbiDTKhp (ORCPT ); Wed, 20 Apr 2022 06:37:45 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F32962676 for ; Wed, 20 Apr 2022 03:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1650450899; x=1681986899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CgU0M9Ctm66tAtz7ZrqfIj4aDO8PJLE7JPM+0GAyffk=; b=lFZnQHxwUWRG/OUKn9Gt/JkUlv7H9q6QnosDFX5o9MWk2eNlgHxn+rkS 0i3EFc/tAEisjB5o80dHNLim55aEQoCQ37OXRNMwGZikAutZnV/+HX3hm Mjt5FL4hSiXCrX0af9Nq93QpBXg0YQN/JO7jYrzRL1YjW/MKzKgoOI1g7 QKz9ZhEjpUAlNDyV2QjIT+xPnfjw1Jxifr7IXKbHPbH0GyRdn4qbMty7f khFC1RoAgdbpBjPHtS+fV3JRF2m9WZPfNpxOicsgfwRIx1/44DhARWlNy gLdpBDbSMSeeOXZy1iVUQgci/aEZ9WuoSoqLC66zhlqxvv91MifcwO9P5 w==; X-IronPort-AV: E=Sophos;i="5.90,275,1643698800"; d="scan'208";a="170245898" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Apr 2022 03:34:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 20 Apr 2022 03:34:58 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 20 Apr 2022 03:34:56 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v4 11/11] mtd: spi-nor: micron-st: Remove status polling on volatile registers write Date: Wed, 20 Apr 2022 13:34:27 +0300 Message-ID: <20220420103427.47867-12-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420103427.47867-1-tudor.ambarus@microchip.com> References: <20220420103427.47867-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Writing volatile registers are instant according to Micron and do not need any status polling. Remove status polling on volatile registers write. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/micron-st.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 61db4896e327..a96f74e0f568 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -58,9 +58,6 @@ static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) op =3D (struct spi_mem_op) MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); ret =3D spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - ret =3D spi_nor_wait_till_ready(nor); if (ret) return ret; =20 --=20 2.25.1