From nobody Sun Sep 22 03:31:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE021C433EF for ; Tue, 19 Apr 2022 18:14:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355536AbiDSSQr (ORCPT ); Tue, 19 Apr 2022 14:16:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356422AbiDSSQB (ORCPT ); Tue, 19 Apr 2022 14:16:01 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 117993EA88; Tue, 19 Apr 2022 11:12:30 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id u18so22350174eda.3; Tue, 19 Apr 2022 11:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nV/V/sSiQrpacLvnsxKcMtnuzTjfpOGiqmnW9+zsuXw=; b=C8+SnHSvi/3OxwkFOy+xJfV8PXdzA+KCAXh+TU+xF+OVvSe3RpJiOEznblvsAwOcDu zzMbQsNlM3oAsUgSoLBVDvUmfoNp1dyyisooBTR2VXMNLVgHfdyTg91VS5cNCwo7WI+N 0TkETmBVk6LR4CKxNMGdlM6LhvbljypPM6xMlDXHkTN2WdA9cUKI0XG61aMFYB0KM7IG rhLmAVDM97ba+odgtNnPTTVsfpF0jN7qrSFmIYo+YI+Y1P5PbTwZtXjXz8XrEH3E7sfL lJx5kx102RHf8tb1oES2lAjcxOJufDCWHl3I0gtSLc6AQFxsP99brDfEq9tjmMzvMFi3 KCag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nV/V/sSiQrpacLvnsxKcMtnuzTjfpOGiqmnW9+zsuXw=; b=07GRT2KkzSjduQLdUrNerQHWyrkBNIohtj2RqCrcLCKTdJsRq+P1OQiCZ9rsRzDpi/ Bntuxx4P3ut2+6sp/nf5p6+zOxuhFkoqtHHl8xEHW/YZFJswN7FV+PiZdZNeSVC4BoNP XEoCWAkwE7yB2F4cpiPY3hawZ2gRxB1f1wWHlgYfKuPk+fodLrqCfO+p4Z0V5rIUdFkS rcM5MvgX2ijgUq4b/N8YJUFrO+qtPdIMKZ6SsKfQcDE09moqO0qPebuvq3pr9eMlyt8B UKsl1kHl0L8ZpTvZeqI9J/hmY+N3XZ6m5H/QggnAKjv+w9RQ0Uy7+80GA29+w/cwpnHh uJBQ== X-Gm-Message-State: AOAM5328RXdGBKWD0yVyB68H5OUUbu8TRKmwEC6sDg4gcO1OKoK+RX96 e+KmEqYGytgC7d5AxGn+VkY= X-Google-Smtp-Source: ABdhPJw5Qs3spIyZaNmqd45dxxwH/JvTxPVzOd6tS7esXoye+O3Ju9Qtxs1013fkuta7ZoX7sN1YbQ== X-Received: by 2002:a05:6402:5cf:b0:41d:7aa7:152a with SMTP id n15-20020a05640205cf00b0041d7aa7152amr19365895edx.68.1650391948620; Tue, 19 Apr 2022 11:12:28 -0700 (PDT) Received: from localhost.localdomain ([212.102.35.230]) by smtp.gmail.com with ESMTPSA id b20-20020a1709063f9400b006e12836e07fsm5930614ejj.154.2022.04.19.11.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 11:12:28 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Sam Shih , Stephen Boyd , Ryder Lee , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: arm: mediatek: topckgen: Convert to DT schema Date: Tue, 19 Apr 2022 22:09:37 +0400 Message-Id: <20220419180938.19397-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419180938.19397-1-y.oudjana@protonmail.com> References: <20220419180938.19397-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert topckgen bindings to DT schema format. MT2701, MT7623 and MT7629 device trees currently have the syscon compatible without it being mentioned in the old DT bindings file which introduces dtbs_check errors when converting to DT schema as-is, so mediatek,mt2701-topckgen and mediatek,mt7629-topckgen are placed in the last items list with the syscon compatible, and syscon is added to the mediatek,mt7623-topckgen list. Signed-off-by: Yassine Oudjana --- .../arm/mediatek/mediatek,topckgen.txt | 35 ----------- .../arm/mediatek/mediatek,topckgen.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,topckgen.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,topckgen.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckg= en.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.t= xt deleted file mode 100644 index b82422bb717f..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek topckgen controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -The Mediatek topckgen controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-topckgen" - - "mediatek,mt2712-topckgen", "syscon" - - "mediatek,mt6765-topckgen", "syscon" - - "mediatek,mt6779-topckgen", "syscon" - - "mediatek,mt6797-topckgen" - - "mediatek,mt7622-topckgen" - - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" - - "mediatek,mt7629-topckgen" - - "mediatek,mt7986-topckgen", "syscon" - - "mediatek,mt8135-topckgen" - - "mediatek,mt8167-topckgen", "syscon" - - "mediatek,mt8173-topckgen" - - "mediatek,mt8183-topckgen", "syscon" - - "mediatek,mt8516-topckgen" -- #clock-cells: Must be 1 - -The topckgen controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -topckgen: power-controller@10000000 { - compatible =3D "mediatek,mt8173-topckgen"; - reg =3D <0 0x10000000 0 0x1000>; - #clock-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckg= en.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.= yaml new file mode 100644 index 000000000000..9ce9cf673cbc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,topckgen.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Top Clock Generator Controller + +maintainers: + - Matthias Brugger + +description: + The Mediatek topckgen controller provides various clocks to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt6797-topckgen + - mediatek,mt7622-topckgen + - mediatek,mt8135-topckgen + - mediatek,mt8173-topckgen + - mediatek,mt8516-topckgen + - items: + - const: mediatek,mt7623-topckgen + - const: mediatek,mt2701-topckgen + - const: syscon + - items: + - enum: + - mediatek,mt2701-topckgen + - mediatek,mt2712-topckgen + - mediatek,mt6765-topckgen + - mediatek,mt6779-topckgen + - mediatek,mt7629-topckgen + - mediatek,mt7986-topckgen + - mediatek,mt8167-topckgen + - mediatek,mt8183-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + topckgen: clock-controller@10000000 { + compatible =3D "mediatek,mt8173-topckgen"; + reg =3D <0x10000000 0x1000>; + #clock-cells =3D <1>; + }; --=20 2.35.3 From nobody Sun Sep 22 03:31:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B5CFC433F5 for ; Tue, 19 Apr 2022 18:14:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356505AbiDSSRO (ORCPT ); Tue, 19 Apr 2022 14:17:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356484AbiDSSQJ (ORCPT ); Tue, 19 Apr 2022 14:16:09 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCC643E0D3; Tue, 19 Apr 2022 11:12:36 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id r13so34610666ejd.5; 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Tue, 19 Apr 2022 11:12:35 -0700 (PDT) Received: from localhost.localdomain ([212.102.35.230]) by smtp.gmail.com with ESMTPSA id b20-20020a1709063f9400b006e12836e07fsm5930614ejj.154.2022.04.19.11.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 11:12:35 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Sam Shih , Stephen Boyd , Ryder Lee , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: arm: mediatek: apmixedsys: Convert to DT schema Date: Tue, 19 Apr 2022 22:09:38 +0400 Message-Id: <20220419180938.19397-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419180938.19397-1-y.oudjana@protonmail.com> References: <20220419180938.19397-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert apmixedsys bindings to DT schema format. MT2701, MT7623 and MT7629 device trees currently have the syscon compatible without it being mentioned in the old DT bindings file which introduces dtbs_check errors when converting to DT schema as-is, so mediatek,mt2701-apmixedsys and mediatek,mt7629-apmixedsys are placed in the last items list with the syscon compatible, and syscon is added to the mediatek,mt7623-apmixedsys list. Signed-off-by: Yassine Oudjana --- .../arm/mediatek/mediatek,apmixedsys.txt | 35 ----------- .../arm/mediatek/mediatek,apmixedsys.yaml | 60 +++++++++++++++++++ 2 files changed, 60 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,apmixedsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,apmixedsys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixe= dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixeds= ys.txt deleted file mode 100644 index 3fa755866528..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek apmixedsys controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D - -The Mediatek apmixedsys controller provides the PLLs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-apmixedsys" - - "mediatek,mt2712-apmixedsys", "syscon" - - "mediatek,mt6765-apmixedsys", "syscon" - - "mediatek,mt6779-apmixedsys", "syscon" - - "mediatek,mt6797-apmixedsys" - - "mediatek,mt7622-apmixedsys" - - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" - - "mediatek,mt7629-apmixedsys" - - "mediatek,mt7986-apmixedsys" - - "mediatek,mt8135-apmixedsys" - - "mediatek,mt8167-apmixedsys", "syscon" - - "mediatek,mt8173-apmixedsys" - - "mediatek,mt8183-apmixedsys", "syscon" - - "mediatek,mt8516-apmixedsys" -- #clock-cells: Must be 1 - -The apmixedsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -apmixedsys: clock-controller@10209000 { - compatible =3D "mediatek,mt8173-apmixedsys"; - reg =3D <0 0x10209000 0 0x1000>; - #clock-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixe= dsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixed= sys.yaml new file mode 100644 index 000000000000..fc967fdc8aec --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.ya= ml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,apmixedsys.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek AP Mixedsys Controller + +maintainers: + - Matthias Brugger + +description: + The Mediatek apmixedsys controller provides PLLs to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt6797-apmixedsys + - mediatek,mt7622-apmixedsys + - mediatek,mt7986-apmixedsys + - mediatek,mt8135-apmixedsys + - mediatek,mt8173-apmixedsys + - mediatek,mt8516-apmixedsys + - items: + - const: mediatek,mt7623-apmixedsys + - const: mediatek,mt2701-apmixedsys + - const: syscon + - items: + - enum: + - mediatek,mt2701-apmixedsys + - mediatek,mt2712-apmixedsys + - mediatek,mt6765-apmixedsys + - mediatek,mt6779-apmixedsys + - mediatek,mt7629-apmixedsys + - mediatek,mt8167-apmixedsys + - mediatek,mt8183-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apmixedsys: clock-controller@10209000 { + compatible =3D "mediatek,mt8173-apmixedsys"; + reg =3D <0x10209000 0x1000>; + #clock-cells =3D <1>; + }; --=20 2.35.3 From nobody Sun Sep 22 03:31:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E68C433EF for ; Tue, 19 Apr 2022 18:15:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356452AbiDSSR4 (ORCPT ); Tue, 19 Apr 2022 14:17:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238262AbiDSSQi (ORCPT ); Tue, 19 Apr 2022 14:16:38 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC4DE3E5CC; Tue, 19 Apr 2022 11:12:42 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id k23so34593070ejd.3; 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Tue, 19 Apr 2022 11:12:41 -0700 (PDT) Received: from localhost.localdomain ([212.102.35.230]) by smtp.gmail.com with ESMTPSA id b20-20020a1709063f9400b006e12836e07fsm5930614ejj.154.2022.04.19.11.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 11:12:40 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: Sam Shih , Stephen Boyd , Ryder Lee , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] dt-bindings: arm: mediatek: infracfg: Convert to DT schema Date: Tue, 19 Apr 2022 22:09:39 +0400 Message-Id: <20220419180938.19397-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419180938.19397-1-y.oudjana@protonmail.com> References: <20220419180938.19397-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Convert infracfg bindings to DT schema format. Not all drivers currently implement resets, so #reset-cells is made a required property only for those that do. Using power-controller in the example node name makes #power-domain-cells required causing a dt_binding_check error. To solve this, the node is renamed to syscon@10001000. Signed-off-by: Yassine Oudjana --- .../arm/mediatek/mediatek,infracfg.txt | 42 ---------- .../arm/mediatek/mediatek,infracfg.yaml | 79 +++++++++++++++++++ 2 files changed, 79 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,infracfg.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek= ,infracfg.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.t= xt deleted file mode 100644 index f66bd720571d..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek infracfg controller -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -The Mediatek infracfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt2712-infracfg", "syscon" - - "mediatek,mt6765-infracfg", "syscon" - - "mediatek,mt6779-infracfg_ao", "syscon" - - "mediatek,mt6797-infracfg", "syscon" - - "mediatek,mt7622-infracfg", "syscon" - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" - - "mediatek,mt7629-infracfg", "syscon" - - "mediatek,mt7986-infracfg", "syscon" - - "mediatek,mt8135-infracfg", "syscon" - - "mediatek,mt8167-infracfg", "syscon" - - "mediatek,mt8173-infracfg", "syscon" - - "mediatek,mt8183-infracfg", "syscon" - - "mediatek,mt8516-infracfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The infracfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -infracfg: power-controller@10001000 { - compatible =3D "mediatek,mt8173-infracfg", "syscon"; - reg =3D <0 0x10001000 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.= yaml new file mode 100644 index 000000000000..4f43fe9f103e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Infrastructure System Configuration Controller + +maintainers: + - Matthias Brugger + +description: + The Mediatek infracfg controller provides various clocks and reset outpu= ts + to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt6765-infracfg + - mediatek,mt6779-infracfg_ao + - mediatek,mt6797-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7629-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8167-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg + - mediatek,mt8516-infracfg + - const: syscon + - items: + - const: mediatek,mt7623-infracfg + - const: mediatek,mt2701-infracfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-infracfg + - mediatek,mt2712-infracfg + - mediatek,mt7622-infracfg + - mediatek,mt7986-infracfg + - mediatek,mt8135-infracfg + - mediatek,mt8173-infracfg + - mediatek,mt8183-infracfg +then: + required: + - '#reset-cells' + +additionalProperties: false + +examples: + - | + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8173-infracfg", "syscon"; + reg =3D <0x10001000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.35.3