From nobody Mon May 11 01:27:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88FEBC433F5 for ; Tue, 19 Apr 2022 07:04:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349190AbiDSHHB (ORCPT ); Tue, 19 Apr 2022 03:07:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239517AbiDSHGr (ORCPT ); Tue, 19 Apr 2022 03:06:47 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B6282AC6C; Tue, 19 Apr 2022 00:04:06 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73gRB090906; Tue, 19 Apr 2022 02:03:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351822; bh=cS1ujKRXfeekCoucx1kpu9VR/rYFmM9er/UxuZoNJeI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rDyD6C4s31J2ShRr2xeK6mZdF6+nLe19aQfcIvOMdOhCVnCKICq3Fo7EAYZc9sVU0 uMyexsL7828uQL2UckJG6f6eJaznxU+/fAltthGeEZ9H6E52keYOf4FANc9/xi/Aou gs5IcCn5wlykbRJRkPFfRDLxPJJsC8fSIpfDPTXw= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73gKc099040 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:42 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:42 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73fjU026287; Tue, 19 Apr 2022 02:03:42 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Date: Tue, 19 Apr 2022 12:33:01 +0530 Message-ID: <20220419070302.16502-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com> References: <20220419070302.16502-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DSS IP on the ti-am65x soc supports an additional register space, named "common1". Further. the IP services a maximum number of 2 interrupts. Add the missing register space "common1" and the additional interrupt. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen --- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..102059e9e0d5 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -26,6 +26,7 @@ properties: Addresses to each DSS memory region described in the SoC's TRM. items: - description: common DSS register area + - description: common1 DSS register area - description: VIDL1 light video plane - description: VID video plane - description: OVR1 overlay manager for vp1 @@ -36,6 +37,7 @@ properties: reg-names: items: - const: common + - const: common1 - const: vidl1 - const: vid - const: ovr1 @@ -64,7 +66,7 @@ properties: maxItems: 3 =20 interrupts: - maxItems: 1 + maxItems: 2 =20 power-domains: maxItems: 1 @@ -122,13 +124,14 @@ examples: dss: dss@4a00000 { compatible =3D "ti,am65x-dss"; reg =3D <0x04a00000 0x1000>, /* common */ + reg =3D <0x04a01000 0x1000>, /* common1 */ <0x04a02000 0x1000>, /* vidl1 */ <0x04a06000 0x1000>, /* vid */ <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ <0x04a0b000 0x1000>; /* vp2 */ - reg-names =3D "common", "vidl1", "vid", + reg-names =3D "common", "common1". "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl =3D <&dss_oldi_io_ctrl>; power-domains =3D <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; @@ -136,7 +139,8 @@ examples: <&k3_clks 216 1>, <&k3_clks 67 2>; clock-names =3D "fck", "vp1", "vp2"; - interrupts =3D ; + interrupts =3D , + ; ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.35.3 From nobody Mon May 11 01:27:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74652C433EF for ; Tue, 19 Apr 2022 07:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349177AbiDSHGy (ORCPT ); Tue, 19 Apr 2022 03:06:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239397AbiDSHGq (ORCPT ); Tue, 19 Apr 2022 03:06:46 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08E582AE00; Tue, 19 Apr 2022 00:04:04 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73ich090970; Tue, 19 Apr 2022 02:03:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351824; bh=rQb5x+seCA/gRyaHh8ycHp7w1ZagLiW2Ocbe4cn0WE8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FNu3cIpmQP2T3j6CKBtdoi23GtPDA+QFvlWI5fDl7zWaCEITM4XZG4r/kERHKh21h aEB3jwf9YRd5GVnGck4eOgO8sNYk/IVp/Lasx3m+dk5iDOq2ZvstCciXTs+Wo0nfqa 8Ja3MWfPnb5xEejkmUJqcZ8OfNDhg4wLBUJsTWgs= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73iUC031438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:44 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:43 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:43 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73hAJ105340; Tue, 19 Apr 2022 02:03:43 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Date: Tue, 19 Apr 2022 12:33:02 +0530 Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com> References: <20220419070302.16502-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DSS IP on the ti-am65x soc supports an additional register space named "common1". Further, it services a maximum of 2 interrupts. Add the missing register space "common1" and the additional interrupt in the dss DT node . Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index e749343acced..1bafa3a98e71 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -830,13 +830,14 @@ csi2_0: port@0 { dss: dss@4a00000 { compatible =3D "ti,am65x-dss"; reg =3D <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a01000 0x0 0x1000>, /* common1 */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ <0x0 0x04a06000 0x0 0x1000>, /* vid */ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ - reg-names =3D "common", "vidl1", "vid", + reg-names =3D "common", "common1", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; =20 ti,am65x-oldi-io-ctrl =3D <&dss_oldi_io_ctrl>; @@ -856,7 +857,8 @@ dss: dss@4a00000 { assigned-clocks =3D <&k3_clks 67 2>; assigned-clock-parents =3D <&k3_clks 67 5>; =20 - interrupts =3D ; + interrupts =3D , + ; =20 dma-coherent; =20 --=20 2.35.3