From nobody Thu Jun 18 18:45:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BA13C433EF for ; Sat, 16 Apr 2022 09:02:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230501AbiDPJEk (ORCPT ); Sat, 16 Apr 2022 05:04:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230460AbiDPJEg (ORCPT ); Sat, 16 Apr 2022 05:04:36 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE00C1066E2; Sat, 16 Apr 2022 02:02:04 -0700 (PDT) Received: by mail-qv1-xf30.google.com with SMTP id d9so7850437qvm.4; Sat, 16 Apr 2022 02:02:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OHIHH7LBjO7n3w0TkyTvZ+CHhZPHMYRUZ96K/VbT0E0=; b=iEN3ZCVaS/t/rWCo/X/zbmS+TjDfAMD6Cpvna9HLhP+x6o6ZYla5+H0GhKvSS5rkNP 8ikamagqu15rha3O9npox2er4Nlo0Hn7ck8poWqBP/q72eCOKEY/dfZt4n41DYaOXrMp EDwEY8QW0e7FKJ8/isjurvCHIKVg+t8SYaanJRsQ2GTh/Xk7Tk9iTdHIqZ2hnCIihenU q+gEjJfKEWbPvQw1Pk47xBBn46/Sof/bvznKDvCqWTND5RbtxfUHpVMZ9XA0YrWq9JBj OR9G+IgS/PA/CTIH4SeRb1oG9054zyGVN9LGAXNtVnduvG9YGfhtywCIy+He6L9mMd9g mbvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OHIHH7LBjO7n3w0TkyTvZ+CHhZPHMYRUZ96K/VbT0E0=; b=Yygr/ux+MpKZ0QyThc9rYdSV7tTiZ4ZqA+WDLq7M1l3GkQcXoOZmhvQ57a9QNrxc+z AzLJ2HlK0q40RWTulLT4JldJUv0Y/3FFHSmmaKhotrqa2oO110lwjeDefQ+JJhvuWHcy h59GWcmoerUWnI6Cp3pYn3CE+Qn2Ira3xnwxlVdmfqT+5DMGwF87YocDPkeuQ8k9VQeM RvZB/GDlKogNL27IuzIlwdBXHPsE20ANEKiQMCJlrgproxxe9T5D2LAXTwrqRI1/RsME xDyGhpTiEzbCwupLYroDKyPQgNa5vtbkxlX8OlK8iqJaMIogQPn2WJ9shydp3fCiYaAE Wu8A== X-Gm-Message-State: AOAM530W1KAQ1lwmeJBZGWbHM/c4tL9RxYXf6uPBNpEplZw/QAhRi4Ei qHf8hD+RByC0ZWliHejqUzYpd0fYb6xg8Bcx X-Google-Smtp-Source: ABdhPJwpTvo4039/1P9AMC+MpCNIKVZR96KS8e9MCcSnpiwoRZMepeQPw0q+y1JNs/94Sh5JjUSMwQ== X-Received: by 2002:a05:6214:e4a:b0:444:28a7:9fb7 with SMTP id o10-20020a0562140e4a00b0044428a79fb7mr1733610qvc.30.1650099724058; Sat, 16 Apr 2022 02:02:04 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id o6-20020a05622a044600b002e1b9be8e6fsm4258085qtx.36.2022.04.16.02.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 02:02:03 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Michael Riesch , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer Subject: [PATCH v4 1/4] arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10 Date: Sat, 16 Apr 2022 05:01:56 -0400 Message-Id: <20220416090159.596930-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416090159.596930-1-pgwipeout@gmail.com> References: <20220416090159.596930-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Riesch The Rockchip RK3568 EVB1 features one USB 3.0 device-only (USB 2.0 OTG) port and one USB 3.0 host-only port. Activate the USB 3.0 controller nodes and phy nodes in the device tree. Signed-off-by: Sascha Hauer Signed-off-by: Michael Riesch --- .../boot/dts/rockchip/rk3568-evb1-v10.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3568-evb1-v10.dts index a794a0ea5c70..622be8be9813 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -103,6 +103,18 @@ vcc5v0_usb_host: vcc5v0-usb-host { vin-supply =3D <&vcc5v0_usb>; }; =20 + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en>; + regulator-name =3D "vcc5v0_usb_otg"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usb>; + }; + vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible =3D "regulator-fixed"; regulator-name =3D "vcc3v3_lcd0_n"; @@ -136,6 +148,14 @@ regulator-state-mem { }; }; =20 +&combphy0 { + status =3D "okay"; +}; + +&combphy1 { + status =3D "okay"; +}; + &cpu0 { cpu-supply =3D <&vdd_cpu>; }; @@ -507,6 +527,9 @@ usb { vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; =20 @@ -568,6 +591,11 @@ &usb_host0_ohci { status =3D "okay"; }; =20 +&usb_host0_xhci { + extcon =3D <&usb2phy0>; + status =3D "okay"; +}; + &usb_host1_ehci { status =3D "okay"; }; @@ -576,6 +604,24 @@ &usb_host1_ohci { status =3D "okay"; }; =20 +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy0_otg { + vbus-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + &usb2phy1 { status =3D "okay"; }; --=20 2.25.1 From nobody Thu Jun 18 18:45:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFF18C433EF for ; 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Sat, 16 Apr 2022 02:02:04 -0700 (PDT) From: Peter Geis To: Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/4] dt-bindings: pci: remove fallback from Rockchip DesignWare binding Date: Sat, 16 Apr 2022 05:01:57 -0400 Message-Id: <20220416090159.596930-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416090159.596930-1-pgwipeout@gmail.com> References: <20220416090159.596930-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The snps,dw-pcie binds to a standalone driver. It is not fully compatible with the Rockchip implementation and causes a hang if it binds to the device. Remove this binding as a valid fallback. Signed-off-by: Peter Geis --- .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..bc0a9d1db750 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -19,20 +19,10 @@ description: |+ allOf: - $ref: /schemas/pci/pci-bus.yaml# =20 -# We need a select here so we don't match all nodes with 'snps,dw-pcie' -select: - properties: - compatible: - contains: - const: rockchip,rk3568-pcie - required: - - compatible - properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie =20 reg: items: @@ -110,7 +100,7 @@ examples: #size-cells =3D <2>; =20 pcie3x2: pcie@fe280000 { - compatible =3D "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible =3D "rockchip,rk3568-pcie"; reg =3D <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; --=20 2.25.1 From nobody Thu Jun 18 18:45:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81DF1C433FE for ; Sat, 16 Apr 2022 09:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbiDPJEv (ORCPT ); Sat, 16 Apr 2022 05:04:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230493AbiDPJEi (ORCPT ); Sat, 16 Apr 2022 05:04:38 -0400 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 093C51066D9; Sat, 16 Apr 2022 02:02:07 -0700 (PDT) Received: by mail-qk1-x72a.google.com with SMTP id a186so5335031qkc.10; Sat, 16 Apr 2022 02:02:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2wd9sVHC/mmpYlhb5g3G/iw92sjMjBm/QMls3NoS/gY=; b=gBastN6vQYfwCm8Q6m+J1iwh3aIAYHUc1b1sXaq7Jhx0NND7+HnxmIJJkE2IF1zNZZ e86wEpsqhUxfA+F5SCcdD1P/NMsbHvzm41rOecue6C01bApMrW5/LWeafZv2VpKdwOt5 5Lx3GV29yRv+awhNKJ723Eo+7oSE2EGx6a/YiyUs2FZQN1Hre37kgvbnMTEPyXOGB7YE Iuc6pYPMOV2LN9peMb0zU/qqd49u+AM8GvrfRoow0QftvtEbL0tc5QOXm8TmQ/WFGEmI INrfKKyckBBCdTfg8sBNBO1mDDeQAapdepsphs442HXUEXJM++rQ8xJj0aWyGZgKvAs6 zbBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2wd9sVHC/mmpYlhb5g3G/iw92sjMjBm/QMls3NoS/gY=; b=DNeAcfB7nzdVm+midlA0tu2F7SW09cdz5ZyzPbrBhw/7/RW2cgybZrWAYQJ2nLorAJ KuDelPFGdnG9FVGuI0juvSGgE8XqhMRg1nkU+lVopr37zZxSUO7u3a3Jpf6WKPMnyr+9 bYY+cBmw6vKiExDOUEBI4gvYXtflX9MYQfjMLs/tZDQNjVqhvED32MUBJEbTZcJwcAOj piRelixhhTs2S9GYDnJJmb2ZcC+IGv6Ikt42UgYkdM+qmoj2bpg5l4C3wL2yXZ8wdPyc 3caC1y++j+rm/nxBfPlxwL/o+SRLQxAVpOOb7h0ZoFNyHzS2916HPj1Llcm2HBcgmlnK 51Zw== X-Gm-Message-State: AOAM530rVbTyIDEidOGqP389Fh2s+hAhHkC9/J9kneHOa2Ibg0+BvX5O gj52tg/VTnls3t95ZhLIKC8= X-Google-Smtp-Source: ABdhPJy3l+7p3EOU3dRUieRVqz2WtZcfZ/JTxg9Xej1AnMNkRNHvbQwBf9wAhZxhEwuZWsBG6htNZw== X-Received: by 2002:a05:620a:2807:b0:67d:6349:2577 with SMTP id f7-20020a05620a280700b0067d63492577mr1442226qkp.785.1650099726080; Sat, 16 Apr 2022 02:02:06 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id o6-20020a05622a044600b002e1b9be8e6fsm4258085qtx.36.2022.04.16.02.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 02:02:05 -0700 (PDT) From: Peter Geis To: Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] PCI: dwc: rockchip: add legacy interrupt support Date: Sat, 16 Apr 2022 05:01:58 -0400 Message-Id: <20220416090159.596930-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416090159.596930-1-pgwipeout@gmail.com> References: <20220416090159.596930-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The legacy interrupts on the rk356x pcie controller are handled by a single muxed interrupt. Add irq domain support to the pcie-dw-rockchip driver to support the virtual domain. Signed-off-by: Peter Geis --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 112 +++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index c9b341e55cbb..863374604fb1 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -10,9 +10,12 @@ =20 #include #include +#include +#include #include #include #include +#include #include #include #include @@ -36,10 +39,13 @@ #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c #define PCIE_CLIENT_GENERAL_DEBUG 0x104 -#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) +#define PCIE_LEGACY_INT_ENABLE GENMASK(3, 0) +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { @@ -51,6 +57,8 @@ struct rockchip_pcie { struct reset_control *rst; struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; + struct irq_domain *irq_domain; + raw_spinlock_t irq_lock; }; =20 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, @@ -65,6 +73,94 @@ static void rockchip_pcie_writel_apb(struct rockchip_pci= e *rockchip, writel_relaxed(val, rockchip->apb_base + reg); } =20 +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct rockchip_pcie *rockchip =3D irq_desc_get_handler_data(desc); + unsigned long reg, hwirq; + + chained_irq_enter(chip, desc); + + reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); + + for_each_set_bit(hwirq, ®, 8) + generic_handle_domain_irq(rockchip->irq_domain, hwirq); + + chained_irq_exit(chip, desc); +} + +static void rockchip_intx_mask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip =3D irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* disable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val =3D HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val |=3D PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static void rockchip_intx_unmask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip =3D irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* enable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val =3D HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val &=3D ~PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static struct irq_chip rockchip_intx_irq_chip =3D { + .name =3D "INTx", + .irq_mask =3D rockchip_intx_mask, + .irq_unmask =3D rockchip_intx_unmask, + .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, +}; + +static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int = irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops =3D { + .map =3D rockchip_pcie_intx_map, +}; + +static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) +{ + struct device *dev =3D rockchip->pci.dev; + struct device_node *intc; + + raw_spin_lock_init(&rockchip->irq_lock); + + intc =3D of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"= ); + if (!intc) { + dev_err(dev, "missing child interrupt-controller node\n"); + return -EINVAL; + } + + rockchip->irq_domain =3D irq_domain_add_linear(intc, PCI_NUM_INTX, + &intx_domain_ops, rockchip); + of_node_put(intc); + if (!rockchip->irq_domain) { + dev_err(dev, "failed to get a INTx IRQ domain\n"); + return -EINVAL; + } + + return 0; +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -111,7 +207,19 @@ static int rockchip_pcie_host_init(struct pcie_port *p= p) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); + struct device *dev =3D rockchip->pci.dev; u32 val =3D HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + int irq, ret; + + irq =3D of_irq_get_byname(dev->of_node, "legacy"); + if (irq < 0) + return irq; + + ret =3D rockchip_pcie_init_irq_domain(rockchip); + if (ret < 0) + dev_err(dev, "failed to init irq domain\n"); + + irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, r= ockchip); =20 /* LTSSM enable control mode */ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); --=20 2.25.1 From nobody Thu Jun 18 18:45:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C9F0C433EF for ; Sat, 16 Apr 2022 09:02:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231140AbiDPJE4 (ORCPT ); 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Sat, 16 Apr 2022 02:02:06 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller Date: Sat, 16 Apr 2022 05:01:59 -0400 Message-Id: <20220416090159.596930-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416090159.596930-1-pgwipeout@gmail.com> References: <20220416090159.596930-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The pcie2x1 controller is common between the rk3568 and rk3566. It is a single lane pcie2 compliant controller. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index ca20d7b91fe5..b2f91aaacca5 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -722,6 +722,61 @@ qos_vop_m1: qos@fe1a8100 { reg =3D <0x0 0xfe1a8100 0x0 0x20>; }; =20 + pcie2x1: pcie@fe260000 { + compatible =3D "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xf>; + assigned-clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msi", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <6>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + msi-map =3D <0x0 &its 0x0 0x1000>; + num-lanes =3D <1>; + phys =3D <&combphy2 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3568_PD_PIPE>; + reg =3D <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x00000000 0x0 0x01000000>; + ranges =3D <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 + 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE20_POWERUP>; + reset-names =3D "pipe"; + status =3D "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + }; + sdmmc0: mmc@fe2b0000 { compatible =3D "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg =3D <0x0 0xfe2b0000 0x0 0x4000>; --=20 2.25.1