From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59748C433EF for ; Sat, 16 Apr 2022 04:26:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbiDPE2x (ORCPT ); Sat, 16 Apr 2022 00:28:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbiDPE2t (ORCPT ); Sat, 16 Apr 2022 00:28:49 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711ACFDE15 for ; Fri, 15 Apr 2022 21:26:19 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id ll10so8955296pjb.5 for ; Fri, 15 Apr 2022 21:26:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/4psa0PrdKvlWjB2+JZ/eA8z6XCUnC2kvgJwCGBUqzs=; b=LQZL+AMRhCLnQI3Mq2wA12Ltli9F4052F+wjLUHlmkMXG3MWCEkDm1KMzruYoCf1kh NMSaG+yJMLDHXtr6K8Ntfv/fOJB9Cm1IO0YiOicPYIBCIqJYu4vL0KaDODrnXEULHgBL OGxNbneLU/hLZE5QKDvoNCLFE1MCDragVQFM6+xR+o6YeTOxnjALWNV3Q6iGZJtDfERE wO9s6xMICFznffXBVflMNekqLcPh7xpkuYYnejnYHkdJPiPDgSftXqIh8nswwaGJ3/T2 ZOvyNC0dX9RQA/x/QZUhkWthAFilDuycVC5Wq2iMJ7CQ6RLJ5SoBe1PS7ii/UjwKCmNY FMSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/4psa0PrdKvlWjB2+JZ/eA8z6XCUnC2kvgJwCGBUqzs=; b=05IvjTndU+CX2ZhA64fIQ7y/3SCUWYUBnB8DUQsKLnSHGw2h8Uy73k2sZxxaXobCcs FgEb6Br2QJk8udhWDdjELdHMGr7kXRe4PVmoTtcmFbkFnfrb/qqREYUcFLrhUc12zM2W ft2195Nl5J2I5JX0P1r1fRxbdu5r5SgENuyxn1+6e7OXgfwHD/pHOfZOlFRMFd088Ddb uu571EgMAVERXbHBuRkbDUPJcaPOM5DBGafjx7KD6aA2g4aaD97+hHETJ67xkYH29lwr qkDQbucgB5FXWKGfE3Dsx68FbynstXpf5D5eFyYrCdVoOK8e2zcFKpECz4EGSzQ27O2z 2bNw== X-Gm-Message-State: AOAM530gHz+P4Rvj9fp8tvPAMJCJ2scazrPwIYG8XhJiRTUls33KOKSr G6go1YOlPfhgHYulRWn14OU= X-Google-Smtp-Source: ABdhPJxLK+WuDeDgUgCMsbTAgcFQ8m2Ij8hpPzKxFxayPUgJXgRD2B7p0XzNZR5ukhvoaOXP9TTQTg== X-Received: by 2002:a17:90b:1809:b0:1d2:6345:b000 with SMTP id lw9-20020a17090b180900b001d26345b000mr303686pjb.98.1650083178925; Fri, 15 Apr 2022 21:26:18 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:9b6:6aad:72f6:6e16]) by smtp.gmail.com with ESMTPSA id d8-20020aa78688000000b00505793566f7sm4258513pfo.211.2022.04.15.21.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 21:26:18 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 1/6] xtensa: clean up function declarations in traps.c Date: Fri, 15 Apr 2022 21:25:54 -0700 Message-Id: <20220416042559.2035015-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop 'extern' from all function declarations. Add 'static' to declarations and definitions only used locally. Add argument names in declarations. Drop unused and not passed second argument from do_multihit and do_page_fault. Signed-off-by: Max Filippov --- arch/xtensa/kernel/traps.c | 61 +++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 515719c7e750..a85992d60c11 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -48,25 +48,31 @@ * Machine specific interrupt handlers */ =20 -extern void kernel_exception(void); -extern void user_exception(void); - -extern void fast_illegal_instruction_user(void); -extern void fast_syscall_user(void); -extern void fast_alloca(void); -extern void fast_unaligned(void); -extern void fast_second_level_miss(void); -extern void fast_store_prohibited(void); -extern void fast_coprocessor(void); - -extern void do_illegal_instruction (struct pt_regs*); -extern void do_interrupt (struct pt_regs*); -extern void do_nmi(struct pt_regs *); -extern void do_unaligned_user (struct pt_regs*); -extern void do_multihit (struct pt_regs*, unsigned long); -extern void do_page_fault (struct pt_regs*, unsigned long); -extern void do_debug (struct pt_regs*); -extern void system_call (struct pt_regs*); +void kernel_exception(void); +void user_exception(void); + +void fast_illegal_instruction_user(void); +void fast_syscall_user(void); +void fast_alloca(void); +void fast_unaligned(void); +void fast_second_level_miss(void); +void fast_store_prohibited(void); +void fast_coprocessor(void); + +void do_IRQ(int hwirq, struct pt_regs *regs); +void do_page_fault(struct pt_regs *regs); +void system_call(struct pt_regs *regs); + +static void do_illegal_instruction(struct pt_regs *regs); +static void do_interrupt(struct pt_regs *regs); +#if XTENSA_FAKE_NMI +static void do_nmi(struct pt_regs *regs); +#endif +#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION +static void do_unaligned_user(struct pt_regs *regs); +#endif +static void do_multihit(struct pt_regs *regs); +static void do_debug(struct pt_regs *regs); =20 /* * The vector table must be preceded by a save area (which @@ -197,7 +203,7 @@ void do_unhandled(struct pt_regs *regs, unsigned long e= xccause) * Multi-hit exception. This if fatal! */ =20 -void do_multihit(struct pt_regs *regs, unsigned long exccause) +static void do_multihit(struct pt_regs *regs) { die("Caught multihit exception", regs, SIGKILL); } @@ -206,8 +212,6 @@ void do_multihit(struct pt_regs *regs, unsigned long ex= ccause) * IRQ handler. */ =20 -extern void do_IRQ(int, struct pt_regs *); - #if XTENSA_FAKE_NMI =20 #define IS_POW2(v) (((v) & ((v) - 1)) =3D=3D 0) @@ -240,7 +244,7 @@ irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_i= d); =20 DEFINE_PER_CPU(unsigned long, nmi_count); =20 -void do_nmi(struct pt_regs *regs) +static void do_nmi(struct pt_regs *regs) { struct pt_regs *old_regs =3D set_irq_regs(regs); =20 @@ -253,7 +257,7 @@ void do_nmi(struct pt_regs *regs) } #endif =20 -void do_interrupt(struct pt_regs *regs) +static void do_interrupt(struct pt_regs *regs) { static const unsigned int_level_mask[] =3D { 0, @@ -303,8 +307,7 @@ void do_interrupt(struct pt_regs *regs) * Illegal instruction. Fatal if in kernel space. */ =20 -void -do_illegal_instruction(struct pt_regs *regs) +static void do_illegal_instruction(struct pt_regs *regs) { __die_if_kernel("Illegal instruction in kernel", regs, SIGKILL); =20 @@ -324,8 +327,7 @@ do_illegal_instruction(struct pt_regs *regs) */ =20 #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION -void -do_unaligned_user (struct pt_regs *regs) +static void do_unaligned_user(struct pt_regs *regs) { __die_if_kernel("Unhandled unaligned exception in kernel", regs, SIGKILL); @@ -346,8 +348,7 @@ do_unaligned_user (struct pt_regs *regs) * breakpoint structures to debug registers intact, so that * DEBUGCAUSE.DBNUM could be used in case of data breakpoint hit. */ -void -do_debug(struct pt_regs *regs) +static void do_debug(struct pt_regs *regs) { #ifdef CONFIG_HAVE_HW_BREAKPOINT int ret =3D check_hw_breakpoint(regs); --=20 2.30.2 From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A8D9C433EF for ; Sat, 16 Apr 2022 04:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230028AbiDPE24 (ORCPT ); Sat, 16 Apr 2022 00:28:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230012AbiDPE2u (ORCPT ); Sat, 16 Apr 2022 00:28:50 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C069C10E067 for ; Fri, 15 Apr 2022 21:26:20 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id c12so8473776plr.6 for ; Fri, 15 Apr 2022 21:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KBVMtZkCYV32p1etltthkvwAoUXM8dM83npMiYgUh/w=; b=cqy6eRhcdih66RqCTWjHb297/2SFSexwmd2okcLZgVZEEqaOnpUDO5AKVY+cUAxawo /oBVREYAyWGQolkfrsbFcRIYUxyTUEb0prVYzMBn0B5n/rB8mctUu+xTUwv5Co9Sw5oE 0zt4AV0+V8oWrFQ0cRSabQKe1dhgmS4poAH32TnZyn+wAki9bN9BJP70HcpMk4nKMyJu m9Rpi2gEe5Whqp2xziQEIzZFUaF6V+k4Q77O7z8/RGP2NhVgURHVcHxcMEjDdKOfuZf6 xCQDF5SR9PeCD7TfzyaCekaj6jR8x91kr1Y6iVx/CqXtW6fM85i0Yf8HWVkbZGxJZq6Y KS/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KBVMtZkCYV32p1etltthkvwAoUXM8dM83npMiYgUh/w=; b=0+jE2M10cO1H/8j/j+67wl9zbOTkNer8Rjbu00Dfmf02TLGmxBc89abQMe8c1/tsT5 IOf0oFlIJamztKem3yi2wip6T1Kd7gO628TtAtmxHBThhq1vSixhRL6nLQslk8Wu72KY 92+ZZxFpSHCQEsEeDZ6ivyBx9HPCvT+oqQ41FY69gp3gV3kQyw2P3Sbyw5/fbpMcacJB lZt+aDq2zVEP9bzKr/6qJkHSgSQ58sR1ti5mctGJmSYaQcXaC04lz0cFD+vpx8WPsru0 7hEMF+FkCgTxGan4/5O0Qoj65fKWHyrY99L/b0ozNH9banx3umnPo7N20kUSazGq4Twf EZzA== X-Gm-Message-State: AOAM5335d19974ltT+PJAxs9kN9mWR/Ff6nVii7xvXWDatZRjlf8jO+d 4L4DQ7XdBO+s2ikyyG7UMZ0= X-Google-Smtp-Source: ABdhPJx6ECAXsP/4flRg5/N6HdnBc7pZXMLqvV2IlWZ5mKExN4qZbQJr0vfEWvAd14AtSTBKrecCig== X-Received: by 2002:a17:90b:1b47:b0:1d0:fdb2:6fb with SMTP id nv7-20020a17090b1b4700b001d0fdb206fbmr2166841pjb.186.1650083180228; Fri, 15 Apr 2022 21:26:20 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:9b6:6aad:72f6:6e16]) by smtp.gmail.com with ESMTPSA id d8-20020aa78688000000b00505793566f7sm4258513pfo.211.2022.04.15.21.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 21:26:19 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 2/6] xtensa: clean up declarations in coprocessor.h Date: Fri, 15 Apr 2022 21:25:55 -0700 Message-Id: <20220416042559.2035015-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop 'extern' from all function declarations. Add argument names in declarations. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/coprocessor.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/as= m/coprocessor.h index 0fbe2a740b8d..a360efced7e7 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -143,10 +143,9 @@ typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); =20 extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; -extern void coprocessor_flush(struct thread_info*, int); - -extern void coprocessor_release_all(struct thread_info*); -extern void coprocessor_flush_all(struct thread_info*); +void coprocessor_flush(struct thread_info *ti, int cp_index); +void coprocessor_release_all(struct thread_info *ti); +void coprocessor_flush_all(struct thread_info *ti); =20 #endif /* XTENSA_HAVE_COPROCESSORS */ =20 --=20 2.30.2 From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A03BFC433EF for ; Sat, 16 Apr 2022 04:26:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbiDPE27 (ORCPT ); Sat, 16 Apr 2022 00:28:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230013AbiDPE2x (ORCPT ); Sat, 16 Apr 2022 00:28:53 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1239FFDE31 for ; Fri, 15 Apr 2022 21:26:21 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id mp16-20020a17090b191000b001cb5efbcab6so13123895pjb.4 for ; Fri, 15 Apr 2022 21:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fLOYNCP7bM0FoGD+XOolwlv66QCUuV6ytlu1gwN0Oh4=; b=NHsvKhHTUbORcEoJwhAnGbbF8gmfK9OYprcI7r9vlmjXQxus3ssM3YTtoAyFfzU8/W 1BKp+cei12Kk+w6n9V/mDRHYdX9H4ZRO1QTAjxsXxVHhtqdSwTCJ9wd1PwoX7iUhOeTm hxsy1dcYTh6zEKGZ+cyo9sUr/xAe9+DELAYDCfz8xqni1PskI/7yj19tlAL5SsL2wBIX XkuGRQCPuk4cUq6/LgtHNwrO5hF8ucM+g0QI1vEUn7O8jEf00tXU8azyfGRoQgpwTi86 5hLnXANVgexD6TYfCVEYiOUDf/Z3MDXrQSn/38gC34AYU90x0iIu76sZI9MzDL3DHPiB ppGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fLOYNCP7bM0FoGD+XOolwlv66QCUuV6ytlu1gwN0Oh4=; b=gayRVBu3AORB+N3qiVNDmOhY/2qXN7/iidyl0DaTNeYuCmwOyacMj2w0BsLADMhlw1 oSAuptTAvn6PYdQg+YK37UPSK75RMC3duWumfLJsH6ibSseonIrBDCPiXcXyP8jnMFww fjFQd9d+49LF9UWplj4fWxwrZNLnuI3PNeQLPeIEhO7V7CXx99iHj+b+AD15zq7iCtq6 nxqyMCimFDR601f17brU8nMLl9tHcm5RvjmCf+tk2slAHH2o53PofQEsqGALBIhBYCug TCHNNv/KBMvycH3OyzdFGQgiXGttefs46kCQNxMgcFs4mMCIGFoXmxZt+BA4qiLcv3dm Fm2g== X-Gm-Message-State: AOAM530YMaUmRGmpKzkCp9umSSKBnXIB/KpnT+ZoabrkW9m/BI0g/Mxz xYySeNmnVICxZ6MlvLoeNWQ= X-Google-Smtp-Source: ABdhPJwOguSHns23VNXqf0tYW5LRtEWg9kZeeEAlGWqRbhDqrFqLHzispLN0tQF6/xHgA9X6S/SEXA== X-Received: by 2002:a17:903:31d5:b0:158:27f4:fc9f with SMTP id v21-20020a17090331d500b0015827f4fc9fmr1916983ple.60.1650083181445; Fri, 15 Apr 2022 21:26:21 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:9b6:6aad:72f6:6e16]) by smtp.gmail.com with ESMTPSA id d8-20020aa78688000000b00505793566f7sm4258513pfo.211.2022.04.15.21.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 21:26:20 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 3/6] xtensa: clean up excsave1 initialization Date: Fri, 15 Apr 2022 21:25:56 -0700 Message-Id: <20220416042559.2035015-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use xtensa_set_sr instead of inline assembly. Rename local variable exc_table in early_trap_init to avoid conflict with per-CPU variable of the same name. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/traps.h | 4 ++-- arch/xtensa/kernel/traps.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index 6fa47cd8e02d..c9c5f59db420 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -45,11 +45,11 @@ void fast_second_level_miss(void); /* Initialize minimal exc_table structure sufficient for basic paging */ static inline void __init early_trap_init(void) { - static struct exc_table exc_table __initdata =3D { + static struct exc_table init_exc_table __initdata =3D { .fast_kernel_handler[EXCCAUSE_DTLB_MISS] =3D fast_second_level_miss, }; - __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (&exc_table)); + xtensa_set_sr(&init_exc_table, excsave1); } =20 void secondary_trap_init(void); diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index a85992d60c11..f6855eb92614 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -386,8 +386,7 @@ void * __init trap_set_handler(int cause, void *handler) =20 static void trap_init_excsave(void) { - unsigned long excsave1 =3D (unsigned long)this_cpu_ptr(&exc_table); - __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1)); + xtensa_set_sr(this_cpu_ptr(&exc_table), excsave1); } =20 static void trap_init_debug(void) --=20 2.30.2 From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 581B6C433F5 for ; Sat, 16 Apr 2022 04:26:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbiDPE3D (ORCPT ); Sat, 16 Apr 2022 00:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbiDPE2x (ORCPT ); Sat, 16 Apr 2022 00:28:53 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C17310EDFD for ; Fri, 15 Apr 2022 21:26:23 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id r66so9618323pgr.3 for ; Fri, 15 Apr 2022 21:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Y9Xga+Vf57beXiQKhYl2BdatYUIL77DBx/0ziFkle0=; b=Tis1KX6EZl0CEKsRc59x2S7dPKnR1WEi934au/E3F0d/WbgTIwTiOB8mewL/VD91Xs NVNfuXcfxjgdV732Lu5b4Cl4SjcXXhDmgDmEfFQYnwEEITd8cRsddJLvRqQeB1nN5UfY 1GhLBRb5baZWBJzDprbY1pFcugB/2KldCaTKCxhaYZaG80vcMypoQfzg8fuiGo9eGB7r yQ33Hv8IcLj2cP6UQGxKoI91xU8CBE3c1FBGN5nCn05e8F4PyMKg9z8DHT1FEG4BABJq P7AQC1/5enx+JxOt1ehoUlnvz+mHnSvg7RW7vJkdjXE/8EGXtyRNu0EiAkzfxqbCsYFg Kp6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Y9Xga+Vf57beXiQKhYl2BdatYUIL77DBx/0ziFkle0=; b=RQqunYsz3TNA5AVuvKcQPiYosRnTG/yx0IHYg1m4PHx0LVsWUjVjliLPEjZbPcRrO3 oEgeNQ1dCnbNDRo5loEaSeV4Ntgs3vFbzf+pXfgIJt5DCN/pfEbopx9Dk8csvNT1mYVc jiV1CE5UddsDJhpRejPps/ADrwMGH3U8ylHuZP8SLe08vGKsQGcrVH58/PDS8x2I11tV BzOQNoAt4y0RaJbRIcqlyaI0QD5Q03YbmoHvIM3DqGiP/OhEiq2LITxWp3lOSrPvnm3s JIb2OqVy8CfnBZRbd8GqDmiJcpB7mBinORANq+JSpGduafaB4xZqDEtvTA3k7KVLfP9v RSgQ== X-Gm-Message-State: AOAM531thWV78hUMc35zgYtqZBIiRb9sJSmRNlnzWiY2d9Y0qjsOJNOY AAtqp2+dJLKs6ray1PwtJ9Y= X-Google-Smtp-Source: ABdhPJzs20s1Cgi6+nhy2Ypz5w/vabzPPHK2gOCRWBPzkbrazPbW8gPzGN4vpGLDMJuD6Rhpas8fZQ== X-Received: by 2002:a05:6a00:2391:b0:50a:3ea9:e84d with SMTP id f17-20020a056a00239100b0050a3ea9e84dmr2185640pfc.21.1650083182710; Fri, 15 Apr 2022 21:26:22 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:9b6:6aad:72f6:6e16]) by smtp.gmail.com with ESMTPSA id d8-20020aa78688000000b00505793566f7sm4258513pfo.211.2022.04.15.21.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 21:26:22 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 4/6] xtensa: use callx0 opcode in fast_coprocessor Date: Fri, 15 Apr 2022 21:25:57 -0700 Message-Id: <20220416042559.2035015-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of emulating call0 in fast_coprocessor use that opcode directly. Use 'ret' instead of 'jx a0'. Signed-off-by: Max Filippov --- arch/xtensa/kernel/coprocessor.S | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index c7b9f12896f2..8bcbabbff38a 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -30,7 +30,7 @@ .align 4; \ .Lsave_cp_regs_cp##x: \ xchal_cp##x##_store a2 a3 a4 a5 a6; \ - jx a0; \ + ret; \ .endif =20 #define SAVE_CP_REGS_TAB(x) \ @@ -47,7 +47,7 @@ .align 4; \ .Lload_cp_regs_cp##x: \ xchal_cp##x##_load a2 a3 a4 a5 a6; \ - jx a0; \ + ret; \ .endif =20 #define LOAD_CP_REGS_TAB(x) \ @@ -163,21 +163,20 @@ ENTRY(fast_coprocessor) s32i a5, a4, THREAD_CPENABLE =20 /* - * Get context save area and 'call' save routine.=20 + * Get context save area and call save routine. * (a4 still holds previous owner (thread_info), a3 CP number) */ =20 movi a5, .Lsave_cp_regs_jump_table - movi a0, 2f # a0: 'return' address addx8 a3, a3, a5 # a3: coprocessor number l32i a2, a3, 4 # a2: xtregs offset l32i a3, a3, 0 # a3: jump address add a2, a2, a4 - jx a3 + callx0 a3 =20 /* Note that only a0 and a1 were preserved. */ =20 -2: rsr a3, exccause + rsr a3, exccause addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED movi a0, coprocessor_owner addx4 a0, a3, a0 @@ -187,19 +186,18 @@ ENTRY(fast_coprocessor) 1: GET_THREAD_INFO (a4, a1) s32i a4, a0, 0 =20 - /* Get context save area and 'call' load routine. */ + /* Get context save area and call load routine. */ =20 movi a5, .Lload_cp_regs_jump_table - movi a0, 1f addx8 a3, a3, a5 l32i a2, a3, 4 # a2: xtregs offset l32i a3, a3, 0 # a3: jump address add a2, a2, a4 - jx a3 + callx0 a3 =20 /* Restore all registers and return from exception handler. */ =20 -1: l32i a6, a1, PT_AREG6 + l32i a6, a1, PT_AREG6 l32i a5, a1, PT_AREG5 l32i a4, a1, PT_AREG4 =20 --=20 2.30.2 From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10487C433EF for ; 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Fri, 15 Apr 2022 21:26:23 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 5/6] xtensa: add xtensa_xsr macro Date: Fri, 15 Apr 2022 21:25:58 -0700 Message-Id: <20220416042559.2035015-6-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtensa_xsr does the XSR instruction for the specified special register. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/processor.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/= processor.h index 4489a27d527a..76bc63127c66 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -246,6 +246,13 @@ extern unsigned long __get_wchan(struct task_struct *p= ); v; \ }) =20 +#define xtensa_xsr(x, sr) \ + ({ \ + unsigned int __v__ =3D (unsigned int)(x); \ + __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \ + __v__; \ + }) + #if XCHAL_HAVE_EXTERN_REGS =20 static inline void set_er(unsigned long value, unsigned long addr) --=20 2.30.2 From nobody Thu Jun 18 19:07:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C0E9C433EF for ; Sat, 16 Apr 2022 04:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230017AbiDPE3L (ORCPT ); Sat, 16 Apr 2022 00:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230031AbiDPE25 (ORCPT ); Sat, 16 Apr 2022 00:28:57 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDF0210FDC5 for ; Fri, 15 Apr 2022 21:26:25 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id q12so9588669pgj.13 for ; Fri, 15 Apr 2022 21:26:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0btSP+exSEnJoJwm80JMqbXTxt3SdLF14yl5KtJTWc8=; b=Dz9+tCwkww74TeicnNLlq08qOU8uJnd1GOLVlXDqv/o+1B09tEPoV+5OrLqJK8AwFJ hO6EFk+RowmFjqFi4IyhFE2UDnjxnNOKQfyh76hcyiELiz4zTteGwIFQ8QkCi65Za7gR suqhOExWns/QiEeXj3BEJ4TBZFEZjIgcSL/X3etvm0jPL1D3D4hSmLif7/BzVR/sP/gv 5hpyCjgTUS3cmTD+LYViWatEfprQ8HRNBGud7xwsuf1K/DRVYzFV6688zx3qoMkUs7oQ B1MI8G1IQZWPnqbW74uNy3HCJx+1ZGKiF806DeFh1hQF9AuE1/itKNh+uYtPnHWbSO7a jL9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0btSP+exSEnJoJwm80JMqbXTxt3SdLF14yl5KtJTWc8=; b=DL8YI9e2ufqs5WFeNJy12n6fa8bQBmjw0zL2tz5W/1fqoFAEK09PztWjof/k2bw29w buXCCh7MccXJV6nbD8jzoeMi1TcwjiNX2ypojPTJSbc77l+iBmcQGMLk7Iaj/yM4Vag4 2qNzLC22KWnwCIErrjlw6rRtdmu4CgqbDubPXSNuC2vmQ2bt//5B69XbVRg3M1aGEHvT LUCIPtudtkpOP6PBiYf2LGNzPkSWCqoWoyICY2az+hti2Aveks8eG6nmio30rk1KZfy7 YWFEqMzDIkiPMXkRYIiaWOo9/PnvlYfcZM5LB9HJ48AhlHjSD65uxmJs11thYYF8A3L8 pixA== X-Gm-Message-State: AOAM530Tial9aMPQlaGGC53G0QVR1ALFADYvSo9sonUmqH807hoeFGws WbnYK1kEyxSDhd0OgA5187Tew9jGMhM= X-Google-Smtp-Source: ABdhPJxHKlmEu3pOcLG2uWvFqqtwJqU/JEaCkyF51Lx4B2mPmnxxm97BsjoY434nCp8D0qMRx5MIrw== X-Received: by 2002:a65:53cc:0:b0:382:8506:f1a6 with SMTP id z12-20020a6553cc000000b003828506f1a6mr1708797pgr.44.1650083185271; Fri, 15 Apr 2022 21:26:25 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:641:401:1d20:9b6:6aad:72f6:6e16]) by smtp.gmail.com with ESMTPSA id d8-20020aa78688000000b00505793566f7sm4258513pfo.211.2022.04.15.21.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 21:26:24 -0700 (PDT) From: Max Filippov To: linux-xtensa@linux-xtensa.org Cc: Chris Zankel , linux-kernel@vger.kernel.org, Max Filippov Subject: [PATCH 6/6] xtensa: support coprocessors on SMP Date: Fri, 15 Apr 2022 21:25:59 -0700 Message-Id: <20220416042559.2035015-7-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220416042559.2035015-1-jcmvbkbc@gmail.com> References: <20220416042559.2035015-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Current coprocessor support on xtensa only works correctly on uniprocessor configurations. Make it work on SMP too and keep it lazy. Make coprocessor_owner array per-CPU and move it to struct exc_table for easy access from the fast_coprocessor exception handler. Allow task to have live coprocessors only on single CPU, record this CPU number in the struct thread_info::cp_owner_cpu. Change struct thread_info::cpenable meaning to be 'coprocessors live on cp_owner_cpu'. Introduce C-level coprocessor exception handler that flushes and releases live coprocessors of the task taking 'coprocessor disabled' exception and call it from the fast_coprocessor handler when the task has live coprocessors on other CPU. Make coprocessor_flush_all and coprocessor_release_all work correctly when called from any CPU by sending IPI to the cp_owner_cpu. Add coprocessor_flush_release_all to do flush followed by release efficiently. Signed-off-by: Max Filippov --- arch/xtensa/include/asm/coprocessor.h | 3 +- arch/xtensa/include/asm/thread_info.h | 7 ++- arch/xtensa/include/asm/traps.h | 7 +++ arch/xtensa/kernel/asm-offsets.c | 8 ++- arch/xtensa/kernel/coprocessor.S | 43 +++++++++++----- arch/xtensa/kernel/entry.S | 17 +++++++ arch/xtensa/kernel/process.c | 70 +++++++++++++++++---------- arch/xtensa/kernel/traps.c | 13 ++++- 8 files changed, 125 insertions(+), 43 deletions(-) diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/as= m/coprocessor.h index a360efced7e7..dc53bd015c5f 100644 --- a/arch/xtensa/include/asm/coprocessor.h +++ b/arch/xtensa/include/asm/coprocessor.h @@ -142,10 +142,11 @@ typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); =20 -extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; +struct thread_info; void coprocessor_flush(struct thread_info *ti, int cp_index); void coprocessor_release_all(struct thread_info *ti); void coprocessor_flush_all(struct thread_info *ti); +void coprocessor_flush_release_all(struct thread_info *ti); =20 #endif /* XTENSA_HAVE_COPROCESSORS */ =20 diff --git a/arch/xtensa/include/asm/thread_info.h b/arch/xtensa/include/as= m/thread_info.h index f6fcbba1d02f..52974317a6b6 100644 --- a/arch/xtensa/include/asm/thread_info.h +++ b/arch/xtensa/include/asm/thread_info.h @@ -52,12 +52,17 @@ struct thread_info { __u32 cpu; /* current CPU */ __s32 preempt_count; /* 0 =3D> preemptable,< 0 =3D> BUG*/ =20 - unsigned long cpenable; #if XCHAL_HAVE_EXCLUSIVE /* result of the most recent exclusive store */ unsigned long atomctl8; #endif =20 + /* + * If i-th bit is set then coprocessor state is loaded into the + * coprocessor i on CPU cp_owner_cpu. + */ + unsigned long cpenable; + u32 cp_owner_cpu; /* Allocate storage for extra user states and coprocessor states. */ #if XTENSA_HAVE_COPROCESSORS xtregs_coprocessor_t xtregs_cp; diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/trap= s.h index c9c5f59db420..6b292facf7a7 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -12,6 +12,7 @@ =20 #include =20 +struct thread_info; /* * Per-CPU exception handling data structure. * EXCSAVE1 points to it. @@ -25,6 +26,10 @@ struct exc_table { void *fixup; /* For passing a parameter to fixup */ void *fixup_param; +#if XTENSA_HAVE_COPROCESSORS + /* Pointers to owner struct thread_info */ + struct thread_info *coprocessor_owner[XCHAL_CP_MAX]; +#endif /* Fast user exception handlers */ void *fast_user_handler[EXCCAUSE_N]; /* Fast kernel exception handlers */ @@ -33,6 +38,8 @@ struct exc_table { void *default_handler[EXCCAUSE_N]; }; =20 +DECLARE_PER_CPU(struct exc_table, exc_table); + /* * handler must be either of the following: * void (*)(struct pt_regs *regs); diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offs= ets.c index 37278e2785fb..e3b9cf4c2289 100644 --- a/arch/xtensa/kernel/asm-offsets.c +++ b/arch/xtensa/kernel/asm-offsets.c @@ -91,10 +91,12 @@ int main(void) /* struct thread_info (offset from start_struct) */ DEFINE(THREAD_RA, offsetof (struct task_struct, thread.ra)); DEFINE(THREAD_SP, offsetof (struct task_struct, thread.sp)); - DEFINE(THREAD_CPENABLE, offsetof (struct thread_info, cpenable)); #if XCHAL_HAVE_EXCLUSIVE DEFINE(THREAD_ATOMCTL8, offsetof (struct thread_info, atomctl8)); #endif + DEFINE(THREAD_CPENABLE, offsetof(struct thread_info, cpenable)); + DEFINE(THREAD_CPU, offsetof(struct thread_info, cpu)); + DEFINE(THREAD_CP_OWNER_CPU, offsetof(struct thread_info, cp_owner_cpu)); #if XTENSA_HAVE_COPROCESSORS DEFINE(THREAD_XTREGS_CP0, offsetof(struct thread_info, xtregs_cp.cp0)); DEFINE(THREAD_XTREGS_CP1, offsetof(struct thread_info, xtregs_cp.cp1)); @@ -137,6 +139,10 @@ int main(void) DEFINE(EXC_TABLE_DOUBLE_SAVE, offsetof(struct exc_table, double_save)); DEFINE(EXC_TABLE_FIXUP, offsetof(struct exc_table, fixup)); DEFINE(EXC_TABLE_PARAM, offsetof(struct exc_table, fixup_param)); +#if XTENSA_HAVE_COPROCESSORS + DEFINE(EXC_TABLE_COPROCESSOR_OWNER, + offsetof(struct exc_table, coprocessor_owner)); +#endif DEFINE(EXC_TABLE_FAST_USER, offsetof(struct exc_table, fast_user_handler)); DEFINE(EXC_TABLE_FAST_KERNEL, diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coproces= sor.S index 8bcbabbff38a..1e2bfcf9f0cf 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -115,9 +115,32 @@ =20 ENTRY(fast_coprocessor) =20 + s32i a3, a2, PT_AREG3 + +#ifdef CONFIG_SMP + /* + * Check if any coprocessor context is live on another CPU + * and if so go through the C-level coprocessor exception handler + * to flush it to memory. + */ + + GET_THREAD_INFO (a0, a2) + l32i a3, a0, THREAD_CPENABLE + beqz a3, .Lload_local + l32i a3, a0, THREAD_CPU + l32i a0, a0, THREAD_CP_OWNER_CPU + beq a0, a3, .Lload_local + + rsr a0, ps + l32i a3, a2, PT_AREG3 + bbci.l a0, PS_UM_BIT, 1f + call0 user_exception +1: call0 kernel_exception +#endif + /* Save remaining registers a1-a3 and SAR */ =20 - s32i a3, a2, PT_AREG3 +.Lload_local: rsr a3, sar s32i a1, a2, PT_AREG1 s32i a3, a2, PT_SAR @@ -150,9 +173,9 @@ ENTRY(fast_coprocessor) =20 /* Retrieve previous owner. (a3 still holds CP number) */ =20 - movi a0, coprocessor_owner # list of owners + rsr a0, excsave1 # exc_table addx4 a0, a3, a0 # entry for CP - l32i a4, a0, 0 + l32i a4, a0, EXC_TABLE_COPROCESSOR_OWNER =20 beqz a4, 1f # skip 'save' if no previous owner =20 @@ -178,13 +201,15 @@ ENTRY(fast_coprocessor) =20 rsr a3, exccause addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED - movi a0, coprocessor_owner + rsr a0, excsave1 # exc_table addx4 a0, a3, a0 =20 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ =20 1: GET_THREAD_INFO (a4, a1) - s32i a4, a0, 0 + l32i a5, a4, THREAD_CPU + s32i a4, a0, EXC_TABLE_COPROCESSOR_OWNER + s32i a5, a4, THREAD_CP_OWNER_CPU =20 /* Get context save area and call load routine. */ =20 @@ -245,12 +270,4 @@ ENTRY(coprocessor_flush) =20 ENDPROC(coprocessor_flush) =20 - .data - -ENTRY(coprocessor_owner) - - .fill XCHAL_CP_MAX, 4, 0 - -END(coprocessor_owner) - #endif /* XTENSA_HAVE_COPROCESSORS */ diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index b9bcb2cd74dd..033443b4ce87 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -2087,9 +2087,26 @@ ENTRY(_switch_to) /* Switch CPENABLE */ =20 #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS) +#ifdef CONFIG_SMP l32i a3, a5, THREAD_CPENABLE + beqz a3, 1f + l32i a6, a5, THREAD_CP_OWNER_CPU + l32i a7, a5, THREAD_CPU + beq a6, a7, 1f # load 0 into CPENABLE if current CPU is not the owner + movi a3, 0 +1: xsr a3, cpenable + + l32i a6, a4, THREAD_CP_OWNER_CPU + l32i a7, a4, THREAD_CPU + bne a6, a7, 1f # skip saving CPENABLE if current CPU was not the owner s32i a3, a4, THREAD_CPENABLE +1: +#else + l32i a3, a5, THREAD_CPENABLE + xsr a3, cpenable + s32i a3, a4, THREAD_CPENABLE +#endif #endif =20 #if XCHAL_HAVE_EXCLUSIVE diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index e8bfbca5f001..a17c37fbd93c 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c @@ -47,6 +47,7 @@ #include #include #include +#include =20 extern void ret_from_fork(void); extern void ret_from_kernel_thread(void); @@ -63,52 +64,70 @@ EXPORT_SYMBOL(__stack_chk_guard); =20 #if XTENSA_HAVE_COPROCESSORS =20 -void coprocessor_release_all(struct thread_info *ti) +static void local_coprocessor_release_all(void *info) { - unsigned long cpenable; + struct thread_info *ti =3D info; + struct thread_info **coprocessor_owner; int i; =20 - /* Make sure we don't switch tasks during this operation. */ - - preempt_disable(); + coprocessor_owner =3D this_cpu_ptr(&exc_table)->coprocessor_owner; =20 /* Walk through all cp owners and release it for the requested one. */ =20 - cpenable =3D ti->cpenable; - for (i =3D 0; i < XCHAL_CP_MAX; i++) { - if (coprocessor_owner[i] =3D=3D ti) { - coprocessor_owner[i] =3D 0; - cpenable &=3D ~(1 << i); - } + if (coprocessor_owner[i] =3D=3D ti) + coprocessor_owner[i] =3D NULL; } - - ti->cpenable =3D cpenable; + ti->cpenable =3D 0; if (ti =3D=3D current_thread_info()) xtensa_set_sr(0, cpenable); +} =20 - preempt_enable(); +void coprocessor_release_all(struct thread_info *ti) +{ + if (ti->cpenable) + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_release_all, + ti, true); } =20 -void coprocessor_flush_all(struct thread_info *ti) +static void local_coprocessor_flush_all(void *info) { - unsigned long cpenable, old_cpenable; + struct thread_info *ti =3D info; + struct thread_info **coprocessor_owner; + unsigned long old_cpenable; int i; =20 - preempt_disable(); - - old_cpenable =3D xtensa_get_sr(cpenable); - cpenable =3D ti->cpenable; - xtensa_set_sr(cpenable, cpenable); + coprocessor_owner =3D this_cpu_ptr(&exc_table)->coprocessor_owner; + old_cpenable =3D xtensa_xsr(ti->cpenable, cpenable); =20 for (i =3D 0; i < XCHAL_CP_MAX; i++) { - if ((cpenable & 1) !=3D 0 && coprocessor_owner[i] =3D=3D ti) + if (coprocessor_owner[i] =3D=3D ti) coprocessor_flush(ti, i); - cpenable >>=3D 1; } xtensa_set_sr(old_cpenable, cpenable); +} + +void coprocessor_flush_all(struct thread_info *ti) +{ + if (ti->cpenable) + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_flush_all, + ti, true); +} =20 - preempt_enable(); +static void local_coprocessor_flush_release_all(void *info) +{ + local_coprocessor_flush_all(info); + local_coprocessor_release_all(info); +} + +void coprocessor_flush_release_all(struct thread_info *ti) +{ + if (ti->cpenable) + smp_call_function_single(ti->cp_owner_cpu, + local_coprocessor_flush_release_all, + ti, true); } =20 #endif @@ -140,8 +159,7 @@ void flush_thread(void) { #if XTENSA_HAVE_COPROCESSORS struct thread_info *ti =3D current_thread_info(); - coprocessor_flush_all(ti); - coprocessor_release_all(ti); + coprocessor_flush_release_all(ti); #endif flush_ptrace_hw_breakpoint(current); } diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index f6855eb92614..9b8a76d4fc05 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -72,6 +72,9 @@ static void do_nmi(struct pt_regs *regs); static void do_unaligned_user(struct pt_regs *regs); #endif static void do_multihit(struct pt_regs *regs); +#if XTENSA_HAVE_COPROCESSORS +static void do_coprocessor(struct pt_regs *regs); +#endif static void do_debug(struct pt_regs *regs); =20 /* @@ -84,7 +87,8 @@ static void do_debug(struct pt_regs *regs); #define USER 0x02 =20 #define COPROCESSOR(x) \ -{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor }, \ +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, 0, do_coprocessor } =20 typedef struct { int cause; @@ -342,6 +346,13 @@ static void do_unaligned_user(struct pt_regs *regs) } #endif =20 +#if XTENSA_HAVE_COPROCESSORS +static void do_coprocessor(struct pt_regs *regs) +{ + coprocessor_flush_release_all(current_thread_info()); +} +#endif + /* Handle debug events. * When CONFIG_HAVE_HW_BREAKPOINT is on this handler is called with * preemption disabled to avoid rescheduling and keep mapping of hardware --=20 2.30.2