From nobody Mon May 11 03:40:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50BBEC433F5 for ; Fri, 15 Apr 2022 14:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354746AbiDOOeO (ORCPT ); Fri, 15 Apr 2022 10:34:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354759AbiDOOeI (ORCPT ); Fri, 15 Apr 2022 10:34:08 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 898A3D3AFE; Fri, 15 Apr 2022 07:31:28 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23FATHme003966; Fri, 15 Apr 2022 07:31:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kQa1/fI8r7R7SSHsQpLYhMScAwHxIdb1Nb1bGo1gqx0=; b=Afq0MHl7Xpci6PQQ9l675E2A1zsFgbLddECZrB7QNaYhD02et4wtN9i9Ud7kuEbyR8HT TVepFMwmmGl1IPUFotfDA1pgy8OfGQERkECoA6fvxni4qS7kq1j3nGVJHmvvNZkEgxA0 l41GotYQ6PlGPhGSnWoH67qFMDyb8hrmantjJWGvcDbu+mRNvwC1TLSNuwD+HgTy/TU2 94j+aPPGsrmN82O2nqJd27PXzfHgHMDL72C37HyqhzRU6bVShweOKoeR/XtyvfGAeldc ko3e3t50mc3hXOK1uUBy2TYG3CptFcikZmLTZynM3WowE11XZA53XzT5usN8Z8hEvH1r nw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fdw7ej6kx-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 15 Apr 2022 07:31:03 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 15 Apr 2022 07:31:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 15 Apr 2022 07:31:01 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 8EB5B3F706C; Fri, 15 Apr 2022 07:31:01 -0700 (PDT) From: Piyush Malgujar To: , CC: , Piyush Malgujar , "Damian Eppel" , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , Paolo Abeni Subject: [PATCH] Marvell MDIO clock related changes. Date: Fri, 15 Apr 2022 07:30:26 -0700 Message-ID: <20220415143026.11088-1-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: bE6rxzjobvtJfhLz4qN_-LMDzm6fWtav X-Proofpoint-ORIG-GUID: bE6rxzjobvtJfhLz4qN_-LMDzm6fWtav X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-15_05,2022-04-15_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch includes following support related to MDIO Clock: 1) clock gating: The purpose of this change is to apply clock gating for MDIO clock when the= re is no transaction happening. This will stop the MDC clock toggling in idle scenario. 2) Marvell MDIO clock frequency attribute change: This MDIO change provides an option for user to have the bus speed set to t= heir needs which is otherwise set to default(3.125 MHz). In case someone needs to use this attribute, they ha= ve to add an extra attribute clock-freq in the mdio entry in their DTS and this driver will support the rest. The changes are made in a way that the clock will set to the nearest possib= le value based on the clock calculation and required frequency from DTS. Below are some possible values: default:3.125 MHz Max:16.67 MHz These changes has been verified internally with Marvell SoCs 9x and 10x ser= ies. Signed-off-by: Piyush Malgujar Signed-off-by: Damian Eppel --- drivers/net/mdio/mdio-cavium.h | 1 + drivers/net/mdio/mdio-thunder.c | 65 +++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/mdio/mdio-cavium.h b/drivers/net/mdio/mdio-cavium.h index a2245d436f5dae4d6424b7c7bfca0aa969a3b3ad..ed4c48d8a38bd80e6a169f7a6d9= 0c1f2a0daccfc 100644 --- a/drivers/net/mdio/mdio-cavium.h +++ b/drivers/net/mdio/mdio-cavium.h @@ -92,6 +92,7 @@ struct cavium_mdiobus { struct mii_bus *mii_bus; void __iomem *register_base; enum cavium_mdiobus_mode mode; + u32 clk_freq; }; =20 #ifdef CONFIG_CAVIUM_OCTEON_SOC diff --git a/drivers/net/mdio/mdio-thunder.c b/drivers/net/mdio/mdio-thunde= r.c index 822d2cdd2f3599025f3e79d4243337c18114c951..642d08aff3f7f849102992a8917= 90e900b111d5c 100644 --- a/drivers/net/mdio/mdio-thunder.c +++ b/drivers/net/mdio/mdio-thunder.c @@ -19,6 +19,46 @@ struct thunder_mdiobus_nexus { struct cavium_mdiobus *buses[4]; }; =20 +#define _calc_clk_freq(_phase) (100000000U / (2 * (_phase))) +#define _calc_sample(_phase) (2 * (_phase) - 3) + +#define PHASE_MIN 3 +#define PHASE_DFLT 16 +#define DFLT_CLK_FREQ _calc_clk_freq(PHASE_DFLT) +#define MAX_CLK_FREQ _calc_clk_freq(PHASE_MIN) + +static inline u32 _config_clk(u32 req_freq, u32 *phase, u32 *sample) +{ + unsigned int p; + u32 freq =3D 0, freq_prev; + + for (p =3D PHASE_MIN; p < PHASE_DFLT; p++) { + freq_prev =3D freq; + freq =3D _calc_clk_freq(p); + + if (req_freq >=3D freq) + break; + } + + if (p =3D=3D PHASE_DFLT) + freq =3D DFLT_CLK_FREQ; + + if (p =3D=3D PHASE_MIN || p =3D=3D PHASE_DFLT) + goto out; + + /* Check which clock value from the identified range + * is closer to the requested value + */ + if ((freq_prev - req_freq) < (req_freq - freq)) { + p =3D p - 1; + freq =3D freq_prev; + } +out: + *phase =3D p; + *sample =3D _calc_sample(p); + return freq; +} + static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -59,6 +99,8 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, struct mii_bus *mii_bus; struct cavium_mdiobus *bus; union cvmx_smix_en smi_en; + union cvmx_smix_clk smi_clk; + u32 req_clk_freq; =20 /* If it is not an OF node we cannot handle it yet, so * exit the loop. @@ -87,6 +129,29 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pd= ev, bus->register_base =3D nexus->bar0 + r.start - pci_resource_start(pdev, 0); =20 + smi_clk.u64 =3D oct_mdio_readq(bus->register_base + SMI_CLK); + smi_clk.s.clk_idle =3D 1; + + if (!of_property_read_u32(node, "clock-freq", &req_clk_freq)) { + u32 phase, sample; + + dev_info(&pdev->dev, "requested bus clock frequency=3D%d\n", + req_clk_freq); + + bus->clk_freq =3D _config_clk(req_clk_freq, + &phase, &sample); + + smi_clk.s.phase =3D phase; + smi_clk.s.sample_hi =3D (sample >> 4) & 0x1f; + smi_clk.s.sample =3D sample & 0xf; + } else { + bus->clk_freq =3D DFLT_CLK_FREQ; + } + + oct_mdio_writeq(smi_clk.u64, bus->register_base + SMI_CLK); + dev_info(&pdev->dev, "bus clock frequency set to %d\n", + bus->clk_freq); + smi_en.u64 =3D 0; smi_en.s.en =3D 1; oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN); --=20 2.17.1