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Tested on Linux 5.18-rc2 Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- arch/arm64/boot/dts/arm/juno-base.dtsi | 162 +++++++++++++++++++++- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 ++++- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r1.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r2.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-scmi.dtsi | 25 ++++ arch/arm64/boot/dts/arm/juno.dts | 25 ++++ 8 files changed, 302 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/a= rm/juno-base.dtsi index 446c8f476eec..4f40a5c8f565 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -117,7 +117,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible =3D "arm,coresight-tmc", "arm,primecell"; reg =3D <0 0x20010000 0 0x1000>; =20 @@ -141,7 +141,7 @@ }; }; =20 - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible =3D "arm,coresight-tpiu", "arm,primecell"; reg =3D <0 0x20030000 0 0x1000>; =20 @@ -194,7 +194,7 @@ }; }; =20 - etr@20070000 { + etr_sys: etr@20070000 { compatible =3D "arm,coresight-tmc", "arm,primecell"; reg =3D <0 0x20070000 0 0x1000>; iommus =3D <&smmu_etr 0>; @@ -212,7 +212,7 @@ }; }; =20 - stm@20100000 { + stm_sys: stm@20100000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -289,6 +289,18 @@ }; }; =20 + cti0: cti@22020000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x22020000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; reg =3D <0 0x220c0000 0 0x1000>; @@ -349,6 +361,18 @@ }; }; =20 + cti1: cti@22120000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x22120000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; reg =3D <0x0 0x23010000 0x0 0x1000>; @@ -374,6 +398,18 @@ }; }; =20 + cti2: cti@23020000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x23020000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; reg =3D <0 0x230c0000 0 0x1000>; @@ -446,6 +482,18 @@ }; }; =20 + cti3: cti@23120000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x23120000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; reg =3D <0x0 0x23210000 0x0 0x1000>; @@ -471,6 +519,18 @@ }; }; =20 + cti4: cti@23220000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x23220000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible =3D "arm,coresight-cpu-debug", "arm,primecell"; reg =3D <0x0 0x23310000 0x0 0x1000>; @@ -496,6 +556,100 @@ }; }; =20 + cti5: cti@23320000 { + compatible =3D "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg =3D <0 0x23320000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + arm,cs-dev-assoc =3D <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0 0x20020000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs=3D<2 3>; + arm,trig-in-types=3D; + arm,trig-out-sigs=3D<0 1>; + arm,trig-out-types=3D; + arm,cs-dev-assoc =3D <&etr_sys>; + }; + + trig-conns@1 { + reg =3D <1>; + arm,trig-in-sigs=3D<0 1>; + arm,trig-in-types=3D; + arm,trig-out-sigs=3D<7 6>; + arm,trig-out-types=3D; + arm,cs-dev-assoc =3D <&etf_sys0>; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-in-sigs=3D<4 5 6 7>; + arm,trig-in-types=3D; + arm,trig-out-sigs=3D<4 5>; + arm,trig-out-types=3D; + arm,cs-dev-assoc =3D <&stm_sys>; + }; + + trig-conns@3 { + reg =3D <3>; + arm,trig-out-sigs=3D<2 3>; + arm,trig-out-types=3D; + arm,cs-dev-assoc =3D <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0 0x20110000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs=3D<0>; + arm,trig-in-types=3D; + arm,trig-out-sigs=3D<0>; + arm,trig-out-types=3D; + arm,trig-conn-name =3D "sys_profiler"; + }; + + trig-conns@1 { + reg =3D <1>; + arm,trig-out-sigs=3D<2 3>; + arm,trig-out-types=3D; + arm,trig-conn-name =3D "watchdog"; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-out-sigs=3D<1 6>; + arm,trig-out-types=3D; + arm,trig-conn-name =3D "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible =3D "arm,juno-mali", "arm,mali-t624"; reg =3D <0 0x2d000000 0 0x10000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dt= s/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; =20 - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible =3D "arm,coresight-tmc", "arm,primecell"; reg =3D <0 0x20140000 0 0x1000>; =20 @@ -82,4 +82,39 @@ =20 }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0 0x20160000 0 0x1000>; + + clocks =3D <&soc_smc50mhz>; + clock-names =3D "apb_pclk"; + power-domains =3D <&scpi_devpd 0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + trig-conns@0 { + reg =3D <0>; + arm,trig-in-sigs=3D<0 1>; + arm,trig-in-types=3D; + arm,trig-out-sigs=3D<0 1>; + arm,trig-out-types=3D; + arm,cs-dev-assoc =3D <&etf_sys1>; + }; + + trig-conns@1 { + reg =3D <1>; + arm,trig-in-sigs=3D<2 3 4>; + arm,trig-in-types=3D; + arm,trig-conn-name =3D "ela_clus_0"; + }; + + trig-conns@2 { + reg =3D <2>; + arm,trig-in-sigs=3D<5 6 7>; + arm,trig-in-types=3D; + arm,trig-conn-name =3D "ela_clus_1"; + }; + }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts= /arm/juno-r1-scmi.dts index fd1f0d26d751..dd9ea69f086f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -15,6 +15,10 @@ }; }; =20 +&cti_sys2 { + power-domains =3D <&scmi_devpd 8>; +}; + &A57_0 { clocks =3D <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/= juno-r1.dts index 0e24e29eb9b1..f099fb611d4e 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; =20 #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" =20 @@ -313,3 +314,27 @@ &cpu_debug5 { cpu =3D <&A53_3>; }; + +&cti0 { + cpu =3D <&A57_0>; +}; + +&cti1 { + cpu =3D <&A57_1>; +}; + +&cti2 { + cpu =3D <&A53_0>; +}; + +&cti3 { + cpu =3D <&A53_1>; +}; + +&cti4 { + cpu =3D <&A53_2>; +}; + +&cti5 { + cpu =3D <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts= /arm/juno-r2-scmi.dts index 35e6d4762c46..de2cbac1d1c3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -15,6 +15,10 @@ }; }; =20 +&cti_sys2 { + power-domains =3D <&scmi_devpd 8>; +}; + &A72_0 { clocks =3D <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/= juno-r2.dts index e609420ce3e4..709389582ae3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; =20 #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" =20 @@ -319,3 +320,27 @@ &cpu_debug5 { cpu =3D <&A53_3>; }; + +&cti0 { + cpu =3D <&A72_0>; +}; + +&cti1 { + cpu =3D <&A72_1>; +}; + +&cti2 { + cpu =3D <&A53_0>; +}; + +&cti3 { + cpu =3D <&A53_1>; +}; + +&cti4 { + cpu =3D <&A53_2>; +}; + +&cti5 { + cpu =3D <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/a= rm/juno-scmi.dtsi index d72dcff9bf06..4135d62e44a2 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -154,6 +154,31 @@ power-domains =3D <&scmi_devpd 8>; }; =20 +&cti0 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti1 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti2 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti3 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti4 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti5 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains =3D <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains =3D <&scmi_devpd 8>; +}; + &gpu { clocks =3D <&scmi_dvfs 2>; power-domains =3D <&scmi_devpd 9>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/jun= o.dts index f00cffbd032c..dbc22e70b62c 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; =20 #include +#include #include "juno-base.dtsi" =20 / { @@ -295,3 +296,27 @@ &cpu_debug5 { cpu =3D <&A53_3>; }; + +&cti0 { + cpu =3D <&A57_0>; +}; + +&cti1 { + cpu =3D <&A57_1>; +}; + +&cti2 { + cpu =3D <&A53_0>; +}; + +&cti3 { + cpu =3D <&A53_1>; +}; + +&cti4 { + cpu =3D <&A53_2>; +}; + +&cti5 { + cpu =3D <&A53_3>; +}; --=20 2.17.1