From nobody Mon May 11 07:46:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E76C433F5 for ; Wed, 13 Apr 2022 02:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231652AbiDMCIl (ORCPT ); Tue, 12 Apr 2022 22:08:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231637AbiDMCId (ORCPT ); Tue, 12 Apr 2022 22:08:33 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 293343465B for ; Tue, 12 Apr 2022 19:06:14 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id k14so463875pga.0 for ; Tue, 12 Apr 2022 19:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/z6VCNILZAmJ4nVoBo0dJpxo2XYMU5Usk4gCsaeE6Yw=; b=auXusTGGPpWbx4FwMgi5fRIZsIeipynBmzmyIDxiUooF2PV8PMpBeEVJ0sRXhw5ICA UWtAPsflTpFfpwkfyZfFNFtO1ENsDt0vNXZDyRokkv1k6mFErkNjU6n/lrXO8oDp2JUM ujQL/JFcCDgtZFP/3YktMkV7T+/qJIZLWk3DKIFryg7uDitjf+cmMpVopCvoKkS9yo8c gEoJ8x+cYsQdvOC0GeAQypfM3cuFTwmrZhYxO1tTCa+59G6qxqYgeWU6Sqh54bU39eEI SirmqncSv3lHmfD+8an/b2UeZMYzt4CWeqjKgzCTXvwQeBBu+BfH9th75BfpFb9DkyGj tz6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/z6VCNILZAmJ4nVoBo0dJpxo2XYMU5Usk4gCsaeE6Yw=; b=weqdlLp7rTMUC28rb1fJAMTyhtvdBP6YIYsQlsxJX4566E/C3mZuD9YPSG08HOfqbv TEbFKVSBr7nu8vWgSmvr/zTUHR8mD1cJ1s7GFJqDY0rT7wiwensWcQAMbTVWGiyPbGwX 8dLVTS4ZMqJG2SF7xkDeIolpi3RGBvLbFwXZuQfIIMiQzNO1OIUEIjwMI434pDz9Tk+I UM/YRHN5lIHkEZSl71jHgCJwzYfdvzMquzTza7VE+pwdTbDRs7YxbQ8Ek6lvnD6mzmBm b0gcn44lmtdJIvj8qpi/ht7NNjF3UCyrLjQcy9gVo4anggKY2Q6jxgAd0bDWXN4y3qdl dV7w== X-Gm-Message-State: AOAM531Se/0Dqn3GZetrugJjvgCyilIGM4ImGmEbpl8zSpGfI2Ejysen 88OV06TxZue+cDBGqcAprgyWfQ== X-Google-Smtp-Source: ABdhPJxQPVLpGODV8SB3q39sdBBl2uibExiZ7AvCqsVWcqRCdtg8V77GJtTIS2/aqARtKZry7HIYRQ== X-Received: by 2002:a65:6d0a:0:b0:382:28b6:7baa with SMTP id bf10-20020a656d0a000000b0038228b67baamr32280131pgb.486.1649815573652; Tue, 12 Apr 2022 19:06:13 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1001:7090:669f:cec7:c0c2:1cc]) by smtp.gmail.com with ESMTPSA id o3-20020aa79783000000b00505f720bb76sm4234053pfp.215.2022.04.12.19.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 19:06:13 -0700 (PDT) From: Drew Fustini To: Rob Herring , Krzysztof Kozlowski , Dave Gerlach , Tony Lindgren , Nishanth Menon , Santosh Shilimkar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Drew Fustini Subject: [PATCH 1/2] dt-bindings: wkup-m3-ipc: Add ti,io-isolation property Date: Tue, 12 Apr 2022 19:06:40 -0700 Message-Id: <20220413020641.2789408-2-dfustini@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220413020641.2789408-1-dfustini@baylibre.com> References: <20220413020641.2789408-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation for the ti,io-isolation DT property on the wkup_m3_ipc node which tells the wkup_m3_ipc driver to use the wkup_m3 to enable IO Isolation during low power mode transitions on am43xx platforms. Signed-off-by: Dave Gerlach [dfustini: convert to YAML, make DTS example that passes check] Signed-off-by: Drew Fustini --- .../bindings/soc/ti/wkup-m3-ipc.yaml | 68 +++++++++++++++++-- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml b/Do= cumentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml index 7f4a75c5fcaa..30a65b75c024 100644 --- a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml @@ -24,14 +24,22 @@ description: |+ A wkup_m3_ipc device node is used to represent the IPC registers within = an SoC. =20 - Support for VTT Toggle - =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Support for VTT Toggle with GPIO pin + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin = is connected to the enable pin on the DDR VTT regulator. This allows the regulator to be disabled upon suspend and enabled upon resume. Please no= te that the GPIO pin must be part of the GPIO0 module as only this GPIO mod= ule is in the wakeup power domain. =20 + Support for IO Isolation + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + On AM437x SoCs, certain pins can be forced into an alternate state when = IO + isolation is activated. Those pins have pad control registers prefixed by + 'CTRL_CONF_' that contain DS0 (e.g. deep sleep) configuration bits that = can + override the pin's existing bias (pull-up/pull-down) and value (high/low= ) when + IO isolation is active. + properties: compatible: enum: @@ -63,6 +71,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: GPIO pin connected to enable pin on VTT regulator =20 + ti,set-io-isolation: + type: boolean + description: + If this property is present, then the wkup_m3_ipc driver will instru= ct + the CM3 firmware to activate IO isolation when suspending to deep sl= eep. + This can be leveraged by a board design to put other devices on the = board + into a low power state. + required: - compatible - reg @@ -74,21 +90,63 @@ additionalProperties: false =20 examples: - | + /* Example for AM335x SoC */ soc { #address-cells =3D <1>; #size-cells =3D <1>; =20 - mailbox: mailbox { + am335x_mailbox: mailbox { #mbox-cells =3D <1>; }; =20 - wkup_m3_ipc: wkup_m3_ipc@1324 { + wkup_m3_ipc@1324 { compatible =3D "ti,am3352-wkup-m3-ipc"; reg =3D <0x1324 0x24>; interrupts =3D <78>; ti,rproc =3D <&wkup_m3>; - mboxes =3D <&mailbox &mbox_wkupm3>; + mboxes =3D <&am335x_mailbox &mbox_wkupm3>; ti,vtt-gpio-pin =3D <7>; }; }; + + - | + /* + * Example for AM473x SoC: + * On the AM437x-GP-EVM board, gpio5_7 is wired to enable pin of the D= DR VTT + * regulator. The 'ddr_vtt_toggle_default' pinmux node configures gpio= 5_7 + * for pull-up during normal system operation. However, the DS0 (deep = sleep) + * state of the pin is configured for pull-down and thus the VTT regul= ator + * will be disabled to save power when IO isolation is active. Note th= at + * this method is an alternative to using the 'ti,vtt-gpio-pin' proper= ty. + */ + #include + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + am437x_mailbox: mailbox { + #mbox-cells =3D <1>; + }; + + am43xx_pinmux { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ddr3_vtt_toggle_default>; + + ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + pinctrl-single,pins =3D < + 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_F= ORCE_OFF_MODE | MUX_MODE7) + >; + }; + }; + + wkup_m3_ipc@1324 { + compatible =3D "ti,am4372-wkup-m3-ipc"; + reg =3D <0x1324 0x24>; + interrupts =3D <78>; + ti,rproc =3D <&wkup_m3>; + mboxes =3D <&am437x_mailbox &mbox_wkupm3>; + ti,set-io-isolation; + }; + }; + ... --=20 2.32.0 From nobody Mon May 11 07:46:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08BEDC433EF for ; Wed, 13 Apr 2022 02:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231658AbiDMCIm (ORCPT ); Tue, 12 Apr 2022 22:08:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231644AbiDMCIf (ORCPT ); Tue, 12 Apr 2022 22:08:35 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFE8D2613D for ; Tue, 12 Apr 2022 19:06:15 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id be5so662738plb.13 for ; Tue, 12 Apr 2022 19:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nzvi/7I6o4g6gT+tWp3ktIpiQNQJRFeE4veqO2lT0Cg=; b=eKqKjAr4pOgRkVvIywuOKZrA+1JkHZeB4DPvaRtX84pupA4Xh5uCCFwBf/j/bXki4E zoeT5mfIoFWi8E1Sh5ibmDqxmgTg7YwjJRpXDwCWIW3g6evCufRybe/GWHJvsKwiPsd9 Kp/8cBV9wAGkugBu0ibCIvB8Z1tDuVuvQoWmgDZewT9BYepvWDzLydrACLsatYhAzRTs d2XwCkg9PxcJZ3/uj2bJkFnCzV8JtQ/LwDQ2gHzyGuTodr/DAUqYgZLF0X1PRKJRUMrI xEqo6ofkXQsE+RkQLqKelZGTcOEsKc+421+M2mg8Mpmu08vZDHDhTXmkkHp9UN0fnz9c VZLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nzvi/7I6o4g6gT+tWp3ktIpiQNQJRFeE4veqO2lT0Cg=; b=8PJ02E6D5GqZ4uo5y77R4TLC4VRq02e0TqrddDbCiOAF1DsbFgqmygT9WUFpjeXeSd se8EYyzRTSywiJ14o/AKIQa8XifKq4fnKZRcI5mm0sjPyR+jn2S+yaSqO3YoOwJ79Tml q7KuEV8bcphmAd6edEzAYeBjA2Uv7vUCseayFT27E1c55yoOB6k9l3LY0ZNNRz3S8V8A PF8IXAa13KRNdsuI5GC1a6Z2+LrQ0XpJTAJrWkl3iR9MQCMZN7UuAmC23n2j5jxKg3Vz K0VDaOBZXoryNxaAJMzYSUsBmH8wPkCUglha7f4CDOdJEzyWHsV/7KsD5hx7Foe/Ex3d QZwg== X-Gm-Message-State: AOAM533/tekrb9Zu0206SxhXm6teu1M8YsXO8DAIYEmIU39H7QfHc6XO UvGAq77/iE2G0N34EYRAaHF9wQ== X-Google-Smtp-Source: ABdhPJz4RdYgxf39eBGJAQQcu/L60B2/GMbOeS1p/vMQQ88FQqB1pwtDxzR3Z9fyqDxnG04Jk8W7+w== X-Received: by 2002:a17:90b:1642:b0:1c7:2497:3807 with SMTP id il2-20020a17090b164200b001c724973807mr8088350pjb.176.1649815575283; Tue, 12 Apr 2022 19:06:15 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1001:7090:669f:cec7:c0c2:1cc]) by smtp.gmail.com with ESMTPSA id o3-20020aa79783000000b00505f720bb76sm4234053pfp.215.2022.04.12.19.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 19:06:14 -0700 (PDT) From: Drew Fustini To: Rob Herring , Krzysztof Kozlowski , Dave Gerlach , Tony Lindgren , Nishanth Menon , Santosh Shilimkar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Drew Fustini , Keerthy Subject: [PATCH 2/2] soc: ti: wkup_m3_ipc: Add support for IO Isolation Date: Tue, 12 Apr 2022 19:06:41 -0700 Message-Id: <20220413020641.2789408-3-dfustini@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220413020641.2789408-1-dfustini@baylibre.com> References: <20220413020641.2789408-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach AM43xx support isolation of the IOs so that control is taken from the peripheral they are connected to and overridden by values present in the CTRL_CONF_* registers for the pad in the control module. The actual toggling happens from the wkup_m3, so use a DT property from the wkup_m3_ipc node to allow the PM code to communicate the necessity for placing the IOs into isolation to the firmware. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Drew Fustini --- drivers/soc/ti/wkup_m3_ipc.c | 14 ++++++++++++-- include/linux/wkup_m3_ipc.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 247a4b57a372..988162dd153a 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -46,6 +46,8 @@ #define IPC_VTT_STAT_MASK (0x1 << 3) #define IPC_VTT_GPIO_PIN_SHIFT (0x4) #define IPC_VTT_GPIO_PIN_MASK (0x3f << 4) +#define IPC_IO_ISOLATION_STAT_SHIFT (10) +#define IPC_IO_ISOLATION_STAT_MASK (0x1 << 10) =20 #define M3_STATE_UNKNOWN 0 #define M3_STATE_RESET 1 @@ -228,6 +230,11 @@ static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m= 3_ipc, int gpio) (gpio << IPC_VTT_GPIO_PIN_SHIFT); } =20 +static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc) +{ + m3_ipc->isolation_conf =3D (1 << IPC_IO_ISOLATION_STAT_SHIFT); +} + /* Public functions */ /** * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use @@ -308,8 +315,8 @@ static int wkup_m3_prepare_low_power(struct wkup_m3_ipc= *m3_ipc, int state) wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0); wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1); wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type | - m3_ipc->vtt_conf, 4); - + m3_ipc->vtt_conf | + m3_ipc->isolation_conf, 4); wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3); wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5); @@ -518,6 +525,9 @@ static int wkup_m3_ipc_probe(struct platform_device *pd= ev) dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp); } =20 + if (of_find_property(np, "ti,set-io-isolation", NULL)) + wkup_m3_set_io_isolation(m3_ipc); + /* * Wait for firmware loading completion in a thread so we * can boot the wkup_m3 as soon as it's ready without holding diff --git a/include/linux/wkup_m3_ipc.h b/include/linux/wkup_m3_ipc.h index 2bc52c6381d5..b706eac58f92 100644 --- a/include/linux/wkup_m3_ipc.h +++ b/include/linux/wkup_m3_ipc.h @@ -34,6 +34,7 @@ struct wkup_m3_ipc { int mem_type; unsigned long resume_addr; int vtt_conf; + int isolation_conf; int state; =20 struct completion sync_complete; --=20 2.32.0