From nobody Mon May 11 06:16:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30279C4332F for ; Tue, 12 Apr 2022 18:58:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358840AbiDLTA2 (ORCPT ); Tue, 12 Apr 2022 15:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346451AbiDLTAT (ORCPT ); Tue, 12 Apr 2022 15:00:19 -0400 Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A477740E48; Tue, 12 Apr 2022 11:58:01 -0700 (PDT) Received: by mail-qv1-xf31.google.com with SMTP id c1so7436328qvl.3; Tue, 12 Apr 2022 11:58:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kQeNukA9v0sAIjhr8IxlYmsIPikuBlNT7ZSLuaA7VkQ=; b=JZvxN4mPsfnmiG5M5FNESw8LyxB8P8335VSGyMh2aBqfkwfTU3nXAagfdAxoOfZ19b M0Ap25k+3+APXLuufjsZgwHKjMNabZkaM+L9pa71CVbyVmxG2KT0NKnDPNf4D4n159Q6 DtNJnl4pLxOHvnwc28igIX1HJJT2xef9d+kRQXT6QplUzxLRuBDfkoVHxiwNNK2ghB0e 7FvlZPe7DpRQAaQH5X6y69mU/tzJgGpf6emMotUifzyLtXSNDDJ1pAsCtQh3OQ1kNWXR CwUEoDu+DwE/zoUn6s/00mJk+2Fzkkh3haO2o4XcU75zceGv8q3O9QZWwCmGnMhIz0O3 CHZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kQeNukA9v0sAIjhr8IxlYmsIPikuBlNT7ZSLuaA7VkQ=; b=m/27XUtA0mHLeVJDCq+191zA9OOgbfSMMcIxB2Bppukxp6+CDXXX1paK2ZCmwV6tfi yqH94oTYUvuPodR/t5HvqrZcS8HY10ShQNMloAW17IpkbMDgdocuWveLxZxVL2akw8qq p+tXwX0//CvYRh6kWmbphWWWbYWZVZzqbuq9KL0O0KOroNciECZPjej+XTo329CeLxit z7jPM14kIz8vyFYNeUB0lSEOMgM8YenNRzpv8IOe2Cxhm3kmXOlMTNzhokpAbasyNUje 66xwfTF9BM0RaFN63YIy0bSPKsZP0ohmQinVMYR6v33z5WTcgUNqVq5PLNrLI2qxYwYA VRCQ== X-Gm-Message-State: AOAM5334BGFkaqCkxIVV0r28xsx/alC0q7+XSy99cE/drL4SDbCcHx6Y 4ENzETJB9Okid0WMFZMdtRA= X-Google-Smtp-Source: ABdhPJysK6WBKHFeXwuor8e59pMVwwACHYk61L2WmbC/NdngGu3X0z1pxc3BdsBfNS2XwEHApuqyrw== X-Received: by 2002:a05:6214:d88:b0:443:e626:40e0 with SMTP id e8-20020a0562140d8800b00443e62640e0mr32677438qve.112.1649789880743; Tue, 12 Apr 2022 11:58:00 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id d18-20020a05622a05d200b002f07ed88a54sm1820610qtb.46.2022.04.12.11.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 11:58:00 -0700 (PDT) From: Peter Geis To: Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/4] dt-bindings: pci: remove fallback from Rockchip DesignWare binding Date: Tue, 12 Apr 2022 14:57:48 -0400 Message-Id: <20220412185751.124783-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412185751.124783-1-pgwipeout@gmail.com> References: <20220412185751.124783-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The snps,dw-pcie binds to a standalone driver. It is not fully compatible with the Rockchip implementation and causes a hang if it binds to the device. Remove this binding as a valid fallback. Signed-off-by: Peter Geis --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..8dc11fed8a3c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -32,7 +32,6 @@ properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie =20 reg: items: @@ -110,7 +109,7 @@ examples: #size-cells =3D <2>; =20 pcie3x2: pcie@fe280000 { - compatible =3D "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible =3D "rockchip,rk3568-pcie"; reg =3D <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; --=20 2.25.1 From nobody Mon May 11 06:16:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F608C433EF for ; Tue, 12 Apr 2022 18:58:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356929AbiDLTBE (ORCPT ); Tue, 12 Apr 2022 15:01:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358811AbiDLTAX (ORCPT ); Tue, 12 Apr 2022 15:00:23 -0400 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEFED43AD5; Tue, 12 Apr 2022 11:58:02 -0700 (PDT) Received: by mail-qk1-x72a.google.com with SMTP id 3so7058444qkj.5; Tue, 12 Apr 2022 11:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qOnwkaEGKViV2QJ1JXpZ5IddTHppSw1fGZxu+INfSyI=; b=TZmjNKf/0qJBTGgkZltGqOBKg5S0YR+tK17WaFiOwq6nHwdCxAaBYAGfGov++BIdJn fWeRCJmWYcXvlvE+6J4czrRnilTz5OV5S6lxmqRtjySXZ/O2LZCudqUKn6upDcU0c/7F /lKufz63s6XHtcTwDE8+xwa+i/MMFv3x4eitEl3bFgwOR+A4nCowudePUNSs4aBjyta6 7GfbSoNTvvYSATbrmd9mpQX2B0nkjzQUBuZJ/D0KAYOvfi+yT/v9WL1Ti8aJCzPQP69v 4s3SnV3HRdFPvND6TE8cQx3HuT9zZ90GM4cxgTTuf0v13lgxlClFLcU+k6abuR3sP2eW llmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qOnwkaEGKViV2QJ1JXpZ5IddTHppSw1fGZxu+INfSyI=; b=6Se5oNpNcQ2l128uU7sm0GemlExBBmaSti93mJHW9Zyq55V8GVoURhS61nH+aBFSQM r1Hpsz3roiHFKzTcFGqxOODaMe7brS1W9PNvhW/CJo/l49kl1qcTUdJMOfuFShKAwwvG qawnMaiMkgsyUdCOAnMQ9Sq39LpEWMHbBG4mLJrTVV8BGJ8VjglsO5VJzRpV2rdC9JJW Mk651SE2bPVFpRxLVBF4F4M02MHMug65KUm8nZDWZ4gEaordUq07JYIePyQkcQPZdrES TsWzuL1NKPTk5OmOkrK5KphCJPoMW6JXnUsFJ4Y0HmeG7k6CKXBFhU8jjzCiSMAzbcRl x3gw== X-Gm-Message-State: AOAM532Qh8NR39fOyHGDDjwufQG0U7Uot/GYHb695NVAQTU3iq5KFToq vEn5kUAgn5YJE/aJD7zqB3M= X-Google-Smtp-Source: ABdhPJytyARNf+NUo54WSUHWnNsaIESDGWaTpic2NDMrdjhU2sXrVY+MmLuxf5en5VxeRtoTpzuqjw== X-Received: by 2002:a37:557:0:b0:69c:2490:cd06 with SMTP id 84-20020a370557000000b0069c2490cd06mr4226982qkf.724.1649789881740; Tue, 12 Apr 2022 11:58:01 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id d18-20020a05622a05d200b002f07ed88a54sm1820610qtb.46.2022.04.12.11.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 11:58:01 -0700 (PDT) From: Peter Geis To: Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/4] PCI: dwc: rockchip: add legacy interrupt support Date: Tue, 12 Apr 2022 14:57:49 -0400 Message-Id: <20220412185751.124783-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412185751.124783-1-pgwipeout@gmail.com> References: <20220412185751.124783-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The legacy interrupts on the rk356x pcie controller are handled by a single muxed interrupt. Add irq domain support to the pcie-dw-rockchip driver to support the virtual domain. Signed-off-by: Peter Geis --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 92 ++++++++++++++++++- 1 file changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index c9b341e55cbb..d14518039674 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -10,9 +10,12 @@ =20 #include #include +#include +#include #include #include #include +#include #include #include #include @@ -36,10 +39,12 @@ #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c #define PCIE_CLIENT_GENERAL_DEBUG 0x104 -#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) +#define PCIE_LEGACY_INT_ENABLE GENMASK(7, 0) +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { @@ -51,6 +56,7 @@ struct rockchip_pcie { struct reset_control *rst; struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; + struct irq_domain *irq_domain; }; =20 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, @@ -65,6 +71,68 @@ static void rockchip_pcie_writel_apb(struct rockchip_pci= e *rockchip, writel_relaxed(val, rockchip->apb_base + reg); } =20 +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct rockchip_pcie *rockchip =3D irq_desc_get_handler_data(desc); + struct device *dev =3D rockchip->pci.dev; + u32 reg; + u32 hwirq; + u32 virq; + + chained_irq_enter(chip, desc); + + reg =3D rockchip_pcie_readl_apb(rockchip, 0x8); + + while (reg) { + hwirq =3D ffs(reg) - 1; + reg &=3D ~BIT(hwirq); + + virq =3D irq_find_mapping(rockchip->irq_domain, hwirq); + if (virq) + generic_handle_irq(virq); + else + dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); + } + + chained_irq_exit(chip, desc); +} + +static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int = irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops =3D { + .map =3D rockchip_pcie_intx_map, +}; + +static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) +{ + struct device *dev =3D rockchip->pci.dev; + struct device_node *intc; + + intc =3D of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"= ); + if (!intc) { + dev_err(dev, "missing child interrupt-controller node\n"); + return -EINVAL; + } + + rockchip->irq_domain =3D irq_domain_add_linear(intc, PCI_NUM_INTX, + &intx_domain_ops, rockchip); + of_node_put(intc); + if (!rockchip->irq_domain) { + dev_err(dev, "failed to get a INTx IRQ domain\n"); + return -EINVAL; + } + + return 0; +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -111,9 +179,27 @@ static int rockchip_pcie_host_init(struct pcie_port *p= p) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); - u32 val =3D HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + struct device *dev =3D rockchip->pci.dev; + int irq, ret; + u32 val; + + irq =3D of_irq_get_byname(dev->of_node, "legacy"); + if (irq < 0) + return irq; + + irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, r= ockchip); + + ret =3D rockchip_pcie_init_irq_domain(rockchip); + if (ret < 0) + dev_err(dev, "failed to init irq domain\n"); + + /* enable legacy interrupts */ + val =3D HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val &=3D ~PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); =20 /* LTSSM enable control mode */ + val =3D HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); =20 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, --=20 2.25.1 From nobody Mon May 11 06:16:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80837C433EF for ; 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Tue, 12 Apr 2022 11:58:02 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller Date: Tue, 12 Apr 2022 14:57:50 -0400 Message-Id: <20220412185751.124783-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412185751.124783-1-pgwipeout@gmail.com> References: <20220412185751.124783-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The pcie2x1 controller is commong between the rk3568 and rk3566. It is a single lane pcie2 compliant controller. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 68 ++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index ca20d7b91fe5..d5131f5aaf73 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -270,10 +270,17 @@ gic: interrupt-controller@fd400000 { <0x0 0xfd460000 0 0x80000>; /* GICR */ interrupts =3D ; interrupt-controller; + ranges; #interrupt-cells =3D <3>; - mbi-alias =3D <0x0 0xfd410000>; - mbi-ranges =3D <296 24>; - msi-controller; + #address-cells =3D <2>; + #size-cells =3D <2>; + + its: interrupt-controller@fd440000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0xfd440000 0x0 0x20000>; + msi-controller; + #msi-cells =3D <1>; + }; }; =20 usb_host0_ehci: usb@fd800000 { @@ -722,6 +729,61 @@ qos_vop_m1: qos@fe1a8100 { reg =3D <0x0 0xfe1a8100 0x0 0x20>; }; =20 + pcie2x1: pcie@fe260000 { + compatible =3D "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xf>; + assigned-clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clocks =3D <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msi", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain =3D <0>; + num-ib-windows =3D <6>; + num-ob-windows =3D <2>; + max-link-speed =3D <2>; + msi-map =3D <0x0 &its 0x0 0x1000>; + num-lanes =3D <1>; + phys =3D <&combphy2 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3568_PD_PIPE>; + reg =3D <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x00000000 0x0 0x01000000>; + ranges =3D <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 + 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE20_POWERUP>; + reset-names =3D "pipe"; + status =3D "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + }; + sdmmc0: mmc@fe2b0000 { compatible =3D "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg =3D <0x0 0xfe2b0000 0x0 0x4000>; --=20 2.25.1 From nobody Mon May 11 06:16:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FADFC433F5 for ; Tue, 12 Apr 2022 18:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358936AbiDLTAw (ORCPT ); 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Tue, 12 Apr 2022 11:58:03 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/4] arm64: dts: rockchip: enable pcie controller on quartz64-a Date: Tue, 12 Apr 2022 14:57:51 -0400 Message-Id: <20220412185751.124783-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412185751.124783-1-pgwipeout@gmail.com> References: <20220412185751.124783-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the nodes to enable the pcie controller on the quartz64 model a board. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm6= 4/boot/dts/rockchip/rk3566-quartz64-a.dts index 141a433429b5..85926d46337d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -125,6 +125,18 @@ vbus: vbus { vin-supply =3D <&vcc12v_dcin>; }; =20 + vcc3v3_pcie_p: vcc3v3_pcie_p { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_enable_h>; + regulator-name =3D "vcc3v3_pcie_p"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3>; + }; + vcc5v0_usb: vcc5v0_usb { compatible =3D "regulator-fixed"; regulator-name =3D "vcc5v0_usb"; @@ -201,6 +213,10 @@ &combphy1 { status =3D "okay"; }; =20 +&combphy2 { + status =3D "okay"; +}; + &cpu0 { cpu-supply =3D <&vdd_cpu>; }; @@ -509,6 +525,14 @@ rgmii_phy1: ethernet-phy@0 { }; }; =20 +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_reset_h>; + reset-gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + vpcie3v3-supply =3D <&vcc3v3_pcie_p>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -534,6 +558,16 @@ diy_led_enable_h: diy-led-enable-h { }; }; =20 + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; --=20 2.25.1