From nobody Mon May 11 06:17:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA4D8C433EF for ; Tue, 12 Apr 2022 14:36:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356690AbiDLOiO (ORCPT ); Tue, 12 Apr 2022 10:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356584AbiDLOiH (ORCPT ); Tue, 12 Apr 2022 10:38:07 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B52BC5C642; Tue, 12 Apr 2022 07:35:49 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A482622248; Tue, 12 Apr 2022 16:35:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649774146; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OQzkjs08QLIF3IQTGjnM6UZsJDyLmHDtfKMOkdE5VCA=; b=CQl/uZJsNLazORWSxqZhY+Aqi/dBxl/SDxT3quo9HDZDMBGtslUl9VdcmEsG7ufPrAmbrT SbGj2ZsPYHC3Zsjo2oLMVnV2BLahV6e+EoH73iqylhsTVNCPuH0xq595oo0/hSrst8UL+c KbOgB/4ODPLqIm4faQG9JJ9BqjT4Ui8= From: Michael Walle To: Shawn Guo , Sascha Hauer Cc: Rob Herring , Krzysztof Kozlowski , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Thiery , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle , Krzysztof Kozlowski , Peng Fan Subject: [PATCH v3 1/2] dt-bindings: arm: fsl: add IMX8MN DDR3L eval board Date: Tue, 12 Apr 2022 16:32:37 +0200 Message-Id: <20220412143238.1925059-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220412143238.1925059-1-michael@walle.cc> References: <20220412143238.1925059-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This eval board features an IMX8MN UltraLite and has DDR3L RAM. The product part number is 8MNANOD3L-EVK. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Acked-by: Krzysztof Kozlowski Acked-by: Peng Fan --- changes since v2: - none, just reposted together with patch to add actual device tree changes since v1: - order entries alphabetically Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index b6cc34115362..d65b7d52bdd6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -881,6 +881,7 @@ properties: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO + - fsl,imx8mn-ddr3l-evk # i.MX8MN DDR3L EVK Board - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board --=20 2.30.2 From nobody Mon May 11 06:17:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE4CEC433F5 for ; Tue, 12 Apr 2022 14:36:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356673AbiDLOiT (ORCPT ); Tue, 12 Apr 2022 10:38:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356585AbiDLOiJ (ORCPT ); Tue, 12 Apr 2022 10:38:09 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DE645C864; Tue, 12 Apr 2022 07:35:50 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 32CF222249; Tue, 12 Apr 2022 16:35:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649774148; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G/hnT3AEhxVxbNwEdDE7vvgvmJxgXYZA0Ny8VTY14TA=; b=Ww/nu+x4QXsYJMEE0AH07YIcmC0qeLlkPD42SFTL3CJUgKcpbHUiQa9cSpRkeoL0j/XBnB CyZG6NFX/0k9k9+JMFI3cJY8Dn4XEHaS9poZLGPVrKpvaiCyQYfCRhNGV1zFje/qNFHRq6 LZqy5hFLZVnhPBycjABPOchfUfssPnU= From: Michael Walle To: Shawn Guo , Sascha Hauer Cc: Rob Herring , Krzysztof Kozlowski , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Thiery , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Walle Subject: [PATCH v3 2/2] arm64: dts: imx8mn: add 8MNANOD3L-EVK device tree Date: Tue, 12 Apr 2022 16:32:38 +0200 Message-Id: <20220412143238.1925059-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220412143238.1925059-1-michael@walle.cc> References: <20220412143238.1925059-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a device tree for the 8MNANOD3L-EVK eval board which features an IMX8MN SoC. It is similar to the 8MNANODLPD4-EVK eval board except it has an IMX8MN UltraLite SoC and DDR3L memory. It esp. differs in the PMIC configuration because the SoC has a smaller package and thus the ARM core voltage is combined with the SoC voltage and the DDR voltage is 1.35V for the DDR3L memory. Signed-off-by: Michael Walle --- changes since v2: - new patch arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-ddr3l-evk.dts | 114 ++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 85c2c9ba5110..bdb76e67ccfe 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm6= 4/boot/dts/freescale/imx8mn-ddr3l-evk.dts new file mode 100644 index 000000000000..000e2c0596df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model =3D "NXP i.MX8MNano DDR3L EVK board"; + compatible =3D "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply =3D <&buck1>; +}; + +&A53_1 { + cpu-supply =3D <&buck1>; +}; + +&A53_2 { + cpu-supply =3D <&buck1>; +}; + +&A53_3 { + cpu-supply =3D <&buck1>; +}; + +&i2c1 { + pmic: pmic@25 { + compatible =3D "nxp,pca9450b"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "VDD_SOC_0V9"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck4: BUCK4 { + regulator-name =3D "VDD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name =3D "VDD_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "NVCC_DRAM_1V35"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "NVCC_SNVS_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "VDD_SNVS_0V8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "VDDA_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "VDD_PHY_1V2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "NVCC_SD2"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; --=20 2.30.2