From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA924C433EF for ; Tue, 12 Apr 2022 13:07:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232381AbiDLNKD (ORCPT ); Tue, 12 Apr 2022 09:10:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354713AbiDLNFQ (ORCPT ); Tue, 12 Apr 2022 09:05:16 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C4A86D3A9; Tue, 12 Apr 2022 05:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767862; x=1681303862; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=HV4INz+UurFlOKl8wmWi/8lnnLAT1+ZPzBDOWPDVarY=; b=RedPYdCafx81kYkK4rYsmlQu0oO0l6RCiDMYurHuB6sdkOW+rWlao9jj HOjyX3ggfNb893bRmfuahxH1nPMWvh36pgfQeHLzyAvRZ16sCtJenU2ax pXgsJpcpBKPQiOa6dd+ouSDDvGPVxQO+5KwdbZhooCbTIm7/XLvFXimkI o=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 12 Apr 2022 05:51:02 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:01 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:01 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:50:57 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths. Date: Tue, 12 Apr 2022 20:50:26 +0800 Message-ID: <20220412125035.40312-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Except stm, there could be other sources which are not associated with cpus. Use IDR to store and search these sources' paths. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++------ 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index bbf415c252f9..23ab16dd9b5d 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,13 @@ static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); =20 +/* + * Use IDR to map the hash of the source's device name + * to the pointer of path for the source. The idr is for + * the sources which aren't associated with CPU. + */ +static DEFINE_IDR(path_idr); + /** * struct coresight_node - elements of a path, from source to sink * @csdev: Address of an element. @@ -43,14 +51,6 @@ struct coresight_node { */ static DEFINE_PER_CPU(struct list_head *, tracer_path); =20 -/* - * As of this writing only a single STM can be found in CS topologies. Si= nce - * there is no way to know if we'll ever see more and what kind of - * configuration they will enact, for the time being only define a single = path - * for STM. - */ -static struct list_head *stm_path; - /* * Set up a global trace ID map. * We may need a per sink ID map in future for larger / multi sink systems. @@ -1061,6 +1061,7 @@ int coresight_enable(struct coresight_device *csdev) struct coresight_device *sink; struct list_head *path; enum coresight_dev_subtype_source subtype; + u32 hash; =20 subtype =3D csdev->subtype.source_subtype; =20 @@ -1115,7 +1116,14 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) =3D path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - stm_path =3D path; + /* + * Use the hash of source's device name as ID + * and map the ID to the pointer of the path. + */ + hash =3D hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + ret =3D idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL); + if (ret) + goto err_source; break; default: /* We can't be here */ @@ -1139,6 +1147,7 @@ void coresight_disable(struct coresight_device *csdev) { int cpu, ret; struct list_head *path =3D NULL; + u32 hash; =20 mutex_lock(&coresight_mutex); =20 @@ -1156,14 +1165,20 @@ void coresight_disable(struct coresight_device *csd= ev) per_cpu(tracer_path, cpu) =3D NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - path =3D stm_path; - stm_path =3D NULL; + hash =3D hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + /* Find the path by the hash. */ + path =3D idr_find(&path_idr, hash); + if (path =3D=3D NULL) { + pr_err("Path is not found for %s\n", dev_name(&csdev->dev)); + goto out; + } break; default: /* We can't be here */ break; } =20 + idr_remove(&path_idr, hash); coresight_disable_path(path); coresight_release_path(path); =20 --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 416A7C433F5 for ; Tue, 12 Apr 2022 13:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355148AbiDLNLT (ORCPT ); Tue, 12 Apr 2022 09:11:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358026AbiDLNFR (ORCPT ); Tue, 12 Apr 2022 09:05:17 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 760D96D3AC; Tue, 12 Apr 2022 05:51:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767867; x=1681303867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=8wPP+/SGvQKk2qHzUTzUSi0V03+Tmb+UgdgS94uirkM=; b=ANd0RVRCzSocCr/MpjtLpKdEj1ahbfdsgcj46eXsY0dEVBooo14+5TTS +ok5kVBCSxELrcRv4vTICoxLUrxvfd6ytaQA0qQEGRM+ir6akuLq8S1jA /KrMmWaoS/5BQwfRGTLjBBGFyzRpYDQnmey2BhcPPIQQBS2jJ/gX/Ff5i A=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Apr 2022 05:51:06 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:05 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:04 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:01 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 02/10] Coresight: Add coresight TPDM source driver Date: Tue, 12 Apr 2022 20:50:27 +0800 Message-ID: <20220412125035.40312-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver to support Coresight device TPDM (Trace, Profiling and Diagnostics Monitor). TPDM is a monitor to collect data from different datasets. This change is to add probe/enable/disable functions for tpdm source. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 145 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 26 ++++ include/linux/coresight.h | 1 + 6 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index 514a9b8086e3..5c506a1cd08f 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,17 @@ config CORESIGHT_TRBE =20 To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +config CORESIGHT_TPDM + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for configuring monitor. Monitors are + primarily responsible for data set collection and support the + ability to collect any permutation of data set types. Monitors are + also responsible for interaction with system cross triggering. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpdm. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 329a0c704b87..6bb9b1746bc7 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) +=3D coresight-cpu-debu= g.o obj-$(CONFIG_CORESIGHT_CATU) +=3D coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) +=3D coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) +=3D coresight-trbe.o +obj-$(CONFIG_CORESIGHT_TPDM) +=3D coresight-tpdm.o coresight-cti-y :=3D coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 23ab16dd9b5d..75fe1781df20 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1047,7 +1047,8 @@ static int coresight_validate_source(struct coresight= _device *csdev, } =20 if (subtype !=3D CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && - subtype !=3D CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) { + subtype !=3D CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype !=3D CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; } @@ -1116,6 +1117,7 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) =3D path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY: /* * Use the hash of source's device name as ID * and map the ID to the pointer of the path. @@ -1165,6 +1167,7 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) =3D NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY: hash =3D hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); /* Find the path by the hash. */ path =3D idr_find(&path_idr, hash); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c new file mode 100644 index 000000000000..3900ae50670a --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpdm.h" + +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); + +/* TPDM enable operations */ +static int tpdm_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + if (drvdata->enable) { + mutex_unlock(&drvdata->lock); + return -EBUSY; + } + + drvdata->enable =3D true; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDM tracing enabled\n"); + return 0; +} + +/* TPDM disable operations */ +static void tpdm_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + if (!drvdata->enable) { + mutex_unlock(&drvdata->lock); + return; + } + + drvdata->enable =3D false; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDM tracing disabled\n"); +} + +static const struct coresight_ops_source tpdm_source_ops =3D { + .enable =3D tpdm_enable, + .disable =3D tpdm_disable, +}; + +static const struct coresight_ops tpdm_cs_ops =3D { + .source_ops =3D &tpdm_source_ops, +}; + +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev =3D &adev->dev; + struct coresight_platform_data *pdata; + struct tpdm_drvdata *drvdata; + struct coresight_desc desc =3D { 0 }; + + pdata =3D coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data =3D pdata; + + /* driver data*/ + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + mutex_init(&drvdata->lock); + + /* Set up coresight component description */ + desc.name =3D coresight_alloc_device_name(&tpdm_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type =3D CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype =3D CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY; + desc.ops =3D &tpdm_cs_ops; + desc.pdata =3D adev->dev.platform_data; + desc.dev =3D &adev->dev; + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + /* Decrease pm refcount when probe is done.*/ + pm_runtime_put(&adev->dev); + + return 0; +} + +static void __exit tpdm_remove(struct amba_device *adev) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDM has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpdm_ids[] =3D { + { + .id =3D 0x000f0e00, + .mask =3D 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpdm_driver =3D { + .drv =3D { + .name =3D "coresight-tpdm", + .owner =3D THIS_MODULE, + .suppress_bind_attrs =3D true, + }, + .probe =3D tpdm_probe, + .id_table =3D tpdm_ids, +}; + +module_amba_driver(tpdm_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtraci= ng/coresight/coresight-tpdm.h new file mode 100644 index 000000000000..94a7748a5426 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDM_H +#define _CORESIGHT_CORESIGHT_TPDM_H + +/** + * struct tpdm_drvdata - specifics associated to an TPDM component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @lock: lock for the enable value. + * @enable: enable status of the component. + */ + +struct tpdm_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + struct mutex lock; + bool enable; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 247147c11231..a9efac55029d 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY, }; =20 enum coresight_dev_subtype_helper { --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DAC2C433EF for ; Tue, 12 Apr 2022 13:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355063AbiDLNLO (ORCPT ); Tue, 12 Apr 2022 09:11:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358056AbiDLNFS (ORCPT ); Tue, 12 Apr 2022 09:05:18 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ED8A6D3B1; Tue, 12 Apr 2022 05:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767869; x=1681303869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=S3fioSwOFpxKRkm18j/pcrQRLSV4hTOldW6XEpMm09E=; b=RCJGkmNQsCpv/o7zmBiAy+V7kvTFArYSp4Q2bW86KXCb9ZJMVKu6vgeW 1bEcjCiHRyAFg7Ff2AVvrLAPV6ZDbkl4J+CFmnINUoYdsoDrlzZRzQ7h9 5W1H7EkT48p6UtqLhiMs0sBN0jmno/GgBertl5vR/ShMsjeGcm5tzr11u g=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 12 Apr 2022 05:51:09 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:09 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:08 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:04 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Date: Tue, 12 Apr 2022 20:50:28 +0800 Message-ID: <20220412125035.40312-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds new coresight-tpdm.yaml file describing the bindings required to define tpdm in the device trees. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/coresight-tpdm.yaml | 99 +++++++++++++++++++ .../devicetree/bindings/arm/coresight.txt | 7 ++ MAINTAINERS | 1 + 3 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.ya= ml diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Do= cumentation/devicetree/bindings/arm/coresight-tpdm.yaml new file mode 100644 index 000000000000..05210e0fc262 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Monitor - TPDM + +description: | + The TPDM or Monitor serves as data collection component for various data= set + types specified in the QPMDA spec. It covers Implementation defined ((Im= plDef), + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and D= iscrete + Single Bit (DSB). It performs data collection in the data producing clock + domain and transfers it to the data collection time domain, generally ATB + clock domain. + + The primary use case of the TPDM is to collect data from different data + sources and send it to a TPDA for packetization, timestamping, and funne= ling. + +maintainers: + - Suzuki K Poulose + - Mathieu Poirier + +properties: + $nodename: + pattern: "^tpdm(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpdm + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + out-ports: + description: | + Output connections from the TPDM to coresight funnle/tpda. + $ref: /schemas/graph.yaml#/properties/ports + properties: + port: + description: Output connection from the TPDM to coresight + funnel/tpda. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum TPDM definition. TPDM connect to coresight funnel. + - | + tpdm@6980000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x6980000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint =3D + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + }; + # minimum TPDM definition. TPDM connect to coresight TPDA. + - | + tpdm@684c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x684c000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_qdss: endpoint { + remote-endpoint =3D + <&tpda_qdss_in_tpdm_prng>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Document= ation/devicetree/bindings/arm/coresight.txt index c68d93a35b6c..f7ce8af48574 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -52,6 +52,10 @@ its hardware characteristcs. "arm,coresight-cti", "arm,primecell"; See coresight-cti.yaml for full CTI definitions. =20 + - Trace, Profiling and Diagnostics Monitor (TPDM): + "qcom,coresight-tpdm", "arm,primecell"; + See coresight-tpdm.yaml for full TPDM definitions. + * reg: physical base address and length of the register set(s) of the component. =20 @@ -82,6 +86,9 @@ its hardware characteristcs. * Required properties for Coresight Cross Trigger Interface (CTI) See coresight-cti.yaml for full CTI definitions. =20 +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM) + See coresight-tpdm.yaml for full TPDM definitions. + * Required properties for devices that don't show up on the AMBA bus, such= as non-configurable replicators and non-configurable funnels: =20 diff --git a/MAINTAINERS b/MAINTAINERS index 61d9f114c37f..0d39bb37935d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1977,6 +1977,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/= coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight-cti.yaml +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/ete.yaml F: Documentation/devicetree/bindings/arm/trbe.yaml --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1841EC433F5 for ; Tue, 12 Apr 2022 13:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355192AbiDLNKu (ORCPT ); Tue, 12 Apr 2022 09:10:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358039AbiDLNFS (ORCPT ); Tue, 12 Apr 2022 09:05:18 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0594018B29; Tue, 12 Apr 2022 05:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767873; x=1681303873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=XuWQieyurR+JOslnfl4Cw57EHugKmKfpb6cW0TAOp3Q=; b=KpX5CyifllquI5Hw7eh1W/pe4fWQS4j3d52M4+TPHkau3D5HWPC+xHV9 iPZNPjeE7T4G2oetRKpROHr9G/7kAjdq8zcBeYganSWk91636Jt4AiOwR AAez/DEhTEv+Nr9CvI04xDQUH19XkSFIlo0gjV70WTu4ALUcuEz93B+Ny U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Apr 2022 05:51:12 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:12 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:12 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:08 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support Date: Tue, 12 Apr 2022 20:50:29 +0800 Message-ID: <20220412125035.40312-5-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TPDM serves as data collection component for various dataset types. DSB(Discrete Single Bit) is one of the dataset types. DSB subunit can be enabled for data collection by writing 1 to the first bit of DSB_CR register. This change is to add enable/disable function for DSB dataset by writing DSB_CR register. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++ 2 files changed, 82 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index 3900ae50670a..d7b970cdcf51 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -20,7 +20,28 @@ =20 DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); =20 +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val =3D readl_relaxed(drvdata->base + TPDM_DSB_CR); + val =3D val | BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM enable operations */ +static void _tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, u32 mode) { @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev, return -EBUSY; } =20 + _tpdm_enable(drvdata); drvdata->enable =3D true; mutex_unlock(&drvdata->lock); =20 @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev, return 0; } =20 +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val =3D readl_relaxed(drvdata->base + TPDM_DSB_CR); + val =3D val & ~BIT(0); + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + /* TPDM disable operations */ +static void _tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (test_bit(TPDM_DS_DSB, drvdata->datasets)) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); + +} + static void tpdm_disable(struct coresight_device *csdev, struct perf_event *event) { @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev, return; } =20 + _tpdm_disable(drvdata); drvdata->enable =3D false; mutex_unlock(&drvdata->lock); =20 @@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops =3D { .source_ops =3D &tpdm_source_ops, }; =20 +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +{ + int i; + u32 pidr; + + CS_UNLOCK(drvdata->base); + /* Get the datasets present on the TPDM. */ + pidr =3D readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + for (i =3D 0; i < TPDM_DATASETS; i++) { + if (pidr & BIT(i)) + __set_bit(i, drvdata->datasets); + } + CS_LOCK(drvdata->base); +} + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; @@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const s= truct amba_id *id) if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); =20 + tpdm_init_default_data(drvdata); /* Decrease pm refcount when probe is done.*/ pm_runtime_put(&adev->dev); =20 diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtraci= ng/coresight/coresight-tpdm.h index 94a7748a5426..8f05070879c4 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -6,6 +6,25 @@ #ifndef _CORESIGHT_CORESIGHT_TPDM_H #define _CORESIGHT_CORESIGHT_TPDM_H =20 +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) + +/** + * This enum is for PERIPHIDR0 register of TPDM. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + */ +enum tpdm_dataset { + TPDM_DS_IMPLDEF, + TPDM_DS_DSB, +}; + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -13,6 +32,7 @@ * @csdev: component vitals needed by the framework. * @lock: lock for the enable value. * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. */ =20 struct tpdm_drvdata { @@ -21,6 +41,7 @@ struct tpdm_drvdata { struct coresight_device *csdev; struct mutex lock; bool enable; + DECLARE_BITMAP(datasets, TPDM_DATASETS); }; =20 #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08898C433F5 for ; Tue, 12 Apr 2022 13:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355068AbiDLNKj (ORCPT ); Tue, 12 Apr 2022 09:10:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358038AbiDLNFS (ORCPT ); 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Tue, 12 Apr 2022 05:51:15 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:12 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 05/10] coresight-tpdm: Add integration test support Date: Tue, 12 Apr 2022 20:50:30 +0800 Message-ID: <20220412125035.40312-6-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm1.bin Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/Kconfig | 9 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++ 3 files changed, 87 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index 5c506a1cd08f..60248fef4089 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -214,4 +214,13 @@ config CORESIGHT_TPDM To compile this driver as a module, choose M here: the module will be called coresight-tpdm. =20 +config CORESIGHT_TPDM_INTEGRATION_TEST + bool "Enable CoreSight Integration Test For TPDM" + depends on CORESIGHT_TPDM + help + This option adds support for the CoreSight integration test on this + devie. Coresight architecture provides integration control modes of + operation to facilitate integration testing and software bringup + and/or to instrument topology discovery. The TPDM utilizes integration + mode to accomplish integration testing and software bringup. endif diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index d7b970cdcf51..14bccbff467d 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -126,6 +126,69 @@ static void tpdm_init_default_data(struct tpdm_drvdata= *drvdata) CS_LOCK(drvdata->base); } =20 +/* + * Define CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST to enable + * integration_test sysfs nodes. It will help to generate + * tpdm data to make sure that the trace path is enabled + * and the funnel configurations are fine. + */ +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST +/* + * value 1: 64 bits test data + * value 2: 32 bits test data + */ +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret =3D 0; + unsigned long val; + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + ret =3D kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val !=3D 1 && val !=3D 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val =3D=3D 1) + val =3D ATBCNTRL_VAL_64; + else + val =3D ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i =3D 1; i < INTEGRATION_TEST_CYCLE; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + +static struct attribute *tpdm_attrs[] =3D { +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST + &dev_attr_integration_test.attr, +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + NULL, +}; + +static struct attribute_group tpdm_attr_grp =3D { + .attrs =3D tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] =3D { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; @@ -160,6 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const s= truct amba_id *id) desc.ops =3D &tpdm_cs_ops; desc.pdata =3D adev->dev.platform_data; desc.dev =3D &adev->dev; + desc.groups =3D tpdm_attr_grps; drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtraci= ng/coresight/coresight-tpdm.h index 8f05070879c4..ea457ba5434e 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,20 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) =20 +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + +/* + * Number of cycles to write value when + * integration test. + */ +#define INTEGRATION_TEST_CYCLE 10 + /** * This enum is for PERIPHIDR0 register of TPDM. * The fields [6:0] of PERIPHIDR0 are used to determine what --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6162C433EF for ; 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Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Apr 2022 05:51:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:20 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:19 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:15 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Date: Tue, 12 Apr 2022 20:50:31 +0800 Message-ID: <20220412125035.40312-7-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add API usage document for sysfs API in TPDM driver. Signed-off-by: Mao Jinlong --- .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-t= pdm diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpdm new file mode 100644 index 000000000000..d70ba429f38d --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -0,0 +1,13 @@ +What: /sys/bus/coresight/devices//integration_test +Date: April 2022 +KernelVersion 5.18 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) <= quic_taozha@quicinc.com> +Description: + (Write) Run integration test for tpdm. Integration test + will generate test data for tpdm. It can help to make + sure that the trace path is enabled and the link configurations + are fine. + + value to this sysfs node: + 1 : Genreate 64 bits data + 2 : Generate 32 bits data --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3760C433F5 for ; Tue, 12 Apr 2022 13:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349195AbiDLNKa (ORCPT ); Tue, 12 Apr 2022 09:10:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355503AbiDLNFS (ORCPT ); Tue, 12 Apr 2022 09:05:18 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07BE86D3BE; Tue, 12 Apr 2022 05:51:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767884; x=1681303884; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=E+i2EpZRUFMOaAhH5Oe/FrkzQ3nDNYcsCwki0B6v7yE=; b=SnqUwCudApgYvF2WrJLMzZKaFENSDhhBK0PSIOaJyxE4DSoylD4z8Tfv +gYoQpK+Tc/BSsufgvxV8+qLCjnf3Kc6OxXeQSfmtVXbVntd7/5FiGe5N 7BPqoWEcBjUvd86dCs1XuonsFFDmeug5An1CS9bI/GV8UwaQfbRLnqy78 A=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Apr 2022 05:51:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:23 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:23 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:19 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 07/10] Coresight: Add TPDA link driver Date: Tue, 12 Apr 2022 20:50:32 +0800 Message-ID: <20220412125035.40312-8-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TPDA(Trace, Profiling and Diagnostics Aggregator) is to provide packetization, funneling and timestamping of TPDM data. Multiple monitors are connected to different input ports of TPDA.This change is to add tpda enable/disable/probe functions for coresight tpda driver. - - - - - - - - - - - - | TPDM 0| | TPDM 1 | | TPDM 2| - - - - - - - - - - - - | | | |_ _ _ _ _ _ | _ _ _ _ | | | | | | | ------------------ | TPDA | ------------------ Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/Kconfig | 11 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 32 ++++ 4 files changed, 236 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index 60248fef4089..317c5e7f4819 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST operation to facilitate integration testing and software bringup and/or to instrument topology discovery. The TPDM utilizes integration mode to accomplish integration testing and software bringup. + +config CORESIGHT_TPDA + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver" + help + This driver provides support for configuring aggregator. This is + primarily useful for pulling the data sets from one or more + attached monitors and pushing the resultant data out. Multiple + monitors are connected on different input ports of TPDA. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpda. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 6bb9b1746bc7..1712d82e7260 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) +=3D coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) +=3D coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) +=3D coresight-trbe.o obj-$(CONFIG_CORESIGHT_TPDM) +=3D coresight-tpdm.o +obj-$(CONFIG_CORESIGHT_TPDA) +=3D coresight-tpda.o coresight-cti-y :=3D coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c new file mode 100644 index 000000000000..9519990c68e2 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpda.h" +#include "coresight-trace-id.h" + +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); + +/* Settings pre enabling port control register */ +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) +{ + u32 val; + + val =3D readl_relaxed(drvdata->base + TPDA_CR); + val |=3D (drvdata->atid << 6); + writel_relaxed(val, drvdata->base + TPDA_CR); +} + +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + val =3D readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* Enable the port */ + val =3D val | BIT(0); + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +} + +static void _tpda_enable(struct tpda_drvdata *drvdata, int port) +{ + CS_UNLOCK(drvdata->base); + + if (!drvdata->enable) + tpda_enable_pre_port(drvdata); + + tpda_enable_port(drvdata, port); + + CS_LOCK(drvdata->base); +} + +static int tpda_enable(struct coresight_device *csdev, int inport, int out= port) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + _tpda_enable(drvdata, inport); + drvdata->enable =3D true; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport); + return 0; +} + +static void _tpda_disable(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + + val =3D readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + val =3D val & ~BIT(0); + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + CS_LOCK(drvdata->base); +} + +static void tpda_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct tpda_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + mutex_lock(&drvdata->lock); + _tpda_disable(drvdata, inport); + drvdata->enable =3D false; + mutex_unlock(&drvdata->lock); + + dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport); +} + +static const struct coresight_ops_link tpda_link_ops =3D { + .enable =3D tpda_enable, + .disable =3D tpda_disable, +}; + +static const struct coresight_ops tpda_cs_ops =3D { + .link_ops =3D &tpda_link_ops, +}; + +static int tpda_init_default_data(struct tpda_drvdata *drvdata) +{ + int atid; + /* + * TPDA must has a unique atid. This atid can uniquely + * identify the TPDM trace source connect to the TPDA. + */ + atid =3D coresight_trace_id_get_system_id(coresight_get_trace_id_map()); + if (atid < 0) + return atid; + + drvdata->atid =3D atid; + return 0; +} + +static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + struct device *dev =3D &adev->dev; + struct coresight_platform_data *pdata; + struct tpda_drvdata *drvdata; + struct coresight_desc desc =3D { 0 }; + + pdata =3D coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data =3D pdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + mutex_init(&drvdata->lock); + + ret =3D tpda_init_default_data(drvdata); + if (ret) + return ret; + + desc.name =3D coresight_alloc_device_name(&tpda_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops =3D &tpda_cs_ops; + desc.pdata =3D adev->dev.platform_data; + desc.dev =3D &adev->dev; + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_put(&adev->dev); + + dev_dbg(drvdata->dev, "TPDA initialized\n"); + return 0; +} + +/* + * Different TPDA has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpda_ids[] =3D { + { + .id =3D 0x000f0f00, + .mask =3D 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpda_driver =3D { + .drv =3D { + .name =3D "coresight-tpda", + .owner =3D THIS_MODULE, + .suppress_bind_attrs =3D true, + }, + .probe =3D tpda_probe, + .id_table =3D tpda_ids, +}; + +module_amba_driver(tpda_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtraci= ng/coresight/coresight-tpda.h new file mode 100644 index 000000000000..6ac33b9c1ea4 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDA_H +#define _CORESIGHT_CORESIGHT_TPDA_H + +#define TPDA_CR (0x000) +#define TPDA_Pn_CR(n) (0x004 + (n * 4)) + +#define TPDA_MAX_INPORTS 32 + +/** + * struct tpda_drvdata - specifics associated to an TPDA component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @lock: lock for the enable value. + * @enable: enable status of the component. + * @traceid: trace source identification for the data packet by TPDA. + */ +struct tpda_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + struct mutex lock; + bool enable; + u32 atid; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */ --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0845C433F5 for ; Tue, 12 Apr 2022 13:08:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345688AbiDLNKV (ORCPT ); Tue, 12 Apr 2022 09:10:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358044AbiDLNFS (ORCPT ); Tue, 12 Apr 2022 09:05:18 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C12E6D4C6; Tue, 12 Apr 2022 05:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767888; x=1681303888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=LIx4K9AnoQVwj9XOioMv8ecFZ11kuYcUHe/1mB92phM=; b=YmzR4MWR0WQW/h4TeknSrKNbljJnulnRSKBzxnSODfIWX517BIcEXsQx IbhhRFa5M0lrg990W9TPyj5kgF/z6Wd2IeBUZ/xRIls5QoNX8zy2o4Pkm +3xiCnApj1wcxEHoJUDbyQfbchMVHj2dc1875NLeyi36W5whpdRhugyJj M=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 12 Apr 2022 05:51:27 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:27 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:27 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:23 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Date: Tue, 12 Apr 2022 20:50:33 +0800 Message-ID: <20220412125035.40312-9-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds new coresight-tpda.yaml file describing the bindings required to define tpda in the device trees. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.ya= ml diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Do= cumentation/devicetree/bindings/arm/coresight-tpda.yaml new file mode 100644 index 000000000000..2c79de0a7928 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Aggregator - TPDA + +description: | + TPDAs are responsible for packetization and timestamping of data sets + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or + more attached TPDM and pushing the resultant (packetized) data out a + master ATB interface. Performing an arbitrated ATB interleaving (funneli= ng) + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). + +maintainers: + - Suzuki K Poulose + - Mathieu Poirier + +properties: + $nodename: + pattern: "^tpda(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpda + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + type: object + description: | + Input connections from TPDM to TPDA + $ref: /schemas/graph.yaml#/properties/ports + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^port@[0-9a-f]+$": + type: object + required: + - reg + + required: + - '#size-cells' + - '#address-cells' + + out-ports: + type: object + description: | + Output connections from the TPDA to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: + Output connection from the TPDA to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + # minimum tpda definition. + - | + tpda@6004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x6004000 0x1000>; + + qcom,tpda-atid =3D <65>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint =3D + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint =3D + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + +... --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8366C433F5 for ; Tue, 12 Apr 2022 13:08:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355025AbiDLNKn (ORCPT ); Tue, 12 Apr 2022 09:10:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358043AbiDLNFS (ORCPT ); Tue, 12 Apr 2022 09:05:18 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 648B7BE2C; Tue, 12 Apr 2022 05:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649767892; x=1681303892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+ve2KMmoe2/qCGGMc6CY5dClWcMurQramuDSd5IV8FY=; b=NLmQKUIPr3pEEvOyFKDGftSsVJmlC2nbVqDEP81rFZbjb5A9heQjAhPO Z8Ze35biVqHR5F8/Ad3jWQjdkOuBfFvPfHh7f4OmtyadgMj1NFwV51iMZ Nh+OmswNM5KYsVOtu0Alu8oPSZKQtTYDDqy5O39Wd8szD1plPD/pzD2uz U=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 12 Apr 2022 05:51:32 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 05:51:31 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:30 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:27 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250 Date: Tue, 12 Apr 2022 20:50:34 +0800 Message-ID: <20220412125035.40312-10-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add coresight device tree for sm8250. STM/ETM are added. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + 2 files changed, 528 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/bo= ot/dts/qcom/sm8250-coresight.dtsi new file mode 100644 index 000000000000..1de42fd39248 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + + stm@6002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names =3D "stm-base", "stm-stimulus-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0 0x06041000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint =3D + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@7 { + reg =3D <7>; + funnel0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0 0x06042000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint =3D + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <4>; + funnel2_in5: endpoint { + remote-endpoint =3D + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + arm,primecell-periphid =3D <0x000bb908>; + + reg =3D <0 0x6b04000 0 0x1000>; + reg-names =3D "funnel-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint =3D + <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@7 { + reg =3D <7>; + funnel_swao_in_funnel_merg: endpoint { + remote-endpoint=3D + <&funnel_merg_out_funnel_swao>; + }; + }; + }; + + }; + + funnel@6045000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0 0x06045000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint =3D <&funnel_swao_in_funnel_merg>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <0>; + merge_funnel_in0: endpoint { + remote-endpoint =3D + <&funnel0_out>; + }; + }; + + port@2 { + reg =3D <1>; + merge_funnel_in2: endpoint { + remote-endpoint =3D + <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0 0x06046000 0 0x1000>; + + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint =3D <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_cx_in_swao_out: endpoint { + remote-endpoint =3D <&replicator_swao_out_cx_in>; + }; + }; + }; + }; + + replicator@6b06000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0 0x06b06000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + replicator_swao_out_cx_in: endpoint { + remote-endpoint =3D <&replicator_cx_in_swao_out>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint =3D <&etf_out>; + }; + }; + }; + }; + + etf@6b05000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0 0x6b05000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint =3D + <&replicator_in>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <0>; + etf_in: endpoint { + remote-endpoint =3D + <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0 0x06048000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint =3D + <&replicator_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07040000 0 0x1000>; + + cpu =3D <&CPU0>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07140000 0 0x1000>; + + cpu =3D <&CPU1>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07240000 0 0x1000>; + + cpu =3D <&CPU2>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07340000 0 0x1000>; + + cpu =3D <&CPU3>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07440000 0 0x1000>; + + cpu =3D <&CPU4>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07540000 0 0x1000>; + + cpu =3D <&CPU5>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07640000 0 0x1000>; + + cpu =3D <&CPU6>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible =3D "arm,coresight-etm4x", "arm,primecell"; + reg =3D <0 0x07740000 0 0x1000>; + + cpu =3D <&CPU7>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint =3D + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0 0x07800000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint =3D + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + apss_funnel_in0: endpoint { + remote-endpoint =3D + <&etm0_out>; + }; + }; + + port@1 { + reg =3D <1>; + apss_funnel_in1: endpoint { + remote-endpoint =3D + <&etm1_out>; + }; + }; + + port@2 { + reg =3D <2>; + apss_funnel_in2: endpoint { + remote-endpoint =3D + <&etm2_out>; + }; + }; + + port@3 { + reg =3D <3>; + apss_funnel_in3: endpoint { + remote-endpoint =3D + <&etm3_out>; + }; + }; + + port@4 { + reg =3D <4>; + apss_funnel_in4: endpoint { + remote-endpoint =3D + <&etm4_out>; + }; + }; + + port@5 { + reg =3D <5>; + apss_funnel_in5: endpoint { + remote-endpoint =3D + <&etm5_out>; + }; + }; + + port@6 { + reg =3D <6>; + apss_funnel_in6: endpoint { + remote-endpoint =3D + <&etm6_out>; + }; + }; + + port@7 { + reg =3D <7>; + apss_funnel_in7: endpoint { + remote-endpoint =3D + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0 0x07810000 0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint =3D + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port@1 { + reg =3D <0>; + apss_merge_funnel_in: endpoint { + remote-endpoint =3D + <&apss_funnel_out>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index af8f22636436..115623392183 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5434,3 +5434,5 @@ }; }; }; + +#include "sm8250-coresight.dtsi" --=20 2.17.1 From nobody Mon May 11 06:18:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1ACCC4332F for ; Tue, 12 Apr 2022 13:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234604AbiDLNLL (ORCPT ); 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12 Apr 2022 05:51:34 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:34 -0700 Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 05:51:30 -0700 From: Mao Jinlong To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin CC: Mao Jinlong , Mike Leach , Leo Yan , Greg Kroah-Hartman , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Trilok Soni , Hao Zhang , Subject: [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250 Date: Tue, 12 Apr 2022 20:50:35 +0800 Message-ID: <20220412125035.40312-11-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412125035.40312-1-quic_jinlmao@quicinc.com> References: <20220412125035.40312-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Signed-off-by: Mao Jinlong --- .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/bo= ot/dts/qcom/sm8250-coresight.dtsi index 1de42fd39248..9c710b69a804 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi @@ -44,6 +44,14 @@ #address-cells =3D <1>; #size-cells =3D <0>; =20 + port@6 { + reg =3D <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint =3D + <&funnel_qatb_out_funnel_in0>; + }; + }; + port@7 { reg =3D <7>; funnel0_in7: endpoint { @@ -523,4 +531,178 @@ }; }; }; + + tpdm@6c08000 { + compatible =3D "arm,primecell"; + reg =3D <0 0x6c08000 0 0x1000>; + reg-names =3D "tpdm-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_mm_out_funnel_dl_mm: endpoint { + remote-endpoint =3D + <&funnel_dl_mm_in_tpdm_mm>; + }; + }; + }; + }; + + funnel@6c0b000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg =3D <0 0x6c0b000 0 0x1000>; + reg-names =3D "funnel-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + funnel_dl_mm_out_funnel_dl_center: endpoint { + remote-endpoint =3D + <&funnel_dl_center_in_funnel_dl_mm>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@3 { + reg =3D <3>; + funnel_dl_mm_in_tpdm_mm: endpoint { + remote-endpoint =3D + <&tpdm_mm_out_funnel_dl_mm>; + }; + }; + }; + }; + + funnel@6c2d000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg =3D <0 0x6c2d000 0 0x1000>; + reg-names =3D "funnel-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port { + tpdm_mm_out_tpda9: endpoint { + remote-endpoint =3D + <&tpda_9_in_tpdm_mm>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + funnel_dl_center_in_funnel_dl_mm: endpoint { + remote-endpoint =3D + <&funnel_dl_mm_out_funnel_dl_center>; + }; + }; + }; + }; + + tpdm@684C000 { + compatible =3D "arm,primecell"; + reg =3D <0 0x684C000 0 0x1000>; + reg-names =3D "tpdm-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_23: endpoint { + remote-endpoint =3D + <&tpda_23_in_tpdm_prng>; + }; + }; + }; + }; + + tpda@6004000 { + compatible =3D "arm,primecell"; + reg =3D <0 0x6004000 0 0x1000>; + reg-names =3D "tpda-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + reg =3D <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint =3D + <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@9 { + reg =3D <9>; + tpda_9_in_tpdm_mm: endpoint { + remote-endpoint =3D + <&tpdm_mm_out_tpda9>; + }; + }; + + port@23 { + reg =3D <23>; + tpda_23_in_tpdm_prng: endpoint { + remote-endpoint =3D + <&tpdm_prng_out_tpda_23>; + }; + }; + }; + }; + + funnel@6005000 { + compatible =3D "arm,primecell"; + + reg =3D <0 0x6005000 0 0x1000>; + reg-names =3D "funnel-base"; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint =3D + <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint =3D + <&tpda_out_funnel_qatb>; + }; + }; + }; + }; }; --=20 2.17.1