From nobody Mon May 11 07:46:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFEACC433EF for ; Tue, 12 Apr 2022 11:39:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351673AbiDLLls (ORCPT ); Tue, 12 Apr 2022 07:41:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354697AbiDLLi6 (ORCPT ); Tue, 12 Apr 2022 07:38:58 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDFDB37BE3; Tue, 12 Apr 2022 03:19:51 -0700 (PDT) Received: from janitor.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: noc@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 8B7E283DA6; Tue, 12 Apr 2022 12:19:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649758789; bh=3yz4s9o1nz4BvPmYZJ3QuhCwoJciRv228WlmR/aEPOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ScT8GtsTqsNDdMHsXSJl9Xe194rsBs9Uw9T92Emr0AWZHP+4QqdecgjGABYwgWudY fyrnV59eX6EPHv5MjFRNV5LVg/Btp1pQqpfDYPQP+MvFw1I3Cbv6/jSC5YXrqe4COs PkbFX+rvDO7YD2Zu8mON2kms1YhdB4uP3EtrPbNFaWDRjLUsce5C5OOeVGqatl/cvp xLqPfFZWaeos/ZlTLLcvX7DfUBGki7vHf5q3ar+0uXnnzkts0sMt9WYPSK96KIoGm4 cWEl4sqOuDz3dH2qUcZ53jf5k+++Z8njFVN5VeGNLKovxbfjXtsdsq0cVF0GqnbjB4 LPHUPPkRU2cGg== Received: by janitor.denx.de (Postfix, from userid 108) id 334A2A02B9; Tue, 12 Apr 2022 12:19:49 +0200 (CEST) Received: from xpert.denx.de (xpert.denx.de [192.168.0.4]) by janitor.denx.de (Postfix) with ESMTPS id F03CCA005F; Tue, 12 Apr 2022 12:19:38 +0200 (CEST) Received: by xpert.denx.de (Postfix, from userid 535) id E21983E0786; Tue, 12 Apr 2022 12:19:38 +0200 (CEST) From: Philip Oberfichtner To: devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Winker Matthias , Philip Oberfichtner Subject: [PATCH 1/2] dt-bindings: arm: Add bosch acc board Date: Tue, 12 Apr 2022 12:19:04 +0200 Message-Id: <20220412101905.514310-2-pro@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220412101905.514310-1-pro@denx.de> References: <20220412101905.514310-1-pro@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree binding for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 08bdd30e511c..9deb568761c1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -192,6 +192,7 @@ properties: items: - enum: - auvidea,h100 # Auvidea H100 + - bosch,imx6q-acc # Bosch ACC i.MX6 Dual - boundary,imx6q-nitrogen6_max - boundary,imx6q-nitrogen6_som2 - boundary,imx6q-nitrogen6x --=20 2.34.1 From nobody Mon May 11 07:46:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99975C433EF for ; Tue, 12 Apr 2022 11:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244633AbiDLLmQ (ORCPT ); Tue, 12 Apr 2022 07:42:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355417AbiDLLjI (ORCPT ); Tue, 12 Apr 2022 07:39:08 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 063EC3FBFD; Tue, 12 Apr 2022 03:20:05 -0700 (PDT) Received: from janitor.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: noc@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 05CE083E17; Tue, 12 Apr 2022 12:20:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649758804; bh=PN5/cROWZS1ZjqRyAdtiqVaiP6PL/RmgBxRkYbmwaGI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gY5OLWakBoh/n/i7scZvpQx0SgaXEsAnKU0qRKPYgeQxxRBQmbMqoMYZNGPRDRdJt RSV9tdHBEtHqckAM7yzk+7dlmYUynQMPdEZ0SzeaLlgFp7ThyFTELlyrOZfc/yvhQ+ 6PhrbwB/ksdJWFZ+m80rVYZGJcnIDx2zx35+UGt2gI++fujLLX2goskMlasmIgP1h8 m9rmARgbFt9ut9Olv3b4s+OqPGWivXJeW2zoQDBnsQiXbOcyP5Fx6NGxhm8ypDAWjf 5k4pODVlQibUGqd4ZRI0MOhqUy0JSzP9ufcIZVaYLazuDjjBybiR+gsqj3IbYNxb3I gfp8JzJ6o/E0g== Received: by janitor.denx.de (Postfix, from userid 108) id C805EA0236; Tue, 12 Apr 2022 12:20:02 +0200 (CEST) Received: from xpert.denx.de (xpert.denx.de [192.168.0.4]) by janitor.denx.de (Postfix) with ESMTPS id 39FD3A00AD; Tue, 12 Apr 2022 12:19:48 +0200 (CEST) Received: by xpert.denx.de (Postfix, from userid 535) id 296DE3E0786; Tue, 12 Apr 2022 12:19:48 +0200 (CEST) From: Philip Oberfichtner To: devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Winker Matthias , Philip Oberfichtner Subject: [PATCH 2/2] arm: dts: Add device tree for bosch acc board Date: Tue, 12 Apr 2022 12:19:05 +0200 Message-Id: <20220412101905.514310-3-pro@denx.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220412101905.514310-1-pro@denx.de> References: <20220412101905.514310-1-pro@denx.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-bosch-acc.dts | 1048 +++++++++++++++++++++++++ 2 files changed, 1049 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-bosch-acc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..a6eff45bfee3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -547,6 +547,7 @@ dtb-$(CONFIG_SOC_IMX6Q) +=3D \ imx6q-b450v3.dtb \ imx6q-b650v3.dtb \ imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6= q-bosch-acc.dts new file mode 100644 index 000000000000..957916b1e7f2 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts @@ -0,0 +1,1048 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" + +/ { + model =3D "Bosch ACC"; + compatible =3D "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + serial0 =3D &uart2; + serial1 =3D &uart1; + + i2c0 =3D &i2c1; + i2c1 =3D &i2c2; + i2c2 =3D &i2c3; + /* eMMC is connected to USDHC interface 4, but shall get the name 0 */ + mmc0 =3D &usdhc4; + /* SC-Cards is connected to USDHC interface 2, but shall get the name 1 = */ + mmc1 =3D &usdhc2; + }; + + backlight { + status =3D "okay"; + + compatible =3D "pwm-backlight"; + /* The last value is the PWM period in nano-seconds! + * -> 5 kHz =3D 200 =C2=B5S =3D 200.000 ns + */ + pwms =3D <&pwm1 0 200000>; + brightness-levels =3D <0 61 499 1706 4079 8022 13938 22237 33328 47623 6= 5535>; + num-interpolated-steps =3D <10>; + default-brightness-level =3D <60>; + power-supply =3D <®_lcd0_pwr>; + }; + + usb3503_refclk: usb3503_refclk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&clks IMX6QDL_CLK_CKO2>; + clock-div =3D <1>; + clock-mult =3D <1>; + clock-output-names =3D "12mhz_refclk"; + + assigned-clocks =3D <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents =3D <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates =3D <0>, <12000000>, <0>; + }; + + cpus { + /* Override operating points with board-specific values */ + cpu0: cpu@0 { + operating-points =3D < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points =3D < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points =3D < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points =3D < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + leds { + compatible =3D "pwm-leds"; + + led_red: red { + label =3D "red"; + max-brightness =3D <248>; + default-state =3D "off"; + pwms =3D <&pwm2 0 500000>; + }; + + led_white: white { + label =3D "white"; + max-brightness =3D <248>; + default-state =3D "off"; + pwms =3D <&pwm3 0 500000>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + memory { + reg =3D <0x10000000 0x40000000>; + }; + + regulators: regulators { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + supply_5P0: regulator@0 { + compatible =3D "regulator-fixed"; + reg =3D <0>; + regulator-name =3D "5P0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + supply_VIN: regulator@1 { + compatible =3D "regulator-fixed"; + reg =3D <1>; + regulator-name =3D "VIN"; + regulator-min-microvolt =3D <4500000>; + regulator-max-microvolt =3D <4500000>; + regulator-always-on; + vin-supply =3D <&supply_5P0>; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible =3D "regulator-fixed"; + reg =3D <2>; + regulator-name =3D "usb_otg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_usb_h1_vbus: regulator@3 { + compatible =3D "regulator-fixed"; + reg =3D <3>; + regulator-name =3D "usb_h1_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + vin-supply =3D <&supply_5P0>; + }; + + supply_VSNVS_3V0: regulator@4 { + compatible =3D "regulator-fixed"; + reg =3D <4>; + regulator-name =3D "VSNVS_3V0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-always-on; + vin-supply =3D <&supply_5P0>; + }; + + reg_lcd0_pwr: regulator-lcd0-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "LCD0 POWER"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_enable>; + gpio =3D <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_usb_h2_vbus: regulator@6 { + compatible =3D "regulator-fixed"; + reg =3D <6>; + regulator-name =3D "usb_h2_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&supply_5P0> ; + regulator-always-on; + }; + + supply_vref_dac: vref_dac { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_dac"; + regulator-min-microvolt =3D <20000>; + regulator-max-microvolt =3D <20000>; + vin-supply =3D <&supply_5P0> ; + regulator-boot-on; + }; + }; + + reset_gpio_led { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reset_gpio_led>; + + reset { + label =3D "red_reset"; + gpios =3D <&gpio5 18 0>; + default-state =3D "off"; + }; + }; + + soc { + aips1: bus@2000000 {}; + }; +}; + +®_arm { + vin-supply =3D <&pmic_sw2>; +}; + +®_soc { + vin-supply =3D <&pmic_sw1abc>; +}; + +®_vdd1p1 { + vin-supply =3D <&supply_VSNVS_3V0>; +}; + +®_vdd2p5 { + vin-supply =3D <&supply_VSNVS_3V0>; +}; + +®_vdd3p0 { + vin-supply =3D <&supply_VSNVS_3V0>; +}; + +&audmux { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_audmux>; + status =3D "okay"; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet>; + status =3D "okay"; + + clocks =3D <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names =3D "ipg", "ahb", "ptp", "enet_out"; + phy-mode =3D "rmii"; + phy-supply =3D <&supply_sw4_3V3>; + phy-handle =3D <ðphy>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + ethphy: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + + +&gpu_vg { + status =3D "disabled"; +}; + +&gpu_2d { + status =3D "disabled"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <400000>; + status =3D "okay"; + + eeprom: eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + pagesize =3D <32>; + bytelen =3D <4096>; + bus-id =3D <0>; + flags =3D <0x80>; /* AT24_FLAG_ADDR16 */ + }; + + lm75: lm75@49 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lm75>; + + compatible =3D "national,lm75b"; + reg =3D <0x49>; + + interrupts =3D <7 0x4>; + interrupt-parent =3D <&gpio4>; + }; + + pmic: pfuze100@8 { + compatible =3D "fsl,pfuze100"; + reg =3D <0x08>; + uboot,bootcounter; + + VGEN1-supply =3D <&supply_AUX_3V15>; + VGEN2-supply =3D <&supply_AUX_3V15>; + VGEN3-supply =3D <&supply_sw4_3V3>; + VGEN4-supply =3D <&supply_sw4_3V3>; + VGEN5-supply =3D <&supply_SYS_4V2>; + VGEN6-supply =3D <&supply_SYS_4V2>; + + VREFDDR-supply =3D <&supply_DDR_1V5>; + + SW1AB-supply =3D <&supply_SYS_4V2>; + SW1C-supply =3D <&supply_SYS_4V2>; + SW2-supply =3D <&supply_SYS_4V2>; + SW3A-supply =3D <&supply_SYS_4V2>; + SW3B-supply =3D <&supply_SYS_4V2>; + SW4-supply =3D <&supply_SYS_4V2>; + + regulators { + /* + * VDD_CORE is connected to SW1 ABC + * We need to define sw1ab and sw1c, but later it is controlled solely = with + * sw1c and therefore only this is named "VDD_SOC". + * See PMIC datasheet Rev. 18, chapter 6.4.4.3.1: "The feedback and all + * other controls are accomplished by use of pin SW1CFB and SW1C control + * registers, respectively." + * Setting min and max according to SOC datasheet + */ + pmic_sw1abc: sw1c { + regulator-name =3D "VDD_SOC (sw1abc)"; + regulator-min-microvolt =3D <1275000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <6250>; + + default-voltage =3D <1300000>; + }; + + pmic_sw2: sw2{ + regulator-name =3D "VDD_ARM (sw2)"; + + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <6250>; + + default-voltage =3D <1300000>; + }; + + pmic_sw3a: sw3a { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible =3D "regulator-fixed"; + regulator-name =3D "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_DDR_1V5: sw3b { + /* U-Boot sets correct voltage, shall not be touched by the OS */ + compatible =3D "regulator-fixed"; + regulator-name =3D "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + supply_AUX_3V15: sw4 { + regulator-name =3D "AUX 3V15 (sw4)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + + default-voltage =3D <3150000>; + + }; + + swbst_reg: swbst { + status =3D "disabled"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5150000>; + regulator-boot-on; + regulator-always-on; + + }; + + snvs_reg: vsnvs { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3000000>; + regulator-boot-on; + regulator-always-on; + + default-voltage =3D <3000000>; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + + default-voltage =3D <675000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1550000>; + regulator-always-on; + + default-voltage =3D <1500000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1550000>; + regulator-always-on; + + default-voltage =3D <1200000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + + default-voltage =3D <2500000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage =3D <1800000>; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + default-voltage =3D <2800000>; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + + default-voltage =3D <2800000>; + }; + + }; + }; + + rtc: rtcpcf8563@51 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rtc>; + + compatible =3D "nxp,pcf8563"; + reg =3D <0x51>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <100000>; + status =3D "okay"; + + adc101c: ac101c@54 { + compatible =3D "ti,adc101c"; + reg =3D <0x54>; + status =3D "okay"; + vref-supply =3D <&supply_vref_dac>; + vcc-supply =3D <&supply_vref_dac>; + }; + + ad5602: ad5602@c { + compatible =3D "adi,ad5602"; + reg =3D <0x0c>; + status =3D "okay"; + vcc-supply =3D <&supply_vref_dac>; + }; + + eeprom_ext: eeprom_ext@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + pagesize =3D <32>; + bytelen =3D <4096>; + bus-id =3D <1>; + flags =3D <0x80>; /* AT24_FLAG_ADDR16 */ + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exc3000: exc3000@2a { + compatible =3D "eeti,exc3000"; + reg =3D <0x2a>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ctouch>; + + interrupt-parent =3D <&gpio4>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + + touchscreen-size-x =3D <4096>; + touchscreen-size-y =3D <4096>; + + status =3D "okay"; + }; + + usb3503: usb3503@8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb3503>; + status =3D "okay"; + + compatible =3D "smsc,usb3503"; + reg =3D <0x08>; + connect-gpios =3D <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios =3D <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios =3D <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode =3D <1>; + + clocks =3D <&usb3503_refclk>; + clock-names =3D "refclk"; + refclk-frequency =3D <12000000>; + }; + + vcnl4035: vcnl4035@60 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_proximity>; + compatible =3D "vishay,vcnl4035"; + reg =3D <0x60>; + status =3D "okay"; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins =3D < + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x110b0 + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins =3D < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001B098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001B098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001B098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_gpio_export_gpio_fixed_in: pinctrl_gpio_export_gpio_fixed_in_grp { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* CLEAR ALL */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* DIG_IN_1 */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x80000000 /* DIG_IN_2 */ + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x80000000 /* PoE */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x80000000 /* PoE T2P */ + >; + }; + + pinctrl_reset_gpio_led: pinctrl_reset_gpio_led_pin { + fsl,pins =3D < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000 + >; + }; + + pinctrl_gpio_export_gpio_fixed_out: pinctrl_gpio_export_gpio_fixed_out_gr= p { + fsl,pins =3D < + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x0001B0B0 /* DIG_OUT_1 */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x0001B0B0 /* DIG_OUT_2 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x0001B0B0 /* nUART_RESET */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0001B0B0 /* nETH1_RESET */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0001B0B0 /* nETH2_RESET */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001B0B0 /* RS485#1_PWR */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0001B0B0 /* RS485#2_PWR */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0001B0B0 /* RS485#3_PWR */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0001B0B0 /* RS485#4_PWR */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x0001B0B0 /* FEC_RESET_B */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001B0B0 /* AN_IN_PWR */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001B0B0 /* AN_OUT_PWR */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001B0B0 /* nUSBH1_PWR */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + /* not used SD2 and SD3 pins */ + /* [HYS 1] [100K PU] [PU] [PU EN] [CMOS] [Med. Speed] [40R] [Slow SR] */ + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x0001B0B0 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x0001B0B0 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0000B0B1 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x0001B0B0 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x0001B0B0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001B0B0 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0000B0B1 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0001B0B0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B8B1 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B8B1 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x000138B1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins =3D < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x80000000 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + /* NO SRE | 130 Ohm | SPEED LOW | Open Drain | PKE | PUE | 100k PU | HY= S */ + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x80000000 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins =3D < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000 + >; + }; + + pinctrl_lcd_enable: lcdenablerp { + fsl,pins =3D < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins =3D < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 + >; + }; + + pinctrl_pfid_0_2: pfid_0_2_grp { + fsl,pins =3D < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0001B0B0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001B0B0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001B0B0 + >; + }; + + pinctrl_pfid_3_4: pfid_3_4_grp { + fsl,pins =3D < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001B0B0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0001B0B0 + >; + }; + + pinctrl_pfid_5_7: pfid_5_7_grp { + fsl,pins =3D < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0001B0B0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001B0B0 + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001B0B0 + >; + }; + + pinctrl_pfid_8_9: pfid_8_9_grp { + fsl,pins =3D < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001B0B0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001B0B0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins =3D < + /* PROXIMITY_INT */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins =3D < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins =3D < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001B0B0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins =3D < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001B0B0 + >; + }; + + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001B0B0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins =3D < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001B0B0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001B0B0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins =3D < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins =3D < + /* 100K Pull-Down, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + /* 47K Pull-Up, 76_OHM drive strength */ + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: pinctrl_usb3503-grp { + fsl,pins =3D < + /* USB Hub REFCLK - No pull-up/pull-down, CMOS output, low speed, 90 Oh= m */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001B0B0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins =3D < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + /* CMD and DATA0..3 have external pull-up, CLK does not need a pull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 = MHz) + */ + fsl,pins =3D < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001B0B0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + /* CMD has external pull-up, DATA0..7 within eMMC, CLK does not need a p= ull-up. + * CLK signal is half the speed than the others (52 MHz compared to 104 = MHz) + */ + fsl,pins =3D < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins =3D < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; + +&ldb { + status =3D "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping =3D "spwg"; + fsl,data-width =3D <24>; + status =3D "okay"; + + display-timings { + native-mode =3D <&lvds0_timing0>; + lvds0_timing0: hsd100pxn1 { + clock-frequency =3D <79479000>; + hactive =3D <1280>; + vactive =3D <800>; + hback-porch =3D <100>; + hfront-porch =3D <100>; + vback-porch =3D <5>; + vfront-porch =3D <5>; + hsync-len =3D <24>; + vsync-len =3D <3>; + hsync-active =3D <0>; + vsync-active =3D <0>; + de-active =3D <1>; + pixelclk-active =3D <1>; + }; + }; + }; +}; + +&pmu { + interrupt-affinity =3D <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; +}; + +&pwm1 { + #pwm-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; + status =3D "okay"; +}; + +&pwm2 { + #pwm-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; + status =3D "okay"; +}; + +&pwm3 { + #pwm-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm3>; + status =3D "okay"; + linux,default-trigger =3D "heartbeat"; +}; + +&pwm4 { + #pwm-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + status =3D "okay"; +}; + +®ulators { + supply_sw4_3V3: regulator@8 { + compatible =3D "regulator-fixed"; + reg =3D <8>; + regulator-name =3D "SW4_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + vin-supply =3D <&supply_5P0>; + }; + + supply_SYS_4V2: regulator@9 { + compatible =3D "regulator-fixed"; + reg =3D <9>; + regulator-name =3D "SYS_4V2"; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + regulator-always-on; + vin-supply =3D <&supply_5P0>; + }; +}; + +&sdma { + fsl,sdma-ram-script-name =3D "imx/sdma/sdma-imx6q.bin"; + iram =3D <&ocram>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; + + rts-gpios =3D <&gpio7 8 0>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status =3D "okay"; +}; + +&usbh1 { + vbus-supply =3D <®_usb_h1_vbus>; + status =3D "okay"; +}; + +&usbh2 { + pinctrl-names =3D "idle", "active"; + pinctrl-0 =3D <&pinctrl_usbh2_idle>; + pinctrl-1 =3D <&pinctrl_usbh2_active>; + status =3D "okay"; + + vbus-supply =3D <®_usb_h2_vbus>; + osc-clkgate-delay =3D <0x3>; + + pad-supply =3D <&vgen2_reg>; +}; + +&usbotg { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usbotg>; + status =3D "okay"; + + vbus-supply =3D <®_usb_otg_vbus>; + disable-over-current; + dr_mode =3D "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +&usbphynop1 { + clocks =3D <&clks IMX6QDL_CLK_USBPHY1>; + clock-names =3D "main_clk"; + vcc-supply =3D <®_usb_h1_vbus>; +}; + +&usbphynop2 { + vcc-supply =3D <®_usb_h2_vbus>; +}; + +/* sdcard */ +&usdhc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + status =3D "okay"; + + cd-gpios =3D <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges =3D <3300 3300>; + vmmc-supply =3D <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +/* emmc */ +&usdhc4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc4>; + status =3D "okay"; + + bus-width =3D <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges =3D <3300 3300>; + vmmc-supply =3D <&supply_sw4_3V3>; + fsl,wp-controller; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog1>; + fsl,ext-reset-output; + status =3D "okay"; + timeout-sec=3D<10>; +}; + --=20 2.34.1