From nobody Sat Jun 13 12:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBF82C4332F for ; Mon, 11 Apr 2022 15:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240250AbiDKPXq (ORCPT ); Mon, 11 Apr 2022 11:23:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347794AbiDKPXf (ORCPT ); Mon, 11 Apr 2022 11:23:35 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9812E326F0 for ; Mon, 11 Apr 2022 08:21:19 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id c7so23632435wrd.0 for ; Mon, 11 Apr 2022 08:21:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Av8EzP8d6KVoQi/yXwkBOAZabP9Xc8kXclRu9dT4+Lw=; b=MSW2higryDgsOhw0ZJDq4mbqycpFHp4ZK/5IKr30dVw+TG88282lZo+8u8kF2+sS/8 t7IICscSNVmaDq9/jbHn0OPrQNhH/FUIc99pHP882qHAHVm/kjNMO4jfZ8UpZnnCK8yK 7z+7lovGGpwh2g0cUNRsIxYVVn8En0/LjjELY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Av8EzP8d6KVoQi/yXwkBOAZabP9Xc8kXclRu9dT4+Lw=; b=xwEVc9fYm0cAC0wHRxGS+3d8MjShTkASFz/vrI558UpfwU1yzHXCMDkUDzt5JXTiKy pyrKMUm/lmgE76seV9bPCzQabsFIHTPobkZFIkKOu9J1q+EkDR4+WhaJ6LiQnmmAK8Hg v8LVuK4eFB+eFzW3skb5OGFBZxJZ4+uAW3qUocUAdNQaNx7AfkSB8Dep8p2cgY6YRgcy jazuCkc/lzIAO9mh7LsfNw6WrEjuPpWp9VYHj64T42fGXhDYt+H6douqqsffrOhESkBt 2DiDwRGUlPVLQaNJ3mYysNgZc/K6094LTojC0/6IhYGDn+jiiBtOFsCsQ9eRlSYqnk+P 6qgQ== X-Gm-Message-State: AOAM532YA3rVA3LQVsI6ZnvcG36Sb28YWSBiJEOnrhLQffvNWJ3AWLM6 e8ZY2P4qd6qXYUPPFUh0EMO6Xg== X-Google-Smtp-Source: ABdhPJxPthidGCKrnPvf9IHSua1gxQPSnNJCQzeeFUq0J9nt1iiyJPKPkuaIafZ/E669DST2+ymPrA== X-Received: by 2002:a05:6000:3ca:b0:207:a389:ca09 with SMTP id b10-20020a05600003ca00b00207a389ca09mr6481526wrg.628.1649690477827; Mon, 11 Apr 2022 08:21:17 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bk1-20020a0560001d8100b002061d6bdfd0sm19512832wrb.63.2022.04.11.08.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:21:17 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v3 1/4] dt-bindings: add mfd/cros_ec definitions Date: Mon, 11 Apr 2022 15:21:11 +0000 Message-Id: <20220411152114.2165933-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1178.g4f1659d476-goog In-Reply-To: <20220411152114.2165933-1-fabiobaltieri@chromium.org> References: <20220411152114.2165933-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cr= os_ec.h new file mode 100644 index 000000000000..3b29cd049578 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif --=20 2.35.1.1178.g4f1659d476-goog From nobody Sat Jun 13 12:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06EA6C433F5 for ; Mon, 11 Apr 2022 15:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347865AbiDKPXu (ORCPT ); Mon, 11 Apr 2022 11:23:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347803AbiDKPXf (ORCPT ); Mon, 11 Apr 2022 11:23:35 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1DB43B3E9 for ; Mon, 11 Apr 2022 08:21:20 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id m33-20020a05600c3b2100b0038ec0218103so1081602wms.3 for ; Mon, 11 Apr 2022 08:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bScrnygALRi5vTrh1+NEViI6Wv9mGSCg+5NQG0F9hNU=; b=nbUlIipH447q4p1olQkERIU5utdBTNQHTWPMFDAkNy2NItph72BhUi1iPTdKXoK8q3 ndq1dhXVf/bQkIm7s/u+CC2wZ8vaTGwKE4FiWga8d3pJDKR9u0e1s5qzjvVAGW796ZDs AVf5TP434mnO1UPvySossJuBDChpNQ7aS/WQw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bScrnygALRi5vTrh1+NEViI6Wv9mGSCg+5NQG0F9hNU=; b=byEYSZsO9oWS3zQqJAboFgvFSfiYguCBXTha1q2/zCLFqTbWGN4x4WNBVAO+JFntOV tqjG1GNQx+AhyHLjbwUCgmWxzLdZczrDiYaKJFBhHgomi6Bwk64LzBmCR801wwwZQr3Q zWm6wm0kQ361JigXTTKnz/U5z+AwCb5fyt1mRkicXqx/ktZPpI7p8GouyqV1l76WsafZ mMiNoGA2lZT1e2rERPaAFFmZB20CS8Kh8NKl4/g3zdIfbyGr9IDeC2bP/5be4SRzapCU 4LO8CjylgLku3/nv2D9NPdUOY6MdcRW8wA9ANR4+T6yc0xvw06SjRKOYcRxCOjODmNqX b6tw== X-Gm-Message-State: AOAM5308/2YZAb7zByPAk637rgS2jCXUs1qXnyhnRZGRs+KMkeP3TFqG 7cfOw1JpdwqZ7NX1HR+z9O0Jxw== X-Google-Smtp-Source: ABdhPJzczSgt8EiKjb99yes0LTdyZkyH+uu1QJ1RmijAByejxq91exHGaEDjuIqrhJkNPcRpyO1EAQ== X-Received: by 2002:a05:600c:1990:b0:38e:a8c9:f32f with SMTP id t16-20020a05600c199000b0038ea8c9f32fmr15105198wmq.35.1649690478709; Mon, 11 Apr 2022 08:21:18 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bk1-20020a0560001d8100b002061d6bdfd0sm19512832wrb.63.2022.04.11.08.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:21:18 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v3 2/4] drivers: pwm: pwm-cros-ec: add channel type support Date: Mon, 11 Apr 2022 15:21:12 +0000 Message-Id: <20220411152114.2165933-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1178.g4f1659d476-goog In-Reply-To: <20220411152114.2165933-1-fabiobaltieri@chromium.org> References: <20220411152114.2165933-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. To use it, define the node with the "google,cros-ec-pwm-type" compatible. Signed-off-by: Fabio Baltieri --- drivers/pwm/pwm-cros-ec.c | 109 ++++++++++++++++++++++++++++++-------- 1 file changed, 86 insertions(+), 23 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..83c33958d52b 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -6,23 +6,30 @@ */ =20 #include +#include #include #include #include #include #include =20 +#include + +#define OF_CROS_EC_PWM_TYPE ((void *)1) + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; =20 /** @@ -58,14 +65,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, str= uct pwm_device *pwm) kfree(channel); } =20 -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 d= uty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type =3D EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type =3D EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x, + u16 duty) +{ + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params =3D &buf.params; struct cros_ec_command *msg =3D &buf.msg; + int ret; =20 memset(&buf, 0, sizeof(buf)); =20 @@ -75,14 +99,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *= ec, u8 index, u16 duty) msg->outsize =3D sizeof(*params); =20 params->duty =3D duty; - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 return cros_ec_cmd_xfer_status(ec, msg); } =20 -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 inde= x) { + struct cros_ec_device *ec =3D ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +137,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device = *ec, u8 index) msg->insize =3D sizeof(*resp); msg->outsize =3D sizeof(*params); =20 - params->pwm_type =3D EC_PWM_TYPE_GENERIC; - params->index =3D index; + if (ec_pwm->use_pwm_type) { + ret =3D cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index =3D 0; + } else { + params->pwm_type =3D EC_PWM_TYPE_GENERIC; + params->index =3D index; + } =20 ret =3D cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +177,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, */ duty_cycle =3D state->enabled ? state->duty_cycle : 0; =20 - ret =3D cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret =3D cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; =20 @@ -149,7 +193,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip= , struct pwm_device *pwm, struct cros_ec_pwm *channel =3D pwm_get_chip_data(pwm); int ret; =20 - ret =3D cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret =3D cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +248,13 @@ static const struct pwm_ops cros_ec_pwm_ops =3D { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; =20 /* The index field is only 8 bits */ for (i =3D 0; i <=3D U8_MAX; i++) { - ret =3D cros_ec_pwm_get_duty(ec, i); + ret =3D cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -232,10 +276,27 @@ static int cros_ec_num_pwms(struct cros_ec_device *ec) return U8_MAX; } =20 +#ifdef CONFIG_OF +static const struct of_device_id cros_ec_pwm_of_match[] =3D { + { + .compatible =3D "google,cros-ec-pwm", + }, + { + .compatible =3D "google,cros-ec-pwm-type", + .data =3D OF_CROS_EC_PWM_TYPE, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match); +#else +#define cros_ec_pwm_of_match NULL +#endif + static int cros_ec_pwm_probe(struct platform_device *pdev) { struct cros_ec_device *ec =3D dev_get_drvdata(pdev->dev.parent); struct device *dev =3D &pdev->dev; + const struct of_device_id *id; struct cros_ec_pwm_device *ec_pwm; struct pwm_chip *chip; int ret; @@ -251,17 +312,27 @@ static int cros_ec_pwm_probe(struct platform_device *= pdev) chip =3D &ec_pwm->chip; ec_pwm->ec =3D ec; =20 + id =3D of_match_device(cros_ec_pwm_of_match, dev); + if (id && id->data =3D=3D OF_CROS_EC_PWM_TYPE) + ec_pwm->use_pwm_type =3D true; + /* PWM chip */ chip->dev =3D dev; chip->ops =3D &cros_ec_pwm_ops; chip->of_xlate =3D cros_ec_pwm_xlate; chip->of_pwm_n_cells =3D 1; - ret =3D cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm =3D CROS_EC_PWM_DT_COUNT; + } else { + ret =3D cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm =3D ret; } - chip->npwm =3D ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); =20 ret =3D pwmchip_add(chip); @@ -285,14 +356,6 @@ static int cros_ec_pwm_remove(struct platform_device *= dev) return 0; } =20 -#ifdef CONFIG_OF -static const struct of_device_id cros_ec_pwm_of_match[] =3D { - { .compatible =3D "google,cros-ec-pwm" }, - {}, -}; -MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match); -#endif - static struct platform_driver cros_ec_pwm_driver =3D { .probe =3D cros_ec_pwm_probe, .remove =3D cros_ec_pwm_remove, --=20 2.35.1.1178.g4f1659d476-goog From nobody Sat Jun 13 12:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D320C433F5 for ; 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Mon, 11 Apr 2022 08:21:19 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v3 3/4] dt-bindings: update google,cros-ec-pwm documentation Date: Mon, 11 Apr 2022 15:21:13 +0000 Message-Id: <20220411152114.2165933-4-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1178.g4f1659d476-goog In-Reply-To: <20220411152114.2165933-1-fabiobaltieri@chromium.org> References: <20220411152114.2165933-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update google,cros-ec-pwm node documentation to mention the google,cros-ec-pwm-type compatible. Signed-off-by: Fabio Baltieri --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml = b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 7ab6912a845f..deb9e4488773 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -21,7 +21,14 @@ allOf: =20 properties: compatible: - const: google,cros-ec-pwm + oneOf: + - description: PWM controlled using EC_PWM_TYPE_GENERIC channels. + items: + - const: google,cros-ec-pwm + - description: PWM controlled using CROS_EC_PWM_DT_<...> types. + items: + - const: google,cros-ec-pwm-type + "#pwm-cells": description: The cell specifies the PWM index. const: 1 --=20 2.35.1.1178.g4f1659d476-goog From nobody Sat Jun 13 12:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00759C433F5 for ; Mon, 11 Apr 2022 15:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343505AbiDKPYF (ORCPT ); Mon, 11 Apr 2022 11:24:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347810AbiDKPXh (ORCPT ); Mon, 11 Apr 2022 11:23:37 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24E3A3B3FF for ; Mon, 11 Apr 2022 08:21:22 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id c7so23632692wrd.0 for ; Mon, 11 Apr 2022 08:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UBu9bKNpcsjBxVmcDi5TeRQJe5h4mzqRMvKt6Hs6yfk=; b=KZQ1OwKLIJThuwjrnbXyMe/lbykmQB1HTeZdE0/lO7EMolpP+udEuy1jDaLgKfjIOU O3iLTLrAODYzX7VmRAPCkpan/K3iYF2HqOs+D8Ym7Ui93sgqmTjrFG5QR/g4nVsI1K2K R3LLIFk0pmPSfy4OCjq6ffYuhTry1WlgjiSsY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UBu9bKNpcsjBxVmcDi5TeRQJe5h4mzqRMvKt6Hs6yfk=; b=c+EEVZrUrtmm+vwV3AMeEgFyRNbA0jsx+dFYm2UfDgWlmV9BiVMJeBVY9GHyeSodGb 6K8WUaE6NjcqrZbXxlz0AvYfErlGMgHiFenAejFp9JbNgrfV3o8Gt2LwSk6yE0Zb/mWj fkMscq41/FnwiQru+8vnlf7V4TmucvD20Q8zelPiOYcaDN3XZNu5sJQVlW6iX7C99exw P/z8yGxQvwCH4SefmYohsT8TXZmeA5VH67IhlLZEW45dFjVpOSdnnuDyaq64kgKTZ95K 00AU7pVrDN6QCzEFwScU5dyAaqX8Tbsi4hxUD3UtUYHGELBn8F0RzKsqjjJaGoHFyOIy iNBg== X-Gm-Message-State: AOAM5302CRtwJxGDcYzYRI6DcQ3MQCgS6eS2Ro/QY4JmW9OPenCC14Lt ir2QsgVvu3dWBjCPbAmlj9sCHA== X-Google-Smtp-Source: ABdhPJzyRb0pgwW+hkvXgmD5vgI/yUy7mnPtvBOPR3Pc6/kt7iIkuJyE7VE61GhHoAJGTrQIdU9cvw== X-Received: by 2002:a05:6000:1681:b0:207:acc5:85f6 with SMTP id y1-20020a056000168100b00207acc585f6mr133502wrd.595.1649690480633; Mon, 11 Apr 2022 08:21:20 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bk1-20020a0560001d8100b002061d6bdfd0sm19512832wrb.63.2022.04.11.08.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 08:21:20 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v3 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Mon, 11 Apr 2022 15:21:14 +0000 Message-Id: <20220411152114.2165933-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1178.g4f1659d476-goog In-Reply-To: <20220411152114.2165933-1-fabiobaltieri@chromium.org> References: <20220411152114.2165933-1-fabiobaltieri@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 +++++---- .../boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 7 ++++--- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 5 +++-- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 13 files changed, 28 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.= dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible =3D "pwm-leds"; keyboard_backlight: keyboard-backlight { label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; }; =20 -&cros_ec_pwm { +&cros_ec_pwm_type { status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/= arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..8474bd3af6eb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,8 +92,8 @@ volume_up { }; =20 &cros_ec { - cros_ec_pwm: ec-pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: ec-pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" =20 diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm= 64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..aea7c66d95e0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status =3D "okay"; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &camcc { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot= /dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..6552e0025f84 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include =20 @@ -316,7 +317,7 @@ backlight: backlight { num-interpolated-steps =3D <64>; default-brightness-level =3D <951>; =20 - pwms =3D <&cros_ec_pwm 1>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -354,7 +355,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -637,8 +638,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/a= rch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 1779d96c30f6..628ef990433b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include #include =20 @@ -336,7 +337,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -705,8 +706,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..eb4b0e17adec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ =20 #include #include +#include =20 #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -288,7 +289,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status =3D "disabled"; label =3D "cros_ec::kbd_backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness =3D <1023>; }; }; @@ -421,8 +422,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-idp-ec-h1.dtsi index a7c346aa3b02..a797f09e1328 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,8 +20,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ap_ec_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/d= ts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..a57951a50cd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include "sdm845.dtsi" =20 @@ -27,7 +28,7 @@ chosen { =20 backlight: backlight { compatible =3D "pwm-backlight"; - pwms =3D <&cros_ec_pwm 0>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply =3D <&ppvar_sys>; pinctrl-names =3D "default"; @@ -708,8 +709,8 @@ cros_ec: ec@0 { pinctrl-0 =3D <&ec_ap_int_l>; spi-max-frequency =3D <3000000>; =20 - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/b= oot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature =3D <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch= /arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..28eda361dfe1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply =3D <&pp3300_disp>; pinctrl-names =3D "default"; pinctrl-0 =3D <&bl_en>; + pwms =3D <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us =3D <10000>; }; =20 @@ -462,8 +463,8 @@ ap_i2c_tp: &i2c5 { }; =20 &cros_ec { - cros_ec_pwm: pwm { - compatible =3D "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible =3D "google,cros-ec-pwm-type"; #pwm-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64= /boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; =20 -&backlight { - pwms =3D <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names =3D "default"; pinctrl-0 =3D <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot= /dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi" =20 --=20 2.35.1.1178.g4f1659d476-goog