From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E9E2C433FE for ; Mon, 11 Apr 2022 09:35:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344458AbiDKJiF (ORCPT ); Mon, 11 Apr 2022 05:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344443AbiDKJiA (ORCPT ); Mon, 11 Apr 2022 05:38:00 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A77AF17061; Mon, 11 Apr 2022 02:35:46 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id h5so12745615pgc.7; Mon, 11 Apr 2022 02:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4TBdVKiMZGgqW7QCg6Hmi31rhc6KOuzjce0DwU5k9a4=; b=kRV08x7jnBBaAy8cGOSdHBNOy5+hfaeyDC2YtOZA73B6lL3hKkJAdKJ7Ye9JakgHjI XA8eZub1qer5QXTwiMlrxx/ZkobDfAs5Vs/+ift+jPL3bud/p2Go52nI64a5B0UuTkHo /DOWQefB3GLK2nyItBtzu5Bk/qL7tl7ZAZccy1BUmX0ZwKmluGdbdPpMfphorO/9WhUL GUH189vj0fYCNPUpokwf8APtIo9leeVhMCGZQ4Wm0YtXoJco/yRe3h0dyvZBWKw8dRkv il/VtAjQmF4maIqeFg2VPPmn9A4jvorSNqUFk6u5Fq0abNfcbK4yn6eLpbWO9OMF60ia ES6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4TBdVKiMZGgqW7QCg6Hmi31rhc6KOuzjce0DwU5k9a4=; b=3p1sqm8idD+bsCsCSoivr4OZHR38lLm1R1XT6rouuRi+R87jYsH1tQDVbFpnzIUMJp 6j1Y+w3O6ZAW6TBLsUYrvqON+kMfjQS95H5G2qcJdToIOhRoU2YdgL84VvX5x2S+RVb6 9B/tMYN6GpA84+zvkw8NWflqBFG66dlqLmlRCmWLpahQG0R9hPso9St8ZcqOdaqCdaH0 wb11hdnKWyqzRUubayZhUGuMUpoSYuPyxMU94WAn4KMkmHfrHTyswpXtYpJ+703x+eh7 pSwFAN0PffANvR7VToo5K8qgp+NS+r4u4EYiPSUMVuGl/5BDjIgOfaXvnrnmQs4r6VBF BMyA== X-Gm-Message-State: AOAM533p8Sxo7xh5IEkvykgnogO32C4ttdvQj/6LCGV6iCjsaJ5a0cK+ syvn/OqxK9tVIJXavLW8cXRwToi+ljc= X-Google-Smtp-Source: ABdhPJziX2EdrB3pd2UFPUnclSEVJWo6jjiSs02Eb6LhxIQIGjOD6hplUQCezCbxooUB7S5k0+DypQ== X-Received: by 2002:a05:6a00:1683:b0:4f7:e497:6a55 with SMTP id k3-20020a056a00168300b004f7e4976a55mr31692166pfc.21.1649669746076; Mon, 11 Apr 2022 02:35:46 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.111]) by smtp.gmail.com with ESMTPSA id k10-20020a056a00168a00b004f7e2a550ccsm34034426pfc.78.2022.04.11.02.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 02:35:45 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 01/11] KVM: x86/pmu: Update comments for AMD gp counters Date: Mon, 11 Apr 2022 17:35:27 +0800 Message-Id: <20220411093537.11558-2-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu The obsolete comment could more accurately state that AMD platforms have two base MSR addresses and two different maximum numbers for gp counters, depending on the X86_FEATURE_PERFCTR_CORE feature. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 618f529f1c4d..b52676f86562 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -34,7 +34,9 @@ * However AMD doesn't support fixed-counters; * - There are three types of index to access perf counters (PMC): * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD - * has MSR_K7_PERFCTRn. + * has MSR_K7_PERFCTRn and, for families 15H and later, + * MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are + * aliased to MSR_K7_PERFCTRn. * 2. MSR Index (named idx): This normally is used by RDPMC instructio= n. * For instance AMD RDPMC instruction uses 0000_0003h in ECX to acc= ess * C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, exce= pt @@ -46,7 +48,8 @@ * between pmc and perf counters is as the following: * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=3D> gp counters * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=3D> = fixed - * * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=3D> gp counters + * * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H + * and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=3D> gp counters */ =20 static struct kvm_pmu_ops kvm_pmu_ops __read_mostly; --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFCE6C433EF for ; Mon, 11 Apr 2022 09:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344468AbiDKJiI (ORCPT ); Mon, 11 Apr 2022 05:38:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344444AbiDKJiD (ORCPT ); Mon, 11 Apr 2022 05:38:03 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A707917040; Mon, 11 Apr 2022 02:35:49 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id p25so7372479pfn.13; Mon, 11 Apr 2022 02:35:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S3CmUzSdA0RYNyNJRXH3lJpoghz9EL53OwgRkYTpCfM=; b=jqBNyi1p17ZlXd5wyyexOmujQLCHTJvKkaQqHtJTC5RVtgwZeRfUzpX1kFumK1BFdy ixmMlRx4zaRoUpc/adZL/ePE9bAd4ol2VCjLSTwZJjP/d7PeQlJmQqeQUBSqnOn9IFUH l1O+TzhEAwPkZPsKfSzNm1m2NSquByTJtk2EY4JY1gFEV9UnPoJd6+Wi9rkeX+0gZDTC DvJdclySrPCGCiypCeHa85ZjBNcAAn0yrxVT0TGgnuJ9th/0VJrwU2rkc1myXsU4fxZ9 GPRUwgXbEqf+oTOQTDGQw+T1Rtqo/h0ahLIZ/NPZ6TXBFv89lDO4UUzMBFrbpmlEMyEL eV+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S3CmUzSdA0RYNyNJRXH3lJpoghz9EL53OwgRkYTpCfM=; b=3y+TPk/k6mAobTKj/pljG2++JTSpuVI9GLsSavyjRMmnGowLgcjxXcIDi1B71u0eHJ Ai62ISh2ZnD0mj4ZVdLVPM9xRBTcIjO/0gYGJpmKPfcYUllZNy4StWQG56UBmev/arN2 0ERdMa+TOVOOaOV9eKpeWPT//p2CC31TNJFoVRLS3V6Q99KO3pi9qc6XVFzIfTblq8rW b4pV4gZZhFBqS127sw8hRrJi3IJJH07qY+DAYnl4j+qf3u1Jn8tQlWicMuqtHLc3XUzx 5d7RTCEgl/STMgVBs8spFynhvvTPbMsE4hx2kYH0NVAlDfLAAZyCuTkBwH26iMOUQvqp TlaA== X-Gm-Message-State: AOAM531nMHPKz5KyAVAfyqnhRIFzx8NQlx6+v0ENPenJB5jWDW4vWekY Jx/NrUBv5qsdjFeotu7vaWM= X-Google-Smtp-Source: ABdhPJwp1WjZtcT1MItnPzEdlgZElWGWjyIsTX3fHj+49OqaXJFlkZ5+6NHUsF+zhnoQqeZpsJshMg== X-Received: by 2002:a63:fc18:0:b0:39c:f431:8310 with SMTP id j24-20020a63fc18000000b0039cf4318310mr13281487pgi.433.1649669749223; Mon, 11 Apr 2022 02:35:49 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.111]) by smtp.gmail.com with ESMTPSA id k10-20020a056a00168a00b004f7e2a550ccsm34034426pfc.78.2022.04.11.02.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 02:35:49 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 02/11] KVM: x86/pmu: Extract check_pmu_event_filter() from the same semantics Date: Mon, 11 Apr 2022 17:35:28 +0800 Message-Id: <20220411093537.11558-3-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Checking the kvm->arch.pmu_event_filter policy in both gp and fixed code paths was somewhat redundant, so common parts can be extracted, which reduces code footprint and improves readability. Signed-off-by: Like Xu Reviewed-by: Wanpeng Li --- arch/x86/kvm/pmu.c | 63 +++++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 26 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index b52676f86562..00436933d13c 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -205,14 +205,44 @@ static int cmp_u64(const void *a, const void *b) return *(__u64 *)a - *(__u64 *)b; } =20 +static bool check_pmu_event_filter(struct kvm_pmc *pmc) +{ + struct kvm_pmu_event_filter *filter; + struct kvm *kvm =3D pmc->vcpu->kvm; + bool allow_event =3D true; + __u64 key; + int idx; + + filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); + if (!filter) + goto out; + + if (pmc_is_gp(pmc)) { + key =3D pmc->eventsel & AMD64_RAW_EVENT_MASK_NB; + if (bsearch(&key, filter->events, filter->nevents, + sizeof(__u64), cmp_u64)) + allow_event =3D filter->action =3D=3D KVM_PMU_EVENT_ALLOW; + else + allow_event =3D filter->action =3D=3D KVM_PMU_EVENT_DENY; + } else { + idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; + if (filter->action =3D=3D KVM_PMU_EVENT_DENY && + test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) + allow_event =3D false; + if (filter->action =3D=3D KVM_PMU_EVENT_ALLOW && + !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) + allow_event =3D false; + } + +out: + return allow_event; +} + void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) { u64 config; u32 type =3D PERF_TYPE_RAW; - struct kvm *kvm =3D pmc->vcpu->kvm; - struct kvm_pmu_event_filter *filter; - struct kvm_pmu *pmu =3D vcpu_to_pmu(pmc->vcpu); - bool allow_event =3D true; + struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); =20 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) printk_once("kvm pmu: pin control bit is ignored\n"); @@ -224,17 +254,7 @@ void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eve= ntsel) if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) return; =20 - filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); - if (filter) { - __u64 key =3D eventsel & AMD64_RAW_EVENT_MASK_NB; - - if (bsearch(&key, filter->events, filter->nevents, - sizeof(__u64), cmp_u64)) - allow_event =3D filter->action =3D=3D KVM_PMU_EVENT_ALLOW; - else - allow_event =3D filter->action =3D=3D KVM_PMU_EVENT_DENY; - } - if (!allow_event) + if (!check_pmu_event_filter(pmc)) return; =20 if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | @@ -267,23 +287,14 @@ void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 = ctrl, int idx) { unsigned en_field =3D ctrl & 0x3; bool pmi =3D ctrl & 0x8; - struct kvm_pmu_event_filter *filter; - struct kvm *kvm =3D pmc->vcpu->kvm; =20 pmc_pause_counter(pmc); =20 if (!en_field || !pmc_is_enabled(pmc)) return; =20 - filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); - if (filter) { - if (filter->action =3D=3D KVM_PMU_EVENT_DENY && - test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) - return; - if (filter->action =3D=3D KVM_PMU_EVENT_ALLOW && - !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap)) - return; - } + if (!check_pmu_event_filter(pmc)) + return; =20 if (pmc->current_config =3D=3D (u64)ctrl && pmc_resume_counter(pmc)) return; --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2E81C433EF for ; Mon, 11 Apr 2022 09:36:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344488AbiDKJiO (ORCPT ); Mon, 11 Apr 2022 05:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344443AbiDKJiG (ORCPT ); Mon, 11 Apr 2022 05:38:06 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3A6E192B5; Mon, 11 Apr 2022 02:35:52 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id t4so13703202pgc.1; Mon, 11 Apr 2022 02:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ctb/Dmpvifb3cPDaFvWsUP/a3QdJdiSG7ihOCp2uZLY=; b=jtrh/M5Jl58UeeShmz+plGV4GGiXAIXW8of66nHuIr5Qh/mq05gAjEpjvBBkADZa9/ Fi/eCV02HPU4HzvM5vPyYGf2XtF9VVzUPgvgahMP3nci6+hzlWLAELWsvEhyW+czmagK 6/dtXuTKb8yO2LXuJGaaovrTM92Vu0A7/7AizTxQj8/0NzytkhQ4dfAWgsPcJjD1VcjL waTTKKM9sMRLWtwE7ROTih/UqwUf9w91NfkaSO7GICjxKaxaDK/wOy0BtWSRMavIaJEM KQw7zzX9bM4T94/7UpApCLkEY7griv9ohGvgLi8ysQiplGLS3pmCpCJoVOVR7m3At+ra /W7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ctb/Dmpvifb3cPDaFvWsUP/a3QdJdiSG7ihOCp2uZLY=; b=vCY0wzoG7c2W2cE6dKlx7vFVGiSPCHe00s7yjd7Abl2LImeVGaCYRfzO8SlRsMa9aB KBqFr9911Y7lUJp6AwcXAYSqXyN59cR933sy51of92pDATCe7GhvW3BHFMpKHtOVbd8i f2jbzE8U/evHRUwxNZlWxakjeH2b3A0bEAhZNqyK6dj14OmAEHi0t+11Hg1tVHlm4rMk z/BEprZKiD5zgFB/5szQ5yuh3VtFzlL0M4v2HPBG9IWApG+z+V+a/kiKMC5sMDzby6qX SX4TQ/j206sN/15FFqWNubIuKPJkz11+vg1hqTZTxuMFFte08sKOygRF+/S6gKQYy6yl Rq1w== X-Gm-Message-State: AOAM531MCsr9w8cMiOL6/DMvmSibC9WH1iObpdZwl4e1CV7J1Dg4xC6a DiWOKpYXgjyF4IRcceq7D9I= X-Google-Smtp-Source: ABdhPJz+78kqBrLnbR8pHgH159B+u1ynq2i1ACTIAAJ5+SbHzm/4GY8mPH9ojFXj11Jr/ApmaPa4BQ== X-Received: by 2002:a63:3e0c:0:b0:398:2829:58cd with SMTP id l12-20020a633e0c000000b00398282958cdmr25943204pga.464.1649669752487; Mon, 11 Apr 2022 02:35:52 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.111]) by smtp.gmail.com with ESMTPSA id k10-20020a056a00168a00b004f7e2a550ccsm34034426pfc.78.2022.04.11.02.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 02:35:52 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 03/11] KVM: x86/pmu: Protect kvm->arch.pmu_event_filter with SRCU Date: Mon, 11 Apr 2022 17:35:29 +0800 Message-Id: <20220411093537.11558-4-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Similar to "kvm->arch.msr_filter", KVM should guarantee that vCPUs will see either the previous filter or the new filter when user space calls KVM_SET_PMU_EVENT_FILTER ioctl with the vCPU running so that guest pmu events with identical settings in both the old and new filter have deterministic behavior. Fixes: 66bb8a065f5a ("KVM: x86: PMU Event Filter") Signed-off-by: Like Xu Reviewed-by: Wanpeng Li --- arch/x86/kvm/pmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 00436933d13c..adbf07695e1f 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -211,8 +211,9 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) struct kvm *kvm =3D pmc->vcpu->kvm; bool allow_event =3D true; __u64 key; - int idx; + int idx, srcu_idx; =20 + srcu_idx =3D srcu_read_lock(&kvm->srcu); filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); if (!filter) goto out; @@ -235,6 +236,7 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) } =20 out: + srcu_read_unlock(&kvm->srcu, srcu_idx); return allow_event; } =20 --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 882C6C433FE for ; Mon, 11 Apr 2022 09:36:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344494AbiDKJiQ (ORCPT ); Mon, 11 Apr 2022 05:38:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344471AbiDKJiJ (ORCPT ); Mon, 11 Apr 2022 05:38:09 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C6531AF27; Mon, 11 Apr 2022 02:35:56 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id y8so8948267pfw.0; Mon, 11 Apr 2022 02:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1KF6+6/OPXYFT8NZlyT7/xmed8GjZlNYgDHQ02cnYrw=; b=Yd0/CPNVSEIOVRYtL6PIZTbaC1FlO0jKhjRBRDaCp8Y1DIhHUFNEZ7RigfrCudggLY zOZh436FlV3A5HuJcVcT2MB+SpOV0gm+EFnP6w/zFTpAPOVBNb5dTfGxDw73pzN79Gfv 28oa5W9WBm6cTv//9tdy6ylHtO4jfeyegYh4foD95UMlyU6rVdI1AQpNYiz/E70yx7hp lb6bJ9Zp69QsvVlbbh0obXFIO3o5TxO7lFfGSDTicvOj7R5vTUcEBLCNUAmwxm8Pq2Wd NI34zfedffJZN+5exw3ymptFQ45YMvH6fSLyHh7BCPDuBlISdvw+8VPLSmXD2EPBRKnT RPHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1KF6+6/OPXYFT8NZlyT7/xmed8GjZlNYgDHQ02cnYrw=; b=Jah3ackhTShjuMWWUVB9K1pAWTjrUX9ckTe6A8y02sz83Dqv8eEzmacHZOfs584UiN B4XHkG5vRSZwM45o9hn8/KwQ14BO7D8+rNfoeimf3Ju9fAa59rKORoYF9IGrdZuPuV7n ZWSwBd5wfdKexTeSSCB7H6gY9kf4ueP7DHxK0sOKAFnnlX/tJy9v4D1jmLySi5NZQWAG 5Dr+kASyRFihgEb+iGACvXA1sU8hmBmOP+5bqapNXQAC6u+0oFVe7Rw25uYHD5yxnJJ3 ZnftU1YmMk8merPTFqGYgdY0skf9SlgE4Cd3vMtcfZzyF3cinfCWGQpfyoB2RtAw5JSu XPtw== X-Gm-Message-State: AOAM532tdMir/Ugqj7f17qZj9ncUG4U3B6X9FCDiiHWFtoEkvyjw7pac iAQCASKfy1ItzlfWULO1cXk= X-Google-Smtp-Source: ABdhPJyvZ69alcJ1qVtVZsyqrpWWhGwIisnUme4+VeTanfmmb6G5yU8i4xiobWbQBkfKYpwT5zdM0w== X-Received: by 2002:a05:6a00:1acb:b0:4fb:358f:fe87 with SMTP id f11-20020a056a001acb00b004fb358ffe87mr32002184pfv.75.1649669755677; Mon, 11 Apr 2022 02:35:55 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.111]) by smtp.gmail.com with ESMTPSA id k10-20020a056a00168a00b004f7e2a550ccsm34034426pfc.78.2022.04.11.02.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 02:35:55 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 04/11] KVM: x86/pmu: Pass only "struct kvm_pmc *pmc" to reprogram_counter() Date: Mon, 11 Apr 2022 17:35:30 +0800 Message-Id: <20220411093537.11558-5-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Passing the reference "struct kvm_pmc *pmc" when creating pmc->perf_event is sufficient. This change helps to simplify the calling convention by replacing reprogram_{gp, fixed}_counter() with reprogram_counter() seamlessly. No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 17 +++++------------ arch/x86/kvm/pmu.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 32 ++++++++++++++++++-------------- 3 files changed, 24 insertions(+), 27 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index adbf07695e1f..51035bd29511 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -312,18 +312,13 @@ void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 = ctrl, int idx) } EXPORT_SYMBOL_GPL(reprogram_fixed_counter); =20 -void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx) +void reprogram_counter(struct kvm_pmc *pmc) { - struct kvm_pmc *pmc =3D static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, pmc_= idx); - - if (!pmc) - return; - if (pmc_is_gp(pmc)) reprogram_gp_counter(pmc, pmc->eventsel); else { - int idx =3D pmc_idx - INTEL_PMC_IDX_FIXED; - u8 ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx); + int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; + u8 ctrl =3D fixed_ctrl_field(pmc_to_pmu(pmc)->fixed_ctr_ctrl, idx); =20 reprogram_fixed_counter(pmc, ctrl, idx); } @@ -342,8 +337,7 @@ void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) clear_bit(bit, pmu->reprogram_pmi); continue; } - - reprogram_counter(pmu, bit); + reprogram_counter(pmc); } =20 /* @@ -527,13 +521,12 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu) =20 static void kvm_pmu_incr_counter(struct kvm_pmc *pmc) { - struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); u64 prev_count; =20 prev_count =3D pmc->counter; pmc->counter =3D (pmc->counter + 1) & pmc_bitmask(pmc); =20 - reprogram_counter(pmu, pmc->idx); + reprogram_counter(pmc); if (pmc->counter < prev_count) __kvm_perf_overflow(pmc, false); } diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 2a53b6c9495c..dbcac971babb 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -137,7 +137,7 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc= , u64 counter_value) =20 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); -void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx); +void reprogram_counter(struct kvm_pmc *pmc); =20 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 9db662399487..2feff54e2e45 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -56,16 +56,32 @@ static void reprogram_fixed_counters(struct kvm_pmu *pm= u, u64 data) pmu->fixed_ctr_ctrl =3D data; } =20 +static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_i= dx) +{ + if (pmc_idx < INTEL_PMC_IDX_FIXED) { + return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, + MSR_P6_EVNTSEL0); + } else { + u32 idx =3D pmc_idx - INTEL_PMC_IDX_FIXED; + + return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0); + } +} + /* function is called when global control register has been updated. */ static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data) { int bit; u64 diff =3D pmu->global_ctrl ^ data; + struct kvm_pmc *pmc; =20 pmu->global_ctrl =3D data; =20 - for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) - reprogram_counter(pmu, bit); + for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) { + pmc =3D intel_pmc_idx_to_pmc(pmu, bit); + if (pmc) + reprogram_counter(pmc); + } } =20 static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc) @@ -101,18 +117,6 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); } =20 -static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_i= dx) -{ - if (pmc_idx < INTEL_PMC_IDX_FIXED) - return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, - MSR_P6_EVNTSEL0); - else { - u32 idx =3D pmc_idx - INTEL_PMC_IDX_FIXED; - - return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0); - } -} - static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int i= dx) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB104C433F5 for ; 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Mon, 11 Apr 2022 02:35:58 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 05/11] KVM: x86/pmu: Drop "u64 eventsel" for reprogram_gp_counter() Date: Mon, 11 Apr 2022 17:35:31 +0800 Message-Id: <20220411093537.11558-6-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Because inside reprogram_gp_counter() it is bound to assign the requested eventel to pmc->eventsel, this assignment step can be moved forward, thus simplifying the passing of parameters to "struct kvm_pmc *pmc" only. No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 7 +++---- arch/x86/kvm/pmu.h | 2 +- arch/x86/kvm/svm/pmu.c | 6 ++++-- arch/x86/kvm/vmx/pmu_intel.c | 3 ++- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 51035bd29511..419f44847520 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -240,17 +240,16 @@ static bool check_pmu_event_filter(struct kvm_pmc *pm= c) return allow_event; } =20 -void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) +void reprogram_gp_counter(struct kvm_pmc *pmc) { u64 config; u32 type =3D PERF_TYPE_RAW; struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); + u64 eventsel =3D pmc->eventsel; =20 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) printk_once("kvm pmu: pin control bit is ignored\n"); =20 - pmc->eventsel =3D eventsel; - pmc_pause_counter(pmc); =20 if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) @@ -315,7 +314,7 @@ EXPORT_SYMBOL_GPL(reprogram_fixed_counter); void reprogram_counter(struct kvm_pmc *pmc) { if (pmc_is_gp(pmc)) - reprogram_gp_counter(pmc, pmc->eventsel); + reprogram_gp_counter(pmc); else { int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; u8 ctrl =3D fixed_ctrl_field(pmc_to_pmu(pmc)->fixed_ctr_ctrl, idx); diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index dbcac971babb..5ec34b940fa1 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -135,7 +135,7 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc= , u64 counter_value) return sample_period; } =20 -void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); +void reprogram_gp_counter(struct kvm_pmc *pmc); void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); void reprogram_counter(struct kvm_pmc *pmc); =20 diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 57ab4739eb19..2794a29b3f54 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -263,8 +263,10 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, stru= ct msr_data *msr_info) pmc =3D get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); if (pmc) { data &=3D ~pmu->reserved_bits; - if (data !=3D pmc->eventsel) - reprogram_gp_counter(pmc, data); + if (data !=3D pmc->eventsel) { + pmc->eventsel =3D data; + reprogram_gp_counter(pmc); + } return 0; } =20 diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 2feff54e2e45..3bf8a22ea2e5 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -453,7 +453,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED)) reserved_bits ^=3D HSW_IN_TX_CHECKPOINTED; if (!(data & reserved_bits)) { - reprogram_gp_counter(pmc, data); + pmc->eventsel =3D data; + reprogram_gp_counter(pmc); return 0; } } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C83AC433F5 for ; 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Mon, 11 Apr 2022 02:36:01 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 06/11] KVM: x86/pmu: Drop "u8 ctrl, int idx" for reprogram_fixed_counter() Date: Mon, 11 Apr 2022 17:35:32 +0800 Message-Id: <20220411093537.11558-7-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Since afrer reprogram_fixed_counter() is called, it's bound to assign the requested fixed_ctr_ctrl to pmu->fixed_ctr_ctrl, this assignment step can be moved forward (the stale value for diff is saved extra early), thus simplifying the passing of parameters. No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 13 ++++++------- arch/x86/kvm/pmu.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 16 ++++++++-------- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 419f44847520..23c7f3cfcc6b 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -284,8 +284,11 @@ void reprogram_gp_counter(struct kvm_pmc *pmc) } EXPORT_SYMBOL_GPL(reprogram_gp_counter); =20 -void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx) +void reprogram_fixed_counter(struct kvm_pmc *pmc) { + struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); + int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; + u8 ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx); unsigned en_field =3D ctrl & 0x3; bool pmi =3D ctrl & 0x8; =20 @@ -315,12 +318,8 @@ void reprogram_counter(struct kvm_pmc *pmc) { if (pmc_is_gp(pmc)) reprogram_gp_counter(pmc); - else { - int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; - u8 ctrl =3D fixed_ctrl_field(pmc_to_pmu(pmc)->fixed_ctr_ctrl, idx); - - reprogram_fixed_counter(pmc, ctrl, idx); - } + else + reprogram_fixed_counter(pmc); } EXPORT_SYMBOL_GPL(reprogram_counter); =20 diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 5ec34b940fa1..9ea01fe02802 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -136,7 +136,7 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc= , u64 counter_value) } =20 void reprogram_gp_counter(struct kvm_pmc *pmc); -void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx); +void reprogram_fixed_counter(struct kvm_pmc *pmc); void reprogram_counter(struct kvm_pmc *pmc); =20 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 3bf8a22ea2e5..ce71ad29643c 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -37,23 +37,23 @@ static int fixed_pmc_events[] =3D {1, 0, 7}; =20 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) { + struct kvm_pmc *pmc; + u8 old_fixed_ctr_ctrl =3D pmu->fixed_ctr_ctrl; int i; =20 + pmu->fixed_ctr_ctrl =3D data; for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) { u8 new_ctrl =3D fixed_ctrl_field(data, i); - u8 old_ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, i); - struct kvm_pmc *pmc; - - pmc =3D get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); + u8 old_ctrl =3D fixed_ctrl_field(old_fixed_ctr_ctrl, i); =20 if (old_ctrl =3D=3D new_ctrl) continue; =20 - __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); - reprogram_fixed_counter(pmc, new_ctrl, i); - } + pmc =3D get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); =20 - pmu->fixed_ctr_ctrl =3D data; + __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); + reprogram_fixed_counter(pmc); + } } =20 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_i= dx) --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2529BC433F5 for ; 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Mon, 11 Apr 2022 02:36:04 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 07/11] KVM: x86/pmu: Use only the uniformly exported interface reprogram_counter() Date: Mon, 11 Apr 2022 17:35:33 +0800 Message-Id: <20220411093537.11558-8-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Since reprogram_counter(), reprogram_{gp, fixed}_counter() currently have the same incoming parameter "struct kvm_pmc *pmc", the callers can simplify the conetxt by using uniformly exported interface, which makes reprogram_ {gp, fixed}_counter() static and eliminates EXPORT_SYMBOL_GPL. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 6 ++---- arch/x86/kvm/pmu.h | 2 -- arch/x86/kvm/svm/pmu.c | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 4 ++-- 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 23c7f3cfcc6b..598b19223965 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -240,7 +240,7 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) return allow_event; } =20 -void reprogram_gp_counter(struct kvm_pmc *pmc) +static void reprogram_gp_counter(struct kvm_pmc *pmc) { u64 config; u32 type =3D PERF_TYPE_RAW; @@ -282,9 +282,8 @@ void reprogram_gp_counter(struct kvm_pmc *pmc) !(eventsel & ARCH_PERFMON_EVENTSEL_OS), eventsel & ARCH_PERFMON_EVENTSEL_INT); } -EXPORT_SYMBOL_GPL(reprogram_gp_counter); =20 -void reprogram_fixed_counter(struct kvm_pmc *pmc) +static void reprogram_fixed_counter(struct kvm_pmc *pmc) { struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; @@ -312,7 +311,6 @@ void reprogram_fixed_counter(struct kvm_pmc *pmc) !(en_field & 0x1), /* exclude kernel */ pmi); } -EXPORT_SYMBOL_GPL(reprogram_fixed_counter); =20 void reprogram_counter(struct kvm_pmc *pmc) { diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 9ea01fe02802..f4a799816c51 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -135,8 +135,6 @@ static inline u64 get_sample_period(struct kvm_pmc *pmc= , u64 counter_value) return sample_period; } =20 -void reprogram_gp_counter(struct kvm_pmc *pmc); -void reprogram_fixed_counter(struct kvm_pmc *pmc); void reprogram_counter(struct kvm_pmc *pmc); =20 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 2794a29b3f54..ebec2b478ac1 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -265,7 +265,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) data &=3D ~pmu->reserved_bits; if (data !=3D pmc->eventsel) { pmc->eventsel =3D data; - reprogram_gp_counter(pmc); + reprogram_counter(pmc); } return 0; } diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ce71ad29643c..1f910b349978 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -52,7 +52,7 @@ static void reprogram_fixed_counters(struct kvm_pmu *pmu,= u64 data) pmc =3D get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); =20 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); - reprogram_fixed_counter(pmc); + reprogram_counter(pmc); } } =20 @@ -454,7 +454,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) reserved_bits ^=3D HSW_IN_TX_CHECKPOINTED; if (!(data & reserved_bits)) { pmc->eventsel =3D data; - reprogram_gp_counter(pmc); + reprogram_counter(pmc); return 0; } } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false)) --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 062C2C433FE for ; Mon, 11 Apr 2022 09:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344541AbiDKJi4 (ORCPT ); Mon, 11 Apr 2022 05:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344504AbiDKJic (ORCPT ); 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Mon, 11 Apr 2022 02:36:07 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu , Peter Zijlstra Subject: [PATCH v3 08/11] KVM: x86/pmu: Use PERF_TYPE_RAW to merge reprogram_{gp,fixed}counter() Date: Mon, 11 Apr 2022 17:35:34 +0800 Message-Id: <20220411093537.11558-9-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu The code sketch for reprogram_{gp, fixed}_counter() is similar, while the fixed counter using the PERF_TYPE_HARDWAR type and the gp being able to use either PERF_TYPE_HARDWAR or PERF_TYPE_RAW type depending on the pmc->eventsel value. After 'commit 761875634a5e ("KVM: x86/pmu: Setup pmc->eventsel for fixed PMCs")', the pmc->eventsel of the fixed counter will also have been setup with the same semantic value and will not be changed during the guest runtime. The original story of using the PERF_TYPE_HARDWARE type is to emulate guest architecture PMU on a host without architecture PMU (the Pentium 4), for which the guest vPMC needs to be reprogrammed using the kernel generic perf_hw_id. But essentially, "the HARDWARE is just a convenience wrapper over RAW IIRC", quoated from Peterz. So it could be pretty safe to use the PERF_TYPE_RAW type only in practice to program both gp and fixed counters naturally in the reprogram_counter(). To make the gp and fixed counters more semantically symmetrical, the selection of EVENTSEL_{USER, OS, INT} bits is temporarily translated via fixed_ctr_ctrl before the pmc_reprogram_counter() call. Cc: Peter Zijlstra Suggested-by: Jim Mattson Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 125 ++++++++++++----------------------- arch/x86/kvm/vmx/pmu_intel.c | 3 +- 2 files changed, 46 insertions(+), 82 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 598b19223965..58960844f49f 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -240,84 +240,58 @@ static bool check_pmu_event_filter(struct kvm_pmc *pm= c) return allow_event; } =20 -static void reprogram_gp_counter(struct kvm_pmc *pmc) -{ - u64 config; - u32 type =3D PERF_TYPE_RAW; - struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); - u64 eventsel =3D pmc->eventsel; - - if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) - printk_once("kvm pmu: pin control bit is ignored\n"); - - pmc_pause_counter(pmc); - - if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) - return; - - if (!check_pmu_event_filter(pmc)) - return; - - if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | - ARCH_PERFMON_EVENTSEL_INV | - ARCH_PERFMON_EVENTSEL_CMASK | - HSW_IN_TX | - HSW_IN_TX_CHECKPOINTED))) { - config =3D static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc); - if (config !=3D PERF_COUNT_HW_MAX) - type =3D PERF_TYPE_HARDWARE; - } - - if (type =3D=3D PERF_TYPE_RAW) - config =3D eventsel & pmu->raw_event_mask; - - if (pmc->current_config =3D=3D eventsel && pmc_resume_counter(pmc)) - return; - - pmc_release_perf_event(pmc); - - pmc->current_config =3D eventsel; - pmc_reprogram_counter(pmc, type, config, - !(eventsel & ARCH_PERFMON_EVENTSEL_USR), - !(eventsel & ARCH_PERFMON_EVENTSEL_OS), - eventsel & ARCH_PERFMON_EVENTSEL_INT); -} - -static void reprogram_fixed_counter(struct kvm_pmc *pmc) +static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc) { struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); - int idx =3D pmc->idx - INTEL_PMC_IDX_FIXED; - u8 ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx); - unsigned en_field =3D ctrl & 0x3; - bool pmi =3D ctrl & 0x8; =20 - pmc_pause_counter(pmc); + if (pmc_is_fixed(pmc)) + return fixed_ctrl_field(pmu->fixed_ctr_ctrl, + pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3; =20 - if (!en_field || !pmc_is_enabled(pmc)) - return; - - if (!check_pmu_event_filter(pmc)) - return; - - if (pmc->current_config =3D=3D (u64)ctrl && pmc_resume_counter(pmc)) - return; - - pmc_release_perf_event(pmc); - - pmc->current_config =3D (u64)ctrl; - pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE, - static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc), - !(en_field & 0x2), /* exclude user */ - !(en_field & 0x1), /* exclude kernel */ - pmi); + return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; } =20 void reprogram_counter(struct kvm_pmc *pmc) { - if (pmc_is_gp(pmc)) - reprogram_gp_counter(pmc); - else - reprogram_fixed_counter(pmc); + struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); + u64 eventsel =3D pmc->eventsel; + u64 new_config =3D eventsel; + u8 fixed_ctr_ctrl; + + pmc_pause_counter(pmc); + + if (!pmc_speculative_in_use(pmc) || !pmc_is_enabled(pmc)) + return; + + if (!check_pmu_event_filter(pmc)) + return; + + if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) + printk_once("kvm pmu: pin control bit is ignored\n"); + + if (pmc_is_fixed(pmc)) { + fixed_ctr_ctrl =3D fixed_ctrl_field(pmu->fixed_ctr_ctrl, + pmc->idx - INTEL_PMC_IDX_FIXED); + if (fixed_ctr_ctrl & 0x1) + eventsel |=3D ARCH_PERFMON_EVENTSEL_OS; + if (fixed_ctr_ctrl & 0x2) + eventsel |=3D ARCH_PERFMON_EVENTSEL_USR; + if (fixed_ctr_ctrl & 0x8) + eventsel |=3D ARCH_PERFMON_EVENTSEL_INT; + new_config =3D (u64)fixed_ctr_ctrl; + } + + if (pmc->current_config =3D=3D new_config && pmc_resume_counter(pmc)) + return; + + pmc_release_perf_event(pmc); + + pmc->current_config =3D new_config; + pmc_reprogram_counter(pmc, PERF_TYPE_RAW, + (eventsel & pmu->raw_event_mask), + !(eventsel & ARCH_PERFMON_EVENTSEL_USR), + !(eventsel & ARCH_PERFMON_EVENTSEL_OS), + eventsel & ARCH_PERFMON_EVENTSEL_INT); } EXPORT_SYMBOL_GPL(reprogram_counter); =20 @@ -474,17 +448,6 @@ void kvm_pmu_init(struct kvm_vcpu *vcpu) kvm_pmu_refresh(vcpu); } =20 -static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc) -{ - struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); - - if (pmc_is_fixed(pmc)) - return fixed_ctrl_field(pmu->fixed_ctr_ctrl, - pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3; - - return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; -} - /* Release perf_events for vPMCs that have been unused for a full time sli= ce. */ void kvm_pmu_cleanup(struct kvm_vcpu *vcpu) { diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 1f910b349978..11eb186929bc 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -498,7 +498,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->raw_event_mask =3D X86_RAW_EVENT_MASK; =20 entry =3D kvm_find_cpuid_entry(vcpu, 0xa, 0); - if (!entry || !vcpu->kvm->arch.enable_pmu) + if (!entry || !vcpu->kvm->arch.enable_pmu || + !boot_cpu_has(X86_FEATURE_ARCH_PERFMON)) return; eax.full =3D entry->eax; edx.full =3D entry->edx; --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E464C433F5 for ; Mon, 11 Apr 2022 09:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344520AbiDKJiy (ORCPT ); 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Mon, 11 Apr 2022 02:36:11 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu , Peter Zijlstra Subject: [PATCH v3 09/11] perf: x86/core: Add interface to query perfmon_event_map[] directly Date: Mon, 11 Apr 2022 17:35:35 +0800 Message-Id: <20220411093537.11558-10-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu Currently, we have [intel|knc|p4|p6]_perfmon_event_map on the Intel platforms and amd_[f17h]_perfmon_event_map on the AMD platforms. Early clumsy KVM code or other potential perf_event users may have hard-coded these perfmon_maps (e.g., arch/x86/kvm/svm/pmu.c), so it would not make sense to program a common hardware event based on the generic "enum perf_hw_id" once the two tables do not match. Let's provide an interface for callers outside the perf subsystem to get the counter config based on the perfmon_event_map currently in use, and it also helps to save bytes. Cc: Peter Zijlstra Signed-off-by: Like Xu Acked-by: Peter Zijlstra (Intel) --- arch/x86/events/core.c | 11 +++++++++++ arch/x86/include/asm/perf_event.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index eef816fc216d..091363bc545d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2996,3 +2996,14 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capa= bility *cap) cap->events_mask_len =3D x86_pmu.events_mask_len; } EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); + +u64 perf_get_hw_event_config(int hw_event) +{ + int max =3D x86_pmu.max_events; + + if (hw_event < max) + return x86_pmu.event_map(array_index_nospec(hw_event, max)); + + return 0; +} +EXPORT_SYMBOL_GPL(perf_get_hw_event_config); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 58d9e4b1fa0a..09ab495d738a 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -477,6 +477,7 @@ struct x86_pmu_lbr { }; =20 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); +extern u64 perf_get_hw_event_config(int hw_event); extern void perf_check_microcode(void); extern void perf_clear_dirty_counters(void); extern int x86_perf_rdpmc_index(struct perf_event *event); @@ -486,6 +487,11 @@ static inline void perf_get_x86_pmu_capability(struct = x86_pmu_capability *cap) memset(cap, 0, sizeof(*cap)); } =20 +static inline u64 perf_get_hw_event_config(int hw_event) +{ + return 0; +} + static inline void perf_events_lapic_init(void) { } static inline void perf_check_microcode(void) { } #endif --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C3AC433F5 for ; Mon, 11 Apr 2022 09:36:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344521AbiDKJit (ORCPT ); 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Mon, 11 Apr 2022 02:36:14 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 10/11] KVM: x86/pmu: Replace pmc_perf_hw_id() with perf_get_hw_event_config() Date: Mon, 11 Apr 2022 17:35:36 +0800 Message-Id: <20220411093537.11558-11-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu With the help of perf_get_hw_event_config(), KVM could query the correct EVENTSEL_{EVENT, UMASK} pair of a kernel-generic hw event directly from the different *_perfmon_event_map[] by the kernel's pre-defined perf_hw_id. Also extend the bit range of the comparison field to AMD64_RAW_EVENT_MASK_NB to prevent AMD from defining EventSelect[11:8] into perfmon_event_map[] one day. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 58960844f49f..f6fd85942a6b 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -493,13 +493,8 @@ static void kvm_pmu_incr_counter(struct kvm_pmc *pmc) static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc, unsigned int perf_hw_id) { - u64 old_eventsel =3D pmc->eventsel; - unsigned int config; - - pmc->eventsel &=3D (ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_U= MASK); - config =3D static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc); - pmc->eventsel =3D old_eventsel; - return config =3D=3D perf_hw_id; + return !((pmc->eventsel ^ perf_get_hw_event_config(perf_hw_id)) & + AMD64_RAW_EVENT_MASK_NB); } =20 static inline bool cpl_is_matched(struct kvm_pmc *pmc) --=20 2.35.1 From nobody Mon May 11 07:46:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 479FEC433FE for ; Mon, 11 Apr 2022 09:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241123AbiDKJil (ORCPT ); Mon, 11 Apr 2022 05:38:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344524AbiDKJid (ORCPT ); Mon, 11 Apr 2022 05:38:33 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A696403DC; Mon, 11 Apr 2022 02:36:18 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id p25so7373514pfn.13; Mon, 11 Apr 2022 02:36:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QbkEjkl9ftZFhzuzmbFjiq0IAVnlVCc+oIbvoqaNepo=; b=Oeg2hqNogXppBTMshhx7EhTcRcypOFNcVOjWw23BizQ7FU6BLSEEIsdfnlptpunYWk YwzB2jfTNTJ5PG0LCsQsDeA+r4/UFTrl2rXmkhfBRRsZMPdEF+DJruRiZzG6YMbHeCFZ dFtAsXhxXpciMG1TBZ/W9nO+2poVttbI+sN9HDB1m5ViaVvndRX53FG9W0EIgesRQVUu OrG6YJTvD3z4+OMlnCgKEZLSwBuxn4yKSkZdeg1KwHKrd8fU/FZGzs36/uMy15w0dhvA BVlORaShCWHQZIumCAlSZTXx1bPjPD+p3N8hw0UXuqI2Q2BOFbYaucQ/aHFHpz9qf8lH mxtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QbkEjkl9ftZFhzuzmbFjiq0IAVnlVCc+oIbvoqaNepo=; b=ZyUeoY/YhNxBdzBQq2ZrkqaYBUUzHurFXgOYvTZ5qghVhGZJJyv96iMlj0uYOwgJOx VbgY4cj+kMF/TSc0dYpX33pOCYRwQZIbYGhcsOVcgXvng8R3wlKiwMcVXB9TLSo6lMPV KHxmhuA+uyJfrdLWGQMH/6P4gi1PzlDxATekPe+naZUXHLfJKyPLPrkh2BJllLZ/rC/E uAIZ70oqh5Sxa9usmygNxAjcEcl+LVZ5eVgrDLPv6z/qVjRMdoX9YOI8/xIMAW8uQZ8y yGWtXADoT7yqr3DaA5UgvmCA3UZXx3Q2xGdiBg6OslDH0SAQ+SQ0ot955gQfPT3qKSwE cCoQ== X-Gm-Message-State: AOAM531nOKM67BdP6yYYaOm6Ykipd7ZDg5/EFdQGVuTo87HjmassXUYs kjuFspW3GB3mQlrXfx6digQ= X-Google-Smtp-Source: ABdhPJxe6AIByThQqqbW8s3kDWh4+2z62zhHOEhzPgx4d+7ZbR3OFLC89oIaUMBZb5/d549GIiGugA== X-Received: by 2002:a63:b24b:0:b0:398:9894:b8be with SMTP id t11-20020a63b24b000000b003989894b8bemr26222769pgo.108.1649669777512; Mon, 11 Apr 2022 02:36:17 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.111]) by smtp.gmail.com with ESMTPSA id k10-20020a056a00168a00b004f7e2a550ccsm34034426pfc.78.2022.04.11.02.36.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 02:36:17 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Subject: [PATCH v3 11/11] KVM: x86/pmu: Drop amd_event_mapping[] in the KVM context Date: Mon, 11 Apr 2022 17:35:37 +0800 Message-Id: <20220411093537.11558-12-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411093537.11558-1-likexu@tencent.com> References: <20220411093537.11558-1-likexu@tencent.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Like Xu All gp or fixed counters have been reprogrammed using PERF_TYPE_RAW, which means that the table that maps perf_hw_id to event select values is no longer useful, at least for AMD. For Intel, the logic to check if the pmu event reported by Intel cpuid is not available is still required, in which case pmc_perf_hw_id() could be renamed to hw_event_is_unavail() and a bool value is returned to replace the semantics of "PERF_COUNT_HW_MAX+1". Signed-off-by: Like Xu --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 2 +- arch/x86/kvm/pmu.c | 6 ++--- arch/x86/kvm/pmu.h | 2 +- arch/x86/kvm/svm/pmu.c | 34 +++----------------------- arch/x86/kvm/vmx/pmu_intel.c | 11 +++------ 5 files changed, 12 insertions(+), 43 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/= kvm-x86-pmu-ops.h index fdfd8e06fee6..227317bafb22 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -12,7 +12,7 @@ BUILD_BUG_ON(1) * a NULL definition, for example if "static_call_cond()" will be used * at the call sites. */ -KVM_X86_PMU_OP(pmc_perf_hw_id) +KVM_X86_PMU_OP(hw_event_is_unavail) KVM_X86_PMU_OP(pmc_is_enabled) KVM_X86_PMU_OP(pmc_idx_to_pmc) KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index f6fd85942a6b..03100e4a5cfb 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -139,9 +139,6 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, = u32 type, .config =3D config, }; =20 - if (type =3D=3D PERF_TYPE_HARDWARE && config >=3D PERF_COUNT_HW_MAX) - return; - attr.sample_period =3D get_sample_period(pmc, pmc->counter); =20 if ((attr.config & HSW_IN_TX_CHECKPOINTED) && @@ -213,6 +210,9 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) __u64 key; int idx, srcu_idx; =20 + if (static_call(kvm_x86_pmu_hw_event_is_unavail)(pmc)) + return false; + srcu_idx =3D srcu_read_lock(&kvm->srcu); filter =3D srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu); if (!filter) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index f4a799816c51..c3c2ac8f79ca 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -22,7 +22,7 @@ struct kvm_event_hw_type_mapping { }; =20 struct kvm_pmu_ops { - unsigned int (*pmc_perf_hw_id)(struct kvm_pmc *pmc); + bool (*hw_event_is_unavail)(struct kvm_pmc *pmc); bool (*pmc_is_enabled)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index ebec2b478ac1..0c9f2e4b7b6b 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -33,18 +33,6 @@ enum index { INDEX_ERROR, }; =20 -/* duplicated from amd_perfmon_event_map, K7 and above should work. */ -static struct kvm_event_hw_type_mapping amd_event_mapping[] =3D { - [0] =3D { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES }, - [1] =3D { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS }, - [2] =3D { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES }, - [3] =3D { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES }, - [4] =3D { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS }, - [5] =3D { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES }, - [6] =3D { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND }, - [7] =3D { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND }, -}; - static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type) { struct kvm_vcpu *vcpu =3D pmu_to_vcpu(pmu); @@ -138,25 +126,9 @@ static inline struct kvm_pmc *get_gp_pmc_amd(struct kv= m_pmu *pmu, u32 msr, return &pmu->gp_counters[msr_to_index(msr)]; } =20 -static unsigned int amd_pmc_perf_hw_id(struct kvm_pmc *pmc) +static bool amd_hw_event_is_unavail(struct kvm_pmc *pmc) { - u8 event_select =3D pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; - u8 unit_mask =3D (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; - int i; - - /* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */ - if (WARN_ON(pmc_is_fixed(pmc))) - return PERF_COUNT_HW_MAX; - - for (i =3D 0; i < ARRAY_SIZE(amd_event_mapping); i++) - if (amd_event_mapping[i].eventsel =3D=3D event_select - && amd_event_mapping[i].unit_mask =3D=3D unit_mask) - break; - - if (i =3D=3D ARRAY_SIZE(amd_event_mapping)) - return PERF_COUNT_HW_MAX; - - return amd_event_mapping[i].event_type; + return false; } =20 /* check if a PMC is enabled by comparing it against global_ctrl bits. Bec= ause @@ -322,7 +294,7 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) } =20 struct kvm_pmu_ops amd_pmu_ops __initdata =3D { - .pmc_perf_hw_id =3D amd_pmc_perf_hw_id, + .hw_event_is_unavail =3D amd_hw_event_is_unavail, .pmc_is_enabled =3D amd_pmc_is_enabled, .pmc_idx_to_pmc =3D amd_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc =3D amd_rdpmc_ecx_to_pmc, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 11eb186929bc..f74816d8f9f1 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -84,7 +84,7 @@ static void global_ctrl_changed(struct kvm_pmu *pmu, u64 = data) } } =20 -static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc) +static bool intel_hw_event_is_unavail(struct kvm_pmc *pmc) { struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); u8 event_select =3D pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; @@ -98,15 +98,12 @@ static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc= *pmc) =20 /* disable event that reported as not present by cpuid */ if ((i < 7) && !(pmu->available_event_types & (1 << i))) - return PERF_COUNT_HW_MAX + 1; + return true; =20 break; } =20 - if (i =3D=3D ARRAY_SIZE(intel_arch_events)) - return PERF_COUNT_HW_MAX; - - return intel_arch_events[i].event_type; + return false; } =20 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */ @@ -730,7 +727,7 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu) } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { - .pmc_perf_hw_id =3D intel_pmc_perf_hw_id, + .hw_event_is_unavail =3D intel_hw_event_is_unavail, .pmc_is_enabled =3D intel_pmc_is_enabled, .pmc_idx_to_pmc =3D intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc =3D intel_rdpmc_ecx_to_pmc, --=20 2.35.1