From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 598DEC433FE for ; Mon, 11 Apr 2022 09:10:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344214AbiDKJNB (ORCPT ); Mon, 11 Apr 2022 05:13:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344185AbiDKJMy (ORCPT ); Mon, 11 Apr 2022 05:12:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B630BC5 for ; Mon, 11 Apr 2022 02:10:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668241; x=1681204241; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=idY7s0WCRZPb+aPMzGwgPQXPNOVLICQyDJA9JTrEoe0=; b=Gsax/w1Sq5qeU6m8T5O5AfLmzYbtrsoVDF++gEFkuqqQ3FnMZ5G9tXh5 vfIzLuJdinJTEYwRv32pORyeX5suZYoTCt6xusULpOjp/8mz2+w95ajQy BrlrJQ2lvBRVk55rKuN3D/u+sHJf+jGqfx8LamunVBglz4gnoKFY0rWf4 dj6GQl0zNfosh6ygAjjsWoJ1RX4V3x1CXH9h3P+QKZzjQ6w789ADPvHLE DVI9beX5jcwBaPiXmmTlTYrQVKRg/FY+wcvMabOGOf+gbZfAIdvVsiRnS xW/10ZNyEOoqjqGcwdWMbHGR48NcX6IxZ5TWJ9A6vKWjMn2r4bR+3qNYw A==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="160048708" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:10:41 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:40 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:38 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 1/9] mtd: spi-nor: Rename method, s/spi_nor_match_id/spi_nor_match_name Date: Mon, 11 Apr 2022 12:10:25 +0300 Message-ID: <20220411091033.98754-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The method is matching a flash_info entry by searching by name. Rename the method for better clarity. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: collect R-bs drivers/mtd/spi-nor/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b4f141ad9c9c..214d3a1ac6b0 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2876,8 +2876,8 @@ void spi_nor_restore(struct spi_nor *nor) } EXPORT_SYMBOL_GPL(spi_nor_restore); =20 -static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, - const char *name) +static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, + const char *name) { unsigned int i, j; =20 @@ -2899,7 +2899,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, const struct flash_info *info =3D NULL; =20 if (name) - info =3D spi_nor_match_id(nor, name); + info =3D spi_nor_match_name(nor, name); /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) info =3D spi_nor_read_id(nor); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18CFEC433F5 for ; Mon, 11 Apr 2022 09:10:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344222AbiDKJND (ORCPT ); Mon, 11 Apr 2022 05:13:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344192AbiDKJM5 (ORCPT ); Mon, 11 Apr 2022 05:12:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D0C7286D5 for ; Mon, 11 Apr 2022 02:10:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668244; x=1681204244; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l502uYE2TnP3MLFemsdwebdVBuL3o2Hjtc5LM+PWKJg=; b=Zdy2j/5JQ2K6xwL/TNIH7cAZnFDq25e6G9Ijqs2X8qwLStRyOOU+HERW 24zSeltiJENJtCSoPJAkQiGvG0Y62iopi/eG6M/03RqN8QE/2/P+wEHBQ irYens3gd9CUZiOEOI+9Uv1cdwmVQp8gr7/3iNVDlik1KDt5IBpFZ8O7p 93w3O7yBK6rFZGX0nEOo4JOm1Q3AXYIS1zFproZ5NtSBB/irdEsExDv9j DlrWNsBuSgmFEH9jhoJW7cvZfj6uzgxirdLrItwL9SGIQ8X2T4RYo3E5V FtFvfCj0FwhLcy09c95KPI+ZKBW/nDahP+P01K2hGMgMMa2//nqnnUIxe g==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="159624234" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:10:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:43 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:41 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 2/9] mtd: spi-nor: Introduce spi_nor_match_id() Date: Mon, 11 Apr 2022 12:10:26 +0300 Message-ID: <20220411091033.98754-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Similar to spi_nor_match_name() extend the search of flash_info through all the manufacturers, this time doing the match by ID. There's no reason to limit the search per manufacturer yet, do it globally, search the flash in all the parts of all manufacturers in a single method. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: collect R-bs drivers/mtd/spi-nor/core.c | 40 ++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 214d3a1ac6b0..b9cc8bbf1f62 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1629,16 +1629,21 @@ static const struct spi_nor_manufacturer *manufactu= rers[] =3D { &spi_nor_xmc, }; =20 -static const struct flash_info * -spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int npa= rts, - const u8 *id) +static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, + const u8 *id) { - unsigned int i; + const struct flash_info *part; + unsigned int i, j; =20 - for (i =3D 0; i < nparts; i++) { - if (parts[i].id_len && - !memcmp(parts[i].id, id, parts[i].id_len)) - return &parts[i]; + for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { + for (j =3D 0; j < manufacturers[i]->nparts; j++) { + part =3D &manufacturers[i]->parts[j]; + if (part->id_len && + !memcmp(part->id, id, part->id_len)) { + nor->manufacturer =3D manufacturers[i]; + return part; + } + } } =20 return NULL; @@ -1648,7 +1653,6 @@ static const struct flash_info *spi_nor_read_id(struc= t spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; - unsigned int i; int ret; =20 if (nor->spimem) { @@ -1668,19 +1672,13 @@ static const struct flash_info *spi_nor_read_id(str= uct spi_nor *nor) return ERR_PTR(ret); } =20 - for (i =3D 0; i < ARRAY_SIZE(manufacturers); i++) { - info =3D spi_nor_search_part_by_id(manufacturers[i]->parts, - manufacturers[i]->nparts, - id); - if (info) { - nor->manufacturer =3D manufacturers[i]; - return info; - } + info =3D spi_nor_match_id(nor, id); + if (!info) { + dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", + SPI_NOR_MAX_ID_LEN, id); + return ERR_PTR(-ENODEV); } - - dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", - SPI_NOR_MAX_ID_LEN, id); - return ERR_PTR(-ENODEV); + return info; } =20 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7823C433EF for ; Mon, 11 Apr 2022 09:10:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344192AbiDKJNJ (ORCPT ); Mon, 11 Apr 2022 05:13:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344205AbiDKJM7 (ORCPT ); Mon, 11 Apr 2022 05:12:59 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C689B19014 for ; Mon, 11 Apr 2022 02:10:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668247; x=1681204247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AkkbZWjZRlH9312vjiduNujt5vMVxf/XLruKiXMySs0=; b=e0mLrdJ2gjKNFgIaAp1W6Rj6NISj/Sv70zJPjcSosC8db/AQp1cMCXut e2Ei2geyqm7VoO7lqKaBooTzwiHRLHeBfzKAJtfdpy48AX3kKl7IpWSkQ ffLfa/J2uPbxLXfOtx9RqFGwZhY9zAxM7P1yjRvHEGhcKe0I93pw1BqEo H+EjSSI7xcfzxkX3Mq+e9B+L4m5DCw8bh/1qN0f6Ev9QY67rrcbAWCG+t BZDMw3oKcYpvksasKPo2ROUEKrLQoCdG+3IE4Hu2Y0IHqCGQGO0DhDw+n 4X5NNNKqsaitLzFsS5iRmfTrRTz782/1WmSTq6rTxj7lFaX34gnVFdUiV A==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="159624238" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:10:47 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:46 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:43 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 3/9] mtd: spi-nor: core: Use auto-detection only once Date: Mon, 11 Apr 2022 12:10:27 +0300 Message-ID: <20220411091033.98754-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In case spi_nor_match_name() returned NULL, the auto detection was issued twice. There's no reason to try to detect the same chip twice, do the auto detection only once. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- v3: = =20 - caller of spi_nor_get_flash_info now handles NULL and translates it to = =20 ENOENT. drivers/mtd/spi-nor/core.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b9cc8bbf1f62..b55d922d46dd 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2896,13 +2896,14 @@ static const struct flash_info *spi_nor_get_flash_i= nfo(struct spi_nor *nor, { const struct flash_info *info =3D NULL; =20 - if (name) + if (name) { info =3D spi_nor_match_name(nor, name); + if (IS_ERR(info)) + return info; + } /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) - info =3D spi_nor_read_id(nor); - if (IS_ERR_OR_NULL(info)) - return ERR_PTR(-ENOENT); + return spi_nor_read_id(nor); =20 /* * If caller has specified name of flash model that can normally be @@ -2994,7 +2995,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, return -ENOMEM; =20 info =3D spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) + if (!info) + return -ENOENT; + else if (IS_ERR(info)) return PTR_ERR(info); =20 nor->info =3D info; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B4B4C433F5 for ; Mon, 11 Apr 2022 09:11:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344243AbiDKJNN (ORCPT ); Mon, 11 Apr 2022 05:13:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344225AbiDKJNE (ORCPT ); Mon, 11 Apr 2022 05:13:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADA633F890 for ; Mon, 11 Apr 2022 02:10:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668249; x=1681204249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FaSy9U5U+AEHbmgDOBzFDdOgKxxIaWmtEqSMPmVYvZk=; b=xyn464mc37Op8CDRZLAObfestFp92U18wwVb91QDGWmYUw5k8oiLypID 28aQJpWDcjcccwPtc/gK3R2CQ1Ek4rYf/lx5xSLTct/P4sxPggdk3bwTU +FE97jrpmzCh4qheUvOPmDrEcJ4paN4C0nxCqMq6zDAkBNF0HpUPdICGY AF9q3uI1Prd8VvBie/sjnVdnrUhV5yWGBv+QoMJz+XyQVLrBsKqy7AWSh bsnRuA7WVEJF7jS59WIUPUKCLJV1IytF4EN0dCnfuSQ4sNBaiC9rBATO2 SUJf95ZeqArUWYP5FxMGoHCZEY39WtORiYD0cAP+b+uOwtReujXTe6QZa Q==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="160048736" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:10:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:48 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:46 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 4/9] mtd: spi-nor: core: Introduce method for RDID op Date: Mon, 11 Apr 2022 12:10:28 +0300 Message-ID: <20220411091033.98754-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RDID is used in the core to auto detect the flash, but also by some manufacturer drivers that contain flashes that support Octal DTR mode, so that they can read the flash ID after the switch to Octal DTR was made to test if the switch was successful. Introduce a core method for RDID op to avoid code duplication. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- v3: s/reg_proto/proto drivers/mtd/spi-nor/core.c | 50 ++++++++++++++++++++++++++------------ drivers/mtd/spi-nor/core.h | 9 +++++++ 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index b55d922d46dd..6165dc7bfd17 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -369,6 +369,37 @@ int spi_nor_write_disable(struct spi_nor *nor) return ret; } =20 +/** + * spi_nor_read_id() - Read the JEDEC ID. + * @nor: pointer to 'struct spi_nor'. + * @naddr: number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @ndummy: number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @id: pointer to a DMA-able buffer where the value of the JEDEC ID + * will be written. + * @proto: the SPI protocol for register operation. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol proto) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN); + + spi_nor_spimem_setup_op(nor, &op, proto); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, + SPI_NOR_MAX_ID_LEN); + } + return ret; +} + /** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. @@ -1649,24 +1680,13 @@ static const struct flash_info *spi_nor_match_id(st= ruct spi_nor *nor, return NULL; } =20 -static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) +static const struct flash_info *spi_nor_detect(struct spi_nor *nor) { const struct flash_info *info; u8 *id =3D nor->bouncebuf; int ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, - SPI_NOR_MAX_ID_LEN); - } + ret =3D spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); if (ret) { dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); return ERR_PTR(ret); @@ -2903,7 +2923,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, } /* Try to auto-detect if chip name wasn't specified or not found */ if (!info) - return spi_nor_read_id(nor); + return spi_nor_detect(nor); =20 /* * If caller has specified name of flash model that can normally be @@ -2912,7 +2932,7 @@ static const struct flash_info *spi_nor_get_flash_inf= o(struct spi_nor *nor, if (name && info->id_len) { const struct flash_info *jinfo; =20 - jinfo =3D spi_nor_read_id(nor); + jinfo =3D spi_nor_detect(nor); if (IS_ERR(jinfo)) { return jinfo; } else if (jinfo !=3D info) { diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b7fd760e3b47..f952061d5c24 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -11,6 +11,13 @@ =20 #define SPI_NOR_MAX_ID_LEN 6 =20 +/* Standard SPI NOR flash operations. */ +#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ + SPI_MEM_OP_ADDR(naddr, 0, 0), \ + SPI_MEM_OP_DUMMY(ndummy, 0), \ + SPI_MEM_OP_DATA_IN(len, buf, 0)) + enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(0), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), @@ -534,6 +541,8 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); int spi_nor_sr_ready(struct spi_nor *nor); int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5728AC433F5 for ; Mon, 11 Apr 2022 09:11:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344254AbiDKJNQ (ORCPT ); Mon, 11 Apr 2022 05:13:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344232AbiDKJNF (ORCPT ); Mon, 11 Apr 2022 05:13:05 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47DC73F8A5 for ; Mon, 11 Apr 2022 02:10:52 -0700 (PDT) DKIM-Signature: v=1; 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Mon, 11 Apr 2022 02:10:51 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:49 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 5/9] mtd: spi-nor: manufacturers: Use spi_nor_read_id() core method Date: Mon, 11 Apr 2022 12:10:29 +0300 Message-ID: <20220411091033.98754-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use spi_nor_read_id() core method to avoid duplication of code. Now the ID is read on the full SPI_NOR_MAX_ID_LEN instead of round_up(nor->info->id_len, 2), but it doesn't harm to read more ID bytes, so the change comes with no secondary effects. dev_dbg messages in case spi_nor_read_id() fails, will be added in a further patch after we split the octal DTR enable/disable methods. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: collect R-b, update commit message drivers/mtd/spi-nor/micron-st.c | 13 +++---------- drivers/mtd/spi-nor/spansion.c | 13 +++---------- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 8a20475ce77a..41b87868ecf9 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -91,17 +91,10 @@ static int micron_st_nor_octal_dtr_enable(struct spi_no= r *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_DUMMY(enable ? 8 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index f24e546e04a5..c5988312cc91 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -98,17 +98,10 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor = *nor, bool enable) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), - SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1), - SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1), - SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), - buf, 1)); - if (enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); - - ret =3D spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + else + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); if (ret) return ret; =20 --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCEA0C433EF for ; Mon, 11 Apr 2022 09:11:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344262AbiDKJNS (ORCPT ); Mon, 11 Apr 2022 05:13:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344237AbiDKJNJ (ORCPT ); Mon, 11 Apr 2022 05:13:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FB4F3F890 for ; Mon, 11 Apr 2022 02:10:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668255; x=1681204255; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h2crEZi5xB2G5eqgtuWh6WJpu41rEMS1+taspgX96r0=; b=HlEwBigJgj188snbpEabBOzPOU1B8kfrFkg5JWbiITUK/ZvtZbBnXdWh Uzw//9363b3KUqfnj4XwliZ+WEp9t06AdO//U9akicmrlL/h6UvjyOGdE abNFDLRIcPf3UVa64O74vqvGUVut73/SPDa67TbCkUrEOXjz/Urrq+HaW yQnmLs2qazM3GQppeV2KYkaGu720oR7VskShMIm1a4TNFzwXdU3/1TV4A 5ca5Qz9VTpIIoxuFkOtpRQSGMykIjbgQfG7OP2CuZw8TXEBhKEa3IOEGH WgH/mW/EmAXmB4YV+HavDJPnPX/04E+Esu4rCWTTgaKHpBc1S5EJpeFnN A==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="91957972" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:10:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:54 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:51 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus , Takahiro Kuwano Subject: [PATCH v3 6/9] mtd: spi-nor: core: Add helpers to read/write any register Date: Mon, 11 Apr 2022 12:10:30 +0300 Message-ID: <20220411091033.98754-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are manufacturers that use registers indexed by address. Some of them support "read/write any register" opcodes. Provide core methods that can be used by all manufacturers. SPI NOR controller ops are intentionally not supported as we intend to move all the SPI NOR controller drivers under the SPI subsystem. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: no changes drivers/mtd/spi-nor/core.c | 41 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 4 ++++ 2 files changed, 45 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 6165dc7bfd17..42794328d3b6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -307,6 +307,47 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t= to, size_t len, return nor->controller_ops->write(nor, to, len, buf); } =20 +/** + * spi_nor_read_reg() - read register to flash memory + * @nor: pointer to 'struct spi_nor'. + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + if (!nor->spimem) + return -EOPNOTSUPP; + + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + +/** + * spi_nor_write_reg() - write register to flash memory + * @nor: pointer to 'struct spi_nor' + * @op: SPI memory operation. op->data.buf must be DMA-able. + * @proto: SPI protocol to use for the register operation. + * + * Return: zero on success, -errno otherwise + */ +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto) +{ + int ret; + + if (!nor->spimem) + return -EOPNOTSUPP; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + spi_nor_spimem_setup_op(nor, op, proto); + return spi_nor_spimem_exec_op(nor, op); +} + /** * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f952061d5c24..7c704475946d 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -554,6 +554,10 @@ ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t = from, size_t len, u8 *buf); ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf); +int spi_nor_read_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); +int spi_nor_write_reg(struct spi_nor *nor, struct spi_mem_op *op, + enum spi_nor_protocol proto); int spi_nor_erase_sector(struct spi_nor *nor, u32 addr); =20 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8= *buf); --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D684C433EF for ; Mon, 11 Apr 2022 09:11:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344242AbiDKJNU (ORCPT ); Mon, 11 Apr 2022 05:13:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239256AbiDKJNL (ORCPT ); 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11 Apr 2022 02:10:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:57 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:54 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 7/9] mtd: spi-nor: micron-st: Rework spi_nor_micron_octal_dtr_enable() Date: Mon, 11 Apr 2022 12:10:31 +0300 Message-ID: <20220411091033.98754-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_micron_octal_dtr_enable() in spi_nor_micron_octal_dtr_en() and spi_nor_micron_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to follow. Add dev_dbg messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: collect R-b, update commit message, add dev_dbg message in case = =20 spi_nor_read_id() fails. drivers/mtd/spi-nor/micron-st.c | 111 +++++++++++++++++--------------- 1 file changed, 60 insertions(+), 51 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 41b87868ecf9..a447762c0d78 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -28,75 +28,78 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ =20 -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Micron ST SPI NOR flash operations. */ +#define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 20 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - *buf =3D 20; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_MT_CFR1V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; - - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - } + /* Use 20 dummy cycles for memory array reads. */ + *buf =3D 20; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_write_enable(nor); + buf[0] =3D SPINOR_MT_OCT_DTR; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR0V, 1, buf); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_MT_OCT_DTR; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. The next register is the dummy - * cycle configuration register. Since the transaction needs to - * be at least 2 bytes wide, set the next register to its - * default value. This also makes sense because the value was - * changed when enabling 8D-8D-8D mode, it should be reset when - * disabling. - */ - buf[0] =3D SPINOR_MT_EXSPI; - buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mod= e\n", ret); + return ret; } =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_MT_CFR0V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + return 0; +} + +static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. The next register is the dummy cycle configuration + * register. Since the transaction needs to be at least 2 bytes wide, + * set the next register to its default value. This also makes sense + * because the value was changed when enabling 8D-8D-8D mode, it should + * be reset when disabling. + */ + buf[0] =3D SPINOR_MT_EXSPI; + buf[1] =3D SPINOR_REG_MT_CFR1V_DEF; + op =3D (struct spi_mem_op) + MICRON_ST_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); - if (ret) + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mo= de\n", ret); return ret; + } =20 if (memcmp(buf, nor->info->id, nor->info->id_len)) return -EINVAL; @@ -104,6 +107,12 @@ static int micron_st_nor_octal_dtr_enable(struct spi_n= or *nor, bool enable) return 0; } =20 +static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? micron_st_nor_octal_dtr_en(nor) : + micron_st_nor_octal_dtr_dis(nor); +} + static void mt35xu512aba_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D micron_st_nor_octal_dtr_enable; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C37AC433EF for ; Mon, 11 Apr 2022 09:11:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344255AbiDKJN0 (ORCPT ); Mon, 11 Apr 2022 05:13:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344205AbiDKJNO (ORCPT ); Mon, 11 Apr 2022 05:13:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0D7E3F8AA for ; Mon, 11 Apr 2022 02:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668261; x=1681204261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QkgPbCam6M63CpqRU4By/vkwHVtyHHOvsN4BRk3QFJY=; b=CTJpqAjhrt3wex1ahM8xussBc7MmGxgEwyPZ3PEWN+E64pXKE5AN41t8 i1hiX8upX9UZzSIXV9jQwlOfbiYyK/V26K9VXOb+hu5lkjbzoIWPqt0Mr Ehx+VG8vIbu3ChzGvzAvzQMDYmtV2wTjYqLx8WEYVzKs/Ka4oZ6+z2VrB T6RW/GAYzaDQLdswzho80PQuMK+f/hZDFMX8FB83Cptl95eXdyw1cV3ps MRHUVwMKTPCBl+WPvole9I/M9qxBbYDCzTUCA1V2KlgJN38IhS7vle60A s1KpQ3gsbXLWaNAqMlSGgUJh9O7fo/HsCeTvVRvgvsW6aP7Sbh5aEjSI9 Q==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="152208190" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:11:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:10:59 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:10:57 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 8/9] mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable() Date: Mon, 11 Apr 2022 12:10:32 +0300 Message-ID: <20220411091033.98754-9-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Add debug messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav Reviewed-by: Michael Walle --- v3: collect R-b, update commit message, add dev_dbg message in case = =20 spi_nor_read_id() fails. drivers/mtd/spi-nor/spansion.c | 128 ++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 59 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index c5988312cc91..35d8edb515a3 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -23,87 +23,81 @@ #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 #define SPINOR_OP_CYPRESS_RD_FAST 0xee =20 -/** - * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. - * @nor: pointer to a 'struct spi_nor' - * @enable: whether to enable or disable Octal DTR - * - * This also sets the memory access latency cycles to 24 to allow the flas= h to - * run at up to 200MHz. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +/* Cypress SPI NOR flash operations. */ +#define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; u8 *buf =3D nor->bouncebuf; int ret; =20 - if (enable) { - /* Use 24 dummy cycles for memory array reads. */ - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; + /* Use 24 dummy cycles for memory array reads. */ + *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf); =20 - *buf =3D SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, buf, 1)); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); - if (ret) - return ret; + ret =3D spi_nor_wait_till_ready(nor); + if (ret) + return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; + nor->read_dummy =3D 24; =20 - nor->read_dummy =3D 24; - } + /* Set the octal and DTR enable bits. */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf); =20 - /* Set/unset the octal and DTR enable bits. */ - ret =3D spi_nor_write_enable(nor); + ret =3D spi_nor_write_reg(nor, &op, nor->reg_proto); if (ret) return ret; =20 - if (enable) { - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; - } else { - /* - * The register is 1-byte wide, but 1-byte transactions are not - * allowed in 8D-8D-8D mode. Since there is no register at the - * next location, just initialize the value to 0 and let the - * transaction go on. - */ - buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; - buf[1] =3D 0; + /* Read flash ID to make sure the switch was successful. */ + ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mod= e\n", ret); + return ret; } =20 - op =3D (struct spi_mem_op) - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), - SPI_MEM_OP_ADDR(enable ? 3 : 4, - SPINOR_REG_CYPRESS_CFR5V, - 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1)); + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; =20 - if (!enable) - spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + return 0; +} =20 - ret =3D spi_mem_exec_op(nor->spimem, &op); +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf =3D nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not allowed + * in 8D-8D-8D mode. Since there is no register at the next location, + * just initialize the value to 0 and let the transaction go on. + */ + buf[0] =3D SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[1] =3D 0; + op =3D (struct spi_mem_op) + CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf); + ret =3D spi_nor_write_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); if (ret) return ret; =20 /* Read flash ID to make sure the switch was successful. */ - if (enable) - ret =3D spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR); - else - ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); - if (ret) + ret =3D spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mo= de\n", ret); return ret; + } =20 if (memcmp(buf, nor->info->id, nor->info->id_len)) return -EINVAL; @@ -111,6 +105,22 @@ static int cypress_nor_octal_dtr_enable(struct spi_nor= *nor, bool enable) return 0; } =20 +/** + * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal DTR + * + * This also sets the memory access latency cycles to 24 to allow the flas= h to + * run at up to 200MHz. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + return enable ? cypress_nor_octal_dtr_en(nor) : + cypress_nor_octal_dtr_dis(nor); +} + static void s28hs512t_default_init(struct spi_nor *nor) { nor->params->octal_dtr_enable =3D cypress_nor_octal_dtr_enable; --=20 2.25.1 From nobody Mon May 11 07:46:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ADE5C433EF for ; Mon, 11 Apr 2022 09:11:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344283AbiDKJNm (ORCPT ); Mon, 11 Apr 2022 05:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344278AbiDKJNX (ORCPT ); Mon, 11 Apr 2022 05:13:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DD223FBCA for ; Mon, 11 Apr 2022 02:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649668265; x=1681204265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=odzJXBAfND22zDvU+RyvVJ3pirtZMgtb8UMnZjarqeo=; b=YFqbuRGW1in23lNl471S4yrR9RWXax5g6iu1R9pcX9/klwK0OG/54ECF eelLK3jldEMSiHPX2KIfY9RpS1eTTuiavhhyDrgCa4FbiHail0NahT8JI lrp15vNxFGmWlaMOEe4xyfCR+4NTuUKEEiuoXIqT5nj6/NMgaubSwKvF5 VoZf8t1dSONO68pvMRmkQAM4ocbvk07iaq/CIJTtP5pjr4iScQj3oHW+5 PIikb87zMlQ7xKbQnWIu+IsDudzS64Oe+hHLLf7JI+CkcIoAqz3RDn2wG NAe9pQiKaIDQgADj74hwJpXKOaYm+wVd5+JzUQ/RaoH1J7b/9uwcpCdSi w==; X-IronPort-AV: E=Sophos;i="5.90,251,1643698800"; d="scan'208";a="160048763" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Apr 2022 02:11:03 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 11 Apr 2022 02:11:02 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 11 Apr 2022 02:11:00 -0700 From: Tudor Ambarus To: , CC: , , , , , , Tudor Ambarus Subject: [PATCH v3 9/9] mtd: spi-nor: Introduce templates for SPI NOR operations Date: Mon, 11 Apr 2022 12:10:33 +0300 Message-ID: <20220411091033.98754-10-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220411091033.98754-1-tudor.ambarus@microchip.com> References: <20220411091033.98754-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clean the op declaration and hide the details of each op. With this it results a cleanner, easier to read code. No functional change expected. Signed-off-by: Tudor Ambarus Acked-by: Michael Walle Acked-by: Pratyush Yadav --- v3: new patch taken from, no changes https://lore.kernel.org/lkml/20220304093011.198173-1-tudor.ambarus@microchi= p.com/ drivers/mtd/spi-nor/core.c | 101 ++++++------------------------- drivers/mtd/spi-nor/core.h | 102 ++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/micron-st.c | 24 ++++---- drivers/mtd/spi-nor/spansion.c | 26 +++++--- drivers/mtd/spi-nor/xilinx.c | 12 ++-- 5 files changed, 158 insertions(+), 107 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 42794328d3b6..fe853532204c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -359,11 +359,7 @@ int spi_nor_write_enable(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_WREN_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -390,11 +386,7 @@ int spi_nor_write_disable(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_WRDI_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -454,11 +446,7 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr, 0)); + struct spi_mem_op op =3D SPI_NOR_RDSR_OP(sr); =20 if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; @@ -498,11 +486,7 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, cr, 0)); + struct spi_mem_op op =3D SPI_NOR_RDCR_OP(cr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -531,14 +515,7 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, b= ool enable) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? - SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_EN4B_EX4B_OP(enable); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -572,11 +549,7 @@ static int spansion_set_4byte_addr_mode(struct spi_nor= *nor, bool enable) nor->bouncebuf[0] =3D enable << 7; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); + struct spi_mem_op op =3D SPI_NOR_BRWR_OP(nor->bouncebuf); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -606,11 +579,7 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear) nor->bouncebuf[0] =3D ear; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); + struct spi_mem_op op =3D SPI_NOR_WREAR_OP(nor->bouncebuf); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -721,11 +690,7 @@ int spi_nor_global_block_unlock(struct spi_nor *nor) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_GBULK_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -760,11 +725,7 @@ int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr= , size_t len) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(len, sr, 0)); + struct spi_mem_op op =3D SPI_NOR_WRSR_OP(sr, len); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -964,11 +925,7 @@ static int spi_nor_write_sr2(struct spi_nor *nor, cons= t u8 *sr2) return ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, sr2, 0)); + struct spi_mem_op op =3D SPI_NOR_WRSR2_OP(sr2); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -1000,11 +957,7 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *= sr2) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr2, 0)); + struct spi_mem_op op =3D SPI_NOR_RDSR2_OP(sr2); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -1033,11 +986,7 @@ static int spi_nor_erase_chip(struct spi_nor *nor) dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPI_NOR_CHIP_ERASE_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); =20 @@ -1179,10 +1128,8 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 ad= dr) =20 if (nor->spimem) { struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), - SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, + nor->addr_width, addr); =20 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); =20 @@ -1978,10 +1925,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *n= or, static int spi_nor_spimem_check_readop(struct spi_nor *nor, const struct spi_nor_read_command *read) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), - SPI_MEM_OP_ADDR(3, 0, 0), - SPI_MEM_OP_DUMMY(1, 0), - SPI_MEM_OP_DATA_IN(2, NULL, 0)); + struct spi_mem_op op =3D SPI_NOR_READ_OP(read->opcode); =20 spi_nor_spimem_setup_op(nor, &op, read->proto); =20 @@ -2004,10 +1948,7 @@ static int spi_nor_spimem_check_readop(struct spi_no= r *nor, static int spi_nor_spimem_check_pp(struct spi_nor *nor, const struct spi_nor_pp_command *pp) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), - SPI_MEM_OP_ADDR(3, 0, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(2, NULL, 0)); + struct spi_mem_op op =3D SPI_NOR_PP_OP(pp->opcode); =20 spi_nor_spimem_setup_op(nor, &op, pp->proto); =20 @@ -2831,10 +2772,7 @@ static void spi_nor_soft_reset(struct spi_nor *nor) struct spi_mem_op op; int ret; =20 - op =3D (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DATA); + op =3D (struct spi_mem_op)SPINOR_SRSTEN_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 @@ -2844,10 +2782,7 @@ static void spi_nor_soft_reset(struct spi_nor *nor) return; } =20 - op =3D (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DATA); + op =3D (struct spi_mem_op)SPINOR_SRST_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7c704475946d..8b7e597fd38c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -18,6 +18,108 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(len, buf, 0)) =20 +#define SPI_NOR_WREN_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_WRDI_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_RDSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPI_NOR_WRSR_OP(buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(len, buf, 0)) + +#define SPI_NOR_RDSR2_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_WRSR2_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_RDCR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPI_NOR_EN4B_EX4B_OP(enable) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_BRWR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_WREAR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 0)) + +#define SPI_NOR_GBULK_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_CHIP_ERASE_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_width, addr) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(addr_width, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPI_NOR_READ_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(3, 0, 0), \ + SPI_MEM_OP_DUMMY(1, 0), \ + SPI_MEM_OP_DATA_IN(2, NULL, 0)) + +#define SPI_NOR_PP_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(3, 0, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(2, NULL, 0)) + +#define SPINOR_SRSTEN_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DATA) + +#define SPINOR_SRST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DATA) + enum spi_nor_option_flags { SNOR_F_HAS_SR_TB =3D BIT(0), SNOR_F_NO_OP_CHIP_ERASE =3D BIT(1), diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index a447762c0d78..26b9a1c2309d 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -35,6 +35,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) =20 +#define MICRON_ST_RDFSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define MICRON_ST_CLFSR_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; @@ -324,11 +336,7 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor,= u8 *fsr) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, fsr, 0)); + struct spi_mem_op op =3D MICRON_ST_RDFSR_OP(fsr); =20 if (nor->reg_proto =3D=3D SNOR_PROTO_8_8_8_DTR) { op.addr.nbytes =3D nor->params->rdsr_addr_nbytes; @@ -363,11 +371,7 @@ static void micron_st_nor_clear_fsr(struct spi_nor *no= r) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D MICRON_ST_CLFSR_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 35d8edb515a3..952db7af6932 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -30,6 +30,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) =20 +#define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + +#define SPANSION_CLSR_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { struct spi_mem_op op; @@ -165,12 +177,12 @@ static int s28hs512t_post_bfpt_fixup(struct spi_nor *= nor, * CFR3V[4] and set the correct size. */ struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), - SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V, + nor->bouncebuf); int ret; =20 + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + ret =3D spi_mem_exec_op(nor->spimem, &op); if (ret) return ret; @@ -320,11 +332,7 @@ static void spansion_nor_clear_sr(struct spi_nor *nor) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); + struct spi_mem_op op =3D SPANSION_CLSR_OP; =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 9459ac2609dc..1d2f5db047bd 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -15,6 +15,12 @@ #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ #define XSR_RDY BIT(7) /* Ready */ =20 +#define XILINX_RDSR_OP(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_IN(1, buf, 0)) + #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ .id =3D { \ ((_jedec_id) >> 16) & 0xff, \ @@ -72,11 +78,7 @@ static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *s= r) int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr, 0)); + struct spi_mem_op op =3D XILINX_RDSR_OP(sr); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 --=20 2.25.1