From nobody Mon May 11 09:54:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0286AC433F5 for ; Sat, 9 Apr 2022 21:11:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232003AbiDIVNx (ORCPT ); Sat, 9 Apr 2022 17:13:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231931AbiDIVNu (ORCPT ); Sat, 9 Apr 2022 17:13:50 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B79AB7664B for ; Sat, 9 Apr 2022 14:11:37 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id a16-20020a17090a6d9000b001c7d6c1bb13so12930529pjk.4 for ; Sat, 09 Apr 2022 14:11:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y7L2Rl1Azs1qdyPqBYsqG+p3Elwf/l1kjj+FLiYmbT0=; b=DSlovrPyKrzRMXH6RmU9rxtzpuENFrLHzZOcjwuGHTEYFCWIVPC6xpiAY44LMxxp/m a47mFuEjBqpIgr6wdSujSp6VXedgqKs7meLk31oA4WXJTV+Q9RJ61nFW37J1TbhA6wFp FGOD99F1zvudg/Sj5XVOdG3DcdPWqYgX6F8juZ4bkJhZrHQ83dRcCrm2T2AYuA3/Epyd nonGKxiEVzFJ5/TWnAR9ipkkESC2vfX8P0lY0OgU2nkKbUdCdS2HPDvlrgL6I4ziVtl4 uJMvko0Sw9L6vopyQtfKtt4PIpCIBmDZ0AQM4W3/SECmghK/UtmGSkjtquvC3y66VXdA yn7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y7L2Rl1Azs1qdyPqBYsqG+p3Elwf/l1kjj+FLiYmbT0=; b=DrzmW8NyIloPyp80Kn16uSUJY7gk17895ZZj+co16IAF7GRU4pCUDtfFXWmYMb6Pce p1GGsfNtMheyN8K2S2g1phgNM9VG796GCeWkB8kl1QGogEj387CkC2/0RxcEq8v9PqTi u3Z2Yrtbynnk4f9tYCjm5RW6KTpN7ybQtx60jCLLVlOLBCNoaW/6OivM3jQto0mKr7RZ EY6UHAozMAN9utycTa154H6TJGpj/0D71BvS9O0d0gHAFEvTGVKSWof4U30CE/OGC5Mp r387QIjC6FBH+qaqf0shssNtFU9BU3EI+LOo5grTQJZDPfH4FogUAmTW2F3puEAylXI4 hJew== X-Gm-Message-State: AOAM532yolCKSBeEbAFMqtT0/6jwZhxOGeZ5mq1rzd1lPdvbfVcfXUPw VrDuPyBsZSSRoKHhrLWg5XDXJA== X-Google-Smtp-Source: ABdhPJw5Rq+GTknDzXhuTRZefTu+M6QpC71rPXCKCsZk3sK1J0SV/wvRnzaw7+WTiuuhP1WBn+uB5w== X-Received: by 2002:a17:902:ecd2:b0:156:9992:5892 with SMTP id a18-20020a170902ecd200b0015699925892mr25158352plh.7.1649538697093; Sat, 09 Apr 2022 14:11:37 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1001:7090:925c:1a60:e433:31b7]) by smtp.gmail.com with ESMTPSA id w127-20020a627b85000000b00505a9142ce5sm1393295pfc.22.2022.04.09.14.11.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 14:11:36 -0700 (PDT) From: Drew Fustini To: Rob Herring , Krzysztof Kozlowski , Dave Gerlach , Tony Lindgren , Nishanth Menon , Santosh Shilimkar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Drew Fustini Subject: [PATCH v2 1/2] dt-bindings: wkup-m3-ipc: Add vtt toggle gpio pin property Date: Sat, 9 Apr 2022 14:12:14 -0700 Message-Id: <20220409211215.2529387-2-dfustini@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220409211215.2529387-1-dfustini@baylibre.com> References: <20220409211215.2529387-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document Wakeup M3 IPC property that indicates a GPIO pin is connected to the enable pin on DDR VTT regulator and can be toggled during low power mode transitions. Signed-off-by: Dave Gerlach [dfustini: converted to YAML, removed unnecessary "ti,needs-vtt-toggle"] Signed-off-by: Drew Fustini Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/ti/wkup-m3-ipc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml b/Do= cumentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml index d855c01ce61c..7f4a75c5fcaa 100644 --- a/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml @@ -24,6 +24,14 @@ description: |+ A wkup_m3_ipc device node is used to represent the IPC registers within = an SoC. =20 + Support for VTT Toggle + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin = is + connected to the enable pin on the DDR VTT regulator. This allows the + regulator to be disabled upon suspend and enabled upon resume. Please no= te + that the GPIO pin must be part of the GPIO0 module as only this GPIO mod= ule + is in the wakeup power domain. + properties: compatible: enum: @@ -51,6 +59,10 @@ properties: mbox_wkupm3 child node. maxItems: 1 =20 + ti,vtt-gpio-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: GPIO pin connected to enable pin on VTT regulator + required: - compatible - reg @@ -76,6 +88,7 @@ examples: interrupts =3D <78>; ti,rproc =3D <&wkup_m3>; mboxes =3D <&mailbox &mbox_wkupm3>; + ti,vtt-gpio-pin =3D <7>; }; }; ... --=20 2.32.0 From nobody Mon May 11 09:54:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C70B2C433EF for ; Sat, 9 Apr 2022 21:11:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232063AbiDIVN5 (ORCPT ); Sat, 9 Apr 2022 17:13:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231915AbiDIVNu (ORCPT ); Sat, 9 Apr 2022 17:13:50 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C50087666B for ; Sat, 9 Apr 2022 14:11:38 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id z128so10832905pgz.2 for ; Sat, 09 Apr 2022 14:11:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pTEAPxrhT32vhayLsKotad+jG3u8S5Ei8ZeMFP9woBA=; b=ltY2ugsAE2tvX0t0fGwusuBjHrIkWhDVxPoIQrjbbexUIl57nSUefymYypdhORwPmo nZSfFMjvOOPsmKIcco+TeK250sA7lXZR+IVGR+TaOyXXxB+UowaBxZCTzi2RCxI6OaWe ds5XtscH7XQGg+JDOw7rk+iVkcH9JPzCufjk1LxnK+Tln+aJ0NFA5ORdPpQooWvmN7iG zocaFH6si8iwMwyZwDnH4fclirpOndGdkebmfYXKpE+jJzZklaHSwVgKB3+6JPooHGOl aol9/p7lu7Tiv7JC33UCFIANoWfPRPpAFTnu+TtkyI4iiyoI5yiKLTHryagRyrmQ29AG 0u6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pTEAPxrhT32vhayLsKotad+jG3u8S5Ei8ZeMFP9woBA=; b=b0ovP2GinX/N0HDCzdqsmvOF3kxFbKOLwfP65wjluqjn2QsAdhR343PokZz1Lf1qOO M9/Amvy2cRYTWJao9pj9krkxb0iGtEf8RQL+2FZ4xik5yByAU1TdtYggGAAkxjqyKOIa JA0lFjtnxidAbXOHyr9zeQRqLnFzauarK804zK4QS0vALQkrBMQwfwV5s/kQRQj/vRsT tpozHJOq07LUhUwguWuL84iOZ0QPV8Akt3rUieGnl9IQ4meBrlnMc6WM4Gi4GcMqnqdy VnIoaOEvPr2QlFVq5x0pvLyivNQK0brcJRFD26gYLwYmvvgn/Hz9tmDJnjogGtEvyje2 oJ2w== X-Gm-Message-State: AOAM530wwKkIG8F1L0lpLawj+k0Vo2mrzCU60cJh/ZmwDvn8y4b/lE2S 1cWDc688hyMnB0n+YoqoCI2krA== X-Google-Smtp-Source: ABdhPJymzHW37Rm36BtfLUtICV/UaRQVPkfm/XEMa3uQcbapqEQJGStby8/ASIO3N632qaOns6r+3w== X-Received: by 2002:a05:6a00:2405:b0:4e1:5008:adcc with SMTP id z5-20020a056a00240500b004e15008adccmr25284211pfh.35.1649538698221; Sat, 09 Apr 2022 14:11:38 -0700 (PDT) Received: from x1.hsd1.or.comcast.net ([2601:1c2:1001:7090:925c:1a60:e433:31b7]) by smtp.gmail.com with ESMTPSA id w127-20020a627b85000000b00505a9142ce5sm1393295pfc.22.2022.04.09.14.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 14:11:37 -0700 (PDT) From: Drew Fustini To: Rob Herring , Krzysztof Kozlowski , Dave Gerlach , Tony Lindgren , Nishanth Menon , Santosh Shilimkar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Drew Fustini , Keerthy Subject: [PATCH v2 2/2] soc: ti: wkup_m3_ipc: Add support for toggling VTT regulator Date: Sat, 9 Apr 2022 14:12:15 -0700 Message-Id: <20220409211215.2529387-3-dfustini@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220409211215.2529387-1-dfustini@baylibre.com> References: <20220409211215.2529387-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Dave Gerlach Some boards like the AM335x EVM-SK and AM437x GP EVM provide software control via a GPIO pin to toggle the DDR VTT regulator to reduce power consumption in low power states. The VTT regulator should be disabled after enabling self-refresh on suspend, and should be enabled before disabling self-refresh on resume. This is to allow proper self-refresh entry/exit commands to be transmitted to the memory. The "ti,vtt-gpio-pin" device tree property in the wkup_m3_ipc node specifies which GPIO pin to use. This property is communicated to the Wakeup Cortex M3 co-processor where the actual toggling of the GPIO pin happens in CM3 firmware [1]. Please note that the GPIO pin must be on the GPIO0 module as that module is in the wakeup power domain. [1] https://git.ti.com/cgit/processor-firmware/ti-amx3-cm3-pm-firmware/tree= /src/pm_services/ddr.c?h=3D08.02.00.006#n190 Signed-off-by: Dave Gerlach Signed-off-by: Keerthy [dfustini: remove the unnecessary "ti,needs-vtt-toggle" property] Signed-off-by: Drew Fustini --- drivers/soc/ti/wkup_m3_ipc.c | 26 ++++++++++++++++++++++++-- include/linux/wkup_m3_ipc.h | 1 + 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 2f03ced0f411..247a4b57a372 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -40,6 +40,13 @@ #define M3_FW_VERSION_MASK 0xffff #define M3_WAKE_SRC_MASK 0xff =20 +#define IPC_MEM_TYPE_SHIFT (0x0) +#define IPC_MEM_TYPE_MASK (0x7 << 0) +#define IPC_VTT_STAT_SHIFT (0x3) +#define IPC_VTT_STAT_MASK (0x1 << 3) +#define IPC_VTT_GPIO_PIN_SHIFT (0x4) +#define IPC_VTT_GPIO_PIN_MASK (0x3f << 4) + #define M3_STATE_UNKNOWN 0 #define M3_STATE_RESET 1 #define M3_STATE_INITED 2 @@ -215,6 +222,12 @@ static int wkup_m3_is_available(struct wkup_m3_ipc *m3= _ipc) (m3_ipc->state !=3D M3_STATE_UNKNOWN)); } =20 +static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio) +{ + m3_ipc->vtt_conf =3D (1 << IPC_VTT_STAT_SHIFT) | + (gpio << IPC_VTT_GPIO_PIN_SHIFT); +} + /* Public functions */ /** * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use @@ -294,7 +307,8 @@ static int wkup_m3_prepare_low_power(struct wkup_m3_ipc= *m3_ipc, int state) /* Program each required IPC register then write defaults to others */ wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0); wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1); - wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type, 4); + wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type | + m3_ipc->vtt_conf, 4); =20 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3); @@ -433,12 +447,13 @@ static int wkup_m3_rproc_boot_thread(void *arg) static int wkup_m3_ipc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - int irq, ret; + int irq, ret, temp; phandle rproc_phandle; struct rproc *m3_rproc; struct resource *res; struct task_struct *task; struct wkup_m3_ipc *m3_ipc; + struct device_node *np =3D dev->of_node; =20 m3_ipc =3D devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL); if (!m3_ipc) @@ -496,6 +511,13 @@ static int wkup_m3_ipc_probe(struct platform_device *p= dev) =20 m3_ipc->ops =3D &ipc_ops; =20 + if (!of_property_read_u32(np, "ti,vtt-gpio-pin", &temp)) { + if (temp >=3D 0 && temp <=3D 31) + wkup_m3_set_vtt_gpio(m3_ipc, temp); + else + dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp); + } + /* * Wait for firmware loading completion in a thread so we * can boot the wkup_m3 as soon as it's ready without holding diff --git a/include/linux/wkup_m3_ipc.h b/include/linux/wkup_m3_ipc.h index 3f496967b538..2bc52c6381d5 100644 --- a/include/linux/wkup_m3_ipc.h +++ b/include/linux/wkup_m3_ipc.h @@ -33,6 +33,7 @@ struct wkup_m3_ipc { =20 int mem_type; unsigned long resume_addr; + int vtt_conf; int state; =20 struct completion sync_complete; --=20 2.32.0