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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id qq21-20020a17090720d500b006e7eec5c96csm5202286ejb.0.2022.04.07.13.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 13:41:18 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Jisheng Zhang , Sebastian Hesselbarth , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [RESEND PATCH] arm64: dts: synaptics: remove unused DTSI for AS370 Date: Thu, 7 Apr 2022 22:41:15 +0200 Message-Id: <20220407204115.34350-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The as370.dtsi for Synaptics AS370 SoC does not have a user (DTS board file), is uncompilable and untestable. It was added back in 2018. No user appeared since that time, so assume it won't be added. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- The AS370 board was submitted for review in Aug 2021 [1] but after few comments there were no resubmits, so basically this is still a dead DTSI. [1] https://lore.kernel.org/all/CAK8P3a2vkZVt1bb7-iDGaSHp20U9d8QXu6AcrUMceJ= SS9Q_-4Q@mail.gmail.com/ --- .../devicetree/bindings/arm/syna.txt | 4 - arch/arm64/boot/dts/synaptics/as370.dtsi | 173 ------------------ 2 files changed, 177 deletions(-) delete mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation= /devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. =20 --------------------------------------------------------------- =20 -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: =20 diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts= /synaptics/as370.dtsi deleted file mode 100644 index 4bb5d650df9c..000000000000 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible =3D "syna,as370"; - interrupt-parent =3D <&gic>; - #address-cells =3D <2>; - #size-cells =3D <2>; - - psci { - compatible =3D "arm,psci-1.0"; - method =3D "smc"; - }; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - - cpu0: cpu@0 { - compatible =3D "arm,cortex-a53"; - device_type =3D "cpu"; - reg =3D <0x0>; - enable-method =3D "psci"; - next-level-cache =3D <&l2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible =3D "arm,cortex-a53"; - device_type =3D "cpu"; - reg =3D <0x1>; - enable-method =3D "psci"; - next-level-cache =3D <&l2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible =3D "arm,cortex-a53"; - device_type =3D "cpu"; - reg =3D <0x2>; - enable-method =3D "psci"; - next-level-cache =3D <&l2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible =3D "arm,cortex-a53"; - device_type =3D "cpu"; - reg =3D <0x3>; - enable-method =3D "psci"; - next-level-cache =3D <&l2>; - cpu-idle-states =3D <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible =3D "cache"; - }; - - idle-states { - entry-method =3D "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible =3D "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param =3D <0x0010000>; - entry-latency-us =3D <75>; - exit-latency-us =3D <155>; - min-residency-us =3D <1000>; - }; - }; - }; - - osc: osc { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <25000000>; - }; - - pmu { - compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D , - , - , - ; - interrupt-affinity =3D <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; - }; - - soc@f7000000 { - compatible =3D "simple-bus"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible =3D "arm,gic-400"; - #interrupt-cells =3D <3>; - interrupt-controller; - reg =3D <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts =3D ; - }; - - apb@e80000 { - compatible =3D "simple-bus"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0xc00 0x100>; - interrupts =3D ; - clocks =3D <&osc>; - reg-shift =3D <2>; - status =3D "disabled"; - }; - - gpio0: gpio@1800 { - compatible =3D "snps,dw-apb-gpio"; - reg =3D <0x1800 0x400>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - porta: gpio-port@0 { - compatible =3D "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells =3D <2>; - ngpios =3D <32>; - reg =3D <0>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D ; - }; - }; - - gpio1: gpio@2000 { - compatible =3D "snps,dw-apb-gpio"; - reg =3D <0x2000 0x400>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - portb: gpio-port@1 { - compatible =3D "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells =3D <2>; - ngpios =3D <32>; - reg =3D <0>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D ; - }; - }; - }; - }; -}; --=20 2.32.0