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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id hp11-20020a1709073e0b00b006dfd53a0e39sm7691029ejc.135.2022.04.07.07.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 07:30:55 -0700 (PDT) From: Krzysztof Kozlowski To: Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] ARM: dts: socfpga: align SPI NOR node name with dtschema Date: Thu, 7 Apr 2022 16:30:49 +0200 Message-Id: <20220407143049.294794-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/bo= ot/dts/socfpga_arria10_socdk_qspi.dts index 2a745522404d..11ccdc6c2dc6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -9,7 +9,7 @@ &qspi { status =3D "okay"; =20 - flash0: n25q00@0 { + flash0: flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/d= ts/socfpga_cyclone5_socdk.dts index 253ef139181d..b2241205c7a9 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -121,7 +121,7 @@ &mmc0 { &qspi { status =3D "okay"; =20 - flash0: n25q00@0 { + flash0: flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/d= ts/socfpga_cyclone5_sodia.dts index b0003f350e65..2564671fc1c6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -113,7 +113,7 @@ &usb1 { &qspi { status =3D "okay"; =20 - flash0: n25q512a@0 { + flash0: flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "micron,n25q512a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/= boot/dts/socfpga_cyclone5_vining_fpga.dts index 25874e1b9c82..f24f17c2f5ee 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -221,7 +221,7 @@ at24@50 { &qspi { status =3D "okay"; =20 - n25q128@0 { + flash@0 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "micron,n25q128", "jedec,spi-nor"; @@ -238,7 +238,7 @@ n25q128@0 { cdns,tslch-ns =3D <4>; }; =20 - n25q00@1 { + flash@1 { #address-cells =3D <1>; #size-cells =3D <1>; compatible =3D "micron,mt25qu02g", "jedec,spi-nor"; --=20 2.32.0