From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED551C433EF for ; Thu, 7 Apr 2022 12:59:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245613AbiDGNBU (ORCPT ); Thu, 7 Apr 2022 09:01:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245609AbiDGNBQ (ORCPT ); Thu, 7 Apr 2022 09:01:16 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83E6A16F049 for ; Thu, 7 Apr 2022 05:59:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336355; x=1680872355; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ApMG1Bi4oDU5ZFDZMfoyC94c3HIadlRWRMcWM6vvhvc=; b=i+pxCS9iNsa96dRe/3AdvzhsWVsxgp70n/Z1lJzfXSFK/awJ/eXibjv/ xphohoCEEAKZAekDhSylewVm/hLstM3ccsRqQ/457mqrtAVKO2U/GT9Hd KnpAajeELZk200ogkWP8NOYAC3334ghBS+3cVqLKmEqBKd8Dbz/NNSREj WLiBEhFlsaBGjQjGKMuggx43txN5mgNraYEIJqM4R1VfJfbP0GnKruVZP cDlmuoEPIIS4DlxCSxMSbZusSGjzNmcQvKW4qrj7J3NBG6z2eZNzzwrQN fush70u3iFeQvdHyBDVaHwvgdzaFLRt/lRChadr9kkazdDiyL6xG43Mao A==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="261307922" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="261307922" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:15 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040733" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:11 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tvrtko Ursulin , Daniele Ceraolo Spurio Subject: [PATCH 01/20] drm/i915/gsc: add gsc as a mei auxiliary device Date: Thu, 7 Apr 2022 15:58:20 +0300 Message-Id: <20220407125839.1479249-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Acked-by: Tvrtko Ursulin Reviewed-by: Daniele Ceraolo Spurio --- MAINTAINERS | 1 + drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/gt/intel_gsc.c | 204 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++ drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_device_info.h | 2 + include/linux/mei_aux.h | 19 +++ 15 files changed, 303 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h create mode 100644 include/linux/mei_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index d54b9f15ffce..42ca741074cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9995,6 +9995,7 @@ S: Supported F: Documentation/driver-api/mei/* F: drivers/misc/mei/ F: drivers/watchdog/mei_wdt.c +F: include/linux/mei_aux.h F: include/linux/mei_cl_bus.h F: include/uapi/linux/mei.h F: samples/mei/* diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index b8d45d259337..aa1e7f0b1fe4 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -30,6 +30,7 @@ config DRM_I915 select VMAP_PFN select DRM_TTM select DRM_BUDDY + select AUXILIARY_BUS help Choose this option if you have a system that has "Intel Graphics Media Accelerator" or "HD Graphics" integrated graphics, diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 7e37455ba88d..cd0bf6806228 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -204,6 +204,9 @@ i915-y +=3D gt/uc/intel_uc.o \ gt/uc/intel_huc_debugfs.o \ gt/uc/intel_huc_fw.o =20 +# graphics system controller (GSC) support +i915-y +=3D gt/intel_gsc.o + # modesetting core code i915-y +=3D \ display/hsw_ips.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c new file mode 100644 index 000000000000..21e860861f0b --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "i915_drv.h" +#include "i915_reg.h" +#include "gt/intel_gsc.h" +#include "gt/intel_gt.h" + +#define GSC_BAR_LENGTH 0x00000FFC + +static void gsc_irq_mask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static void gsc_irq_unmask(struct irq_data *d) +{ + /* generic irq handling */ +} + +static struct irq_chip gsc_irq_chip =3D { + .name =3D "gsc_irq_chip", + .irq_mask =3D gsc_irq_mask, + .irq_unmask =3D gsc_irq_unmask, +}; + +static int gsc_irq_init(int irq) +{ + irq_set_chip_and_handler_name(irq, &gsc_irq_chip, + handle_simple_irq, "gsc_irq_handler"); + + return irq_set_chip_data(irq, NULL); +} + +struct gsc_def { + const char *name; + unsigned long bar; + size_t bar_size; +}; + +/* gsc resources and definitions (HECI1 and HECI2) */ +static const struct gsc_def gsc_def_dg1[] =3D { + { + /* HECI1 not yet implemented. */ + }, + { + .name =3D "mei-gscfi", + .bar =3D DG1_GSC_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + } +}; + +static void gsc_release_dev(struct device *dev) +{ + struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + + kfree(adev); +} + +static void gsc_destroy_one(struct intel_gsc_intf *intf) +{ + if (intf->adev) { + auxiliary_device_delete(&intf->adev->aux_dev); + auxiliary_device_uninit(&intf->adev->aux_dev); + intf->adev =3D NULL; + } + if (intf->irq >=3D 0) + irq_free_desc(intf->irq); + intf->irq =3D -1; +} + +static void gsc_init_one(struct drm_i915_private *i915, + struct intel_gsc_intf *intf, + unsigned int intf_id) +{ + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); + struct mei_aux_device *adev; + struct auxiliary_device *aux_dev; + const struct gsc_def *def; + int ret; + + intf->irq =3D -1; + intf->id =3D intf_id; + + if (intf_id =3D=3D 0 && !HAS_HECI_PXP(i915)) + return; + + def =3D &gsc_def_dg1[intf_id]; + + if (!def->name) { + drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1); + return; + } + + intf->irq =3D irq_alloc_desc(0); + if (intf->irq < 0) { + drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); + return; + } + + ret =3D gsc_irq_init(intf->irq); + if (ret < 0) { + drm_err(&i915->drm, "gsc irq init failed %d\n", ret); + goto fail; + } + + adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + goto fail; + + adev->irq =3D intf->irq; + adev->bar.parent =3D &pdev->resource[0]; + adev->bar.start =3D def->bar + pdev->resource[0].start; + adev->bar.end =3D adev->bar.start + def->bar_size - 1; + adev->bar.flags =3D IORESOURCE_MEM; + adev->bar.desc =3D IORES_DESC_NONE; + + aux_dev =3D &adev->aux_dev; + aux_dev->name =3D def->name; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D gsc_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret < 0) { + drm_err(&i915->drm, "gsc aux init failed %d\n", ret); + kfree(adev); + goto fail; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret < 0) { + drm_err(&i915->drm, "gsc aux add failed %d\n", ret); + /* adev will be freed with the put_device() and .release sequence */ + auxiliary_device_uninit(aux_dev); + goto fail; + } + intf->adev =3D adev; + + return; +fail: + gsc_destroy_one(intf); +} + +static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id) +{ + int ret; + + if (intf_id >=3D INTEL_GSC_NUM_INTERFACES) { + drm_warn_once(>->i915->drm, "GSC irq: intf_id %d is out of range", int= f_id); + return; + } + + if (!HAS_HECI_GSC(gt->i915)) { + drm_warn_once(>->i915->drm, "GSC irq: not supported"); + return; + } + + if (gt->gsc.intf[intf_id].irq < 0) { + drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set"); + return; + } + + ret =3D generic_handle_irq(gt->gsc.intf[intf_id].irq); + if (ret) + drm_err_ratelimited(>->i915->drm, "error handling GSC irq: %d\n", ret); +} + +void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir) +{ + if (iir & GSC_IRQ_INTF(0)) + gsc_irq_handler(gt, 0); + if (iir & GSC_IRQ_INTF(1)) + gsc_irq_handler(gt, 1); +} + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915) +{ + unsigned int i; + + if (!HAS_HECI_GSC(i915)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + gsc_init_one(i915, &gsc->intf[i], i); +} + +void intel_gsc_fini(struct intel_gsc *gsc) +{ + struct intel_gt *gt =3D gsc_to_gt(gsc); + unsigned int i; + + if (!HAS_HECI_GSC(gt->i915)) + return; + + for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) + gsc_destroy_one(&gsc->intf[i]); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/= intel_gsc.h new file mode 100644 index 000000000000..68582f912b21 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + */ +#ifndef __INTEL_GSC_DEV_H__ +#define __INTEL_GSC_DEV_H__ + +#include + +struct drm_i915_private; +struct intel_gt; +struct mei_aux_device; + +#define INTEL_GSC_NUM_INTERFACES 2 +/* + * The HECI1 bit corresponds to bit15 and HECI2 to bit14. + * The reason for this is to allow growth for more interfaces in the futur= e. + */ +#define GSC_IRQ_INTF(_x) BIT(15 - (_x)) + +/** + * struct intel_gsc - graphics security controller + * @intf : gsc interface + */ +struct intel_gsc { + struct intel_gsc_intf { + struct mei_aux_device *adev; + int irq; + unsigned int id; + } intf[INTEL_GSC_NUM_INTERFACES]; +}; + +void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_pr= iv); +void intel_gsc_fini(struct intel_gsc *gsc); +void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir); + +#endif /* __INTEL_GSC_DEV_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/i= ntel_gt.c index f0014c5072c9..92394f13b42f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -456,6 +456,8 @@ void intel_gt_chipset_flush(struct intel_gt *gt) =20 void intel_gt_driver_register(struct intel_gt *gt) { + intel_gsc_init(>->gsc, gt->i915); + intel_rps_driver_register(>->rps); =20 intel_gt_debugfs_register(gt); @@ -784,6 +786,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt) intel_wakeref_t wakeref; =20 intel_rps_driver_unregister(>->rps); + intel_gsc_fini(>->gsc); =20 intel_pxp_fini(>->pxp); =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/i= ntel_gt.h index 0163bba0959e..44c6cb63ccbc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -46,6 +46,11 @@ static inline struct intel_gt *huc_to_gt(struct intel_hu= c *huc) return container_of(huc, struct intel_gt, uc.huc); } =20 +static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) +{ + return container_of(gsc, struct intel_gt, gsc); +} + void intel_root_gt_init_early(struct drm_i915_private *i915); int intel_gt_assign_ggtt(struct intel_gt *gt); int intel_gt_init_mmio(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/= gt/intel_gt_irq.c index e443ac4c8059..88b4becfcb17 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -68,6 +68,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 ins= tance, if (instance =3D=3D OTHER_KCR_INSTANCE) return intel_pxp_irq_handler(>->pxp, iir); =20 + if (instance =3D=3D OTHER_GSC_INSTANCE) + return intel_gsc_irq_handler(gt, iir); + WARN_ONCE(1, "unhandled other interrupt instance=3D0x%x, iir=3D0x%x\n", instance, iir); } @@ -184,6 +187,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); if (CCS_MASK(gt)) intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); =20 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); @@ -201,6 +206,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); =20 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); @@ -215,6 +222,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) { struct intel_uncore *uncore =3D gt->uncore; u32 irqs =3D GT_RENDER_USER_INTERRUPT; + const u32 gsc_mask =3D GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); u32 dmask; u32 smask; =20 @@ -233,6 +241,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); if (CCS_MASK(gt)) intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, + gsc_mask); =20 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); @@ -250,6 +261,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); + if (HAS_HECI_GSC(gt->i915)) + intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); =20 /* * RPS interrupts will get enabled/disabled on demand when RPS itself diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915= /gt/intel_gt_regs.h index 0a5c2648aaf0..5d8c8b4e2f7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1484,6 +1484,7 @@ #define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 #define OTHER_KCR_INSTANCE 4 +#define OTHER_GSC_INSTANCE 6 =20 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i91= 5/gt/intel_gt_types.h index 937b2e1a305e..b06611c1d4ad 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -16,6 +16,7 @@ #include =20 #include "uc/intel_uc.h" +#include "intel_gsc.h" =20 #include "i915_vma.h" #include "intel_engine_types.h" @@ -73,6 +74,7 @@ struct intel_gt { struct i915_ggtt *ggtt; =20 struct intel_uc uc; + struct intel_gsc gsc; =20 struct mutex tlb_invalidate_lock; =20 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 06e7c2802c5e..907eda7edf1b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1307,6 +1307,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, =20 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) =20 +#define HAS_HECI_PXP(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_pxp) + +#define HAS_HECI_GSCFI(dev_priv) \ + (INTEL_INFO(dev_priv)->has_heci_gscfi) + +#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(d= ev_priv)) + #define HAS_MSO(i915) (DISPLAY_VER(i915) >=3D 12) =20 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pc= i.c index 736e04078f56..06e6dad0d7f7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -901,7 +901,8 @@ static const struct intel_device_info rkl_info =3D { .has_llc =3D 0, \ .has_pxp =3D 0, \ .has_snoop =3D 1, \ - .is_dgfx =3D 1 + .is_dgfx =3D 1, \ + .has_heci_gscfi =3D 1 =20 static const struct intel_device_info dg1_info =3D { GEN12_FEATURES, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index fef71b242706..1dd7b7de6002 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -976,6 +976,8 @@ #define GEN12_COMPUTE2_RING_BASE 0x1e000 #define GEN12_COMPUTE3_RING_BASE 0x26000 #define BLT_RING_BASE 0x22000 +#define DG1_GSC_HECI1_BASE 0x00258000 +#define DG1_GSC_HECI2_BASE 0x00259000 =20 =20 =20 diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i91= 5/intel_device_info.h index f9b955810593..576d15a04c9e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -141,6 +141,8 @@ enum intel_ppgtt_type { func(has_flat_ccs); \ func(has_global_mocs); \ func(has_gt_uc); \ + func(has_heci_pxp); \ + func(has_heci_gscfi); \ func(has_guc_deprivilege); \ func(has_l3_dpf); \ func(has_llc); \ diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h new file mode 100644 index 000000000000..587f25128848 --- /dev/null +++ b/include/linux/mei_aux.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Intel Corporation. All rights reserved. + */ +#ifndef _LINUX_MEI_AUX_H +#define _LINUX_MEI_AUX_H + +#include + +struct mei_aux_device { + struct auxiliary_device aux_dev; + int irq; + struct resource bar; +}; + +#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct mei_aux_device, aux_dev) + +#endif /* _LINUX_MEI_AUX_H */ --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED1BC433EF for ; Thu, 7 Apr 2022 12:59:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245620AbiDGNB2 (ORCPT ); Thu, 7 Apr 2022 09:01:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245615AbiDGNB0 (ORCPT ); Thu, 7 Apr 2022 09:01:26 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E624817DCB0 for ; Thu, 7 Apr 2022 05:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336366; x=1680872366; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p7SudjqeZZVQCjbanffD3VlgVDgmzgqVlkINc+gOQ80=; b=MdD+gJvEf46KG5AF5MmCr83a4ejwA7eG0+p+ffkpRJQakHAFnZRkfTuP Zt3qI1I8Vk44jpNJoMjXzZc/VPU0Gsbp65KK7fuPZgpMgTKZrdxyaZITk wJpRO0sb1M8Jum+6dFMlMZ+JJMoC5259ffguFnPjius6FT366f4vRct+i qd78ltQgSgb4QJYLR520Fa9LzV43JZvhnsAx+r9tn40vZJXG8iKH3Ew9Q m5Ll4pfwFt3+wXu3PiysxryHCYt6pza2IFC1zGzjPV3tmREMnFxIdTzOm 75NqgzAPxJm0EhMpc8UBMNKhhhMfk2nDNHMtFpPK3VLu6vhrNYK+Hn0my Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907434" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907434" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:26 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040782" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:22 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 02/20] mei: add support for graphics system controller (gsc) devices Date: Thu, 7 Apr 2022 15:58:21 +0300 Message-Id: <20220407125839.1479249-3-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC is a graphics system controller, based on CSE, it provides a chassis controller for graphics discrete cards, as well as it supports media protection on selected devices. mei_gsc binds to a auxiliary devices exposed by Intel discrete driver i915. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/Kconfig | 14 +++ drivers/misc/mei/Makefile | 3 + drivers/misc/mei/gsc-me.c | 194 ++++++++++++++++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 27 +++++- drivers/misc/mei/hw-me.h | 2 + 5 files changed, 238 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/mei/gsc-me.c diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 0e0bcd0da852..d21486d69df2 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -46,6 +46,20 @@ config INTEL_MEI_TXE Supported SoCs: Intel Bay Trail =20 +config INTEL_MEI_GSC + tristate "Intel MEI GSC embedded device" + depends on INTEL_MEI + depends on INTEL_MEI_ME + depends on X86 && PCI + depends on DRM_I915 + help + Intel auxiliary driver for GSC devices embedded in Intel graphics devic= es. + + An MEI device here called GSC can be embedded in an + Intel graphics devices, to support a range of chassis + tasks such as graphics card firmware update and security + tasks. + source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" =20 diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index d8e5165917f2..fb740d754900 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) +=3D mei-me.o mei-me-objs :=3D pci-me.o mei-me-objs +=3D hw-me.o =20 +obj-$(CONFIG_INTEL_MEI_GSC) +=3D mei-gsc.o +mei-gsc-objs :=3D gsc-me.o + obj-$(CONFIG_INTEL_MEI_TXE) +=3D mei-txe.o mei-txe-objs :=3D pci-txe.o mei-txe-objs +=3D hw-txe.o diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c new file mode 100644 index 000000000000..64b02adf3149 --- /dev/null +++ b/drivers/misc/mei/gsc-me.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved. + * + * Intel Management Engine Interface (Intel MEI) Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mei_dev.h" +#include "hw-me.h" +#include "hw-me-regs.h" + +#include "mei-trace.h" + +#define MEI_GSC_RPM_TIMEOUT 500 + +static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *= val) +{ + struct mei_me_hw *hw =3D to_me_hw(dev); + + *val =3D ioread32(hw->mem_addr + where + 0xC00); + + return 0; +} + +static int mei_gsc_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *aux_dev_id) +{ + struct mei_aux_device *adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + struct mei_device *dev; + struct mei_me_hw *hw; + struct device *device; + const struct mei_cfg *cfg; + int ret; + + cfg =3D mei_me_get_cfg(aux_dev_id->driver_data); + if (!cfg) + return -ENODEV; + + device =3D &aux_dev->dev; + + dev =3D mei_me_dev_init(device, cfg); + if (IS_ERR(dev)) { + ret =3D PTR_ERR(dev); + goto err; + } + + hw =3D to_me_hw(dev); + hw->mem_addr =3D devm_ioremap_resource(device, &adev->bar); + if (IS_ERR(hw->mem_addr)) { + dev_err(device, "mmio not mapped\n"); + ret =3D PTR_ERR(hw->mem_addr); + goto err; + } + + hw->irq =3D adev->irq; + hw->read_fws =3D mei_gsc_read_hfs; + + dev_set_drvdata(device, dev); + + ret =3D devm_request_threaded_irq(device, hw->irq, + mei_me_irq_quick_handler, + mei_me_irq_thread_handler, + IRQF_ONESHOT, KBUILD_MODNAME, dev); + if (ret) { + dev_err(device, "irq register failed %d\n", ret); + goto err; + } + + pm_runtime_get_noresume(device); + pm_runtime_set_active(device); + pm_runtime_enable(device); + + if (mei_start(dev)) { + dev_err(device, "init hw failure.\n"); + ret =3D -ENODEV; + goto irq_err; + } + + pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); + pm_runtime_use_autosuspend(device); + + ret =3D mei_register(dev, device); + if (ret) + goto register_err; + + pm_runtime_put_noidle(device); + return 0; + +register_err: + mei_stop(dev); +irq_err: + devm_free_irq(device, hw->irq, dev); + +err: + dev_err(device, "probe failed: %d\n", ret); + dev_set_drvdata(device, NULL); + return ret; +} + +static void mei_gsc_remove(struct auxiliary_device *aux_dev) +{ + struct mei_device *dev; + struct mei_me_hw *hw; + + dev =3D dev_get_drvdata(&aux_dev->dev); + if (!dev) + return; + + hw =3D to_me_hw(dev); + + mei_stop(dev); + + mei_deregister(dev); + + pm_runtime_disable(&aux_dev->dev); + + mei_disable_interrupts(dev); + devm_free_irq(&aux_dev->dev, hw->irq, dev); +} + +static int __maybe_unused mei_gsc_pm_suspend(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + + mei_stop(dev); + + mei_disable_interrupts(dev); + + return 0; +} + +static int __maybe_unused mei_gsc_pm_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + int err; + + if (!dev) + return -ENODEV; + + err =3D mei_restart(dev); + if (err) + return err; + + /* Start timer if stopped in suspend */ + schedule_delayed_work(&dev->timer_work, HZ); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); + +static const struct auxiliary_device_id mei_gsc_id_table[] =3D { + { + .name =3D "i915.mei-gsc", + .driver_data =3D MEI_ME_GSC_CFG, + + }, + { + .name =3D "i915.mei-gscfi", + .driver_data =3D MEI_ME_GSCFI_CFG, + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table); + +static struct auxiliary_driver mei_gsc_driver =3D { + .probe =3D mei_gsc_probe, + .remove =3D mei_gsc_remove, + .driver =3D { + /* auxiliary_driver_register() sets .name to be the modname */ + .pm =3D &mei_gsc_pm_ops, + }, + .id_table =3D mei_gsc_id_table +}; +module_auxiliary_driver(mei_gsc_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_ALIAS("auxiliary:i915.mei-gsc"); +MODULE_ALIAS("auxiliary:i915.mei-gscfi"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 719fee9af156..03945d3b34da 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *d= ev_id) me_intr_disable(dev, hcsr); return IRQ_WAKE_THREAD; } +EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler); =20 /** * mei_me_irq_thread_handler - function called after ISR to handle the int= errupt @@ -1326,6 +1327,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *= dev_id) mutex_unlock(&dev->device_lock); return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); =20 static const struct mei_hw_ops mei_me_hw_ops =3D { =20 @@ -1440,6 +1442,12 @@ static bool mei_me_fw_type_sps_ign(const struct pci_= dev *pdev) #define MEI_CFG_KIND_ITOUCH \ .kind =3D "itouch" =20 +#define MEI_CFG_TYPE_GSC \ + .kind =3D "gsc" + +#define MEI_CFG_TYPE_GSCFI \ + .kind =3D "gscfi" + #define MEI_CFG_FW_SPS_IGN \ .quirk_probe =3D mei_me_fw_type_sps_ign =20 @@ -1572,6 +1580,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg =3D= { MEI_CFG_FW_SPS_IGN, }; =20 +/* Graphics System Controller */ +static const struct mei_cfg mei_me_gsc_cfg =3D { + MEI_CFG_TYPE_GSC, + MEI_CFG_PCH8_HFS, +}; + +/* Graphics System Controller Firmware Interface */ +static const struct mei_cfg mei_me_gscfi_cfg =3D { + MEI_CFG_TYPE_GSCFI, + MEI_CFG_PCH8_HFS, +}; + /* * mei_cfg_list - A list of platform platform specific configurations. * Note: has to be synchronized with enum mei_cfg_idx. @@ -1592,6 +1612,8 @@ static const struct mei_cfg *const mei_cfg_list[] =3D= { [MEI_ME_PCH12_SPS_ITOUCH_CFG] =3D &mei_me_pch12_itouch_sps_cfg, [MEI_ME_PCH15_CFG] =3D &mei_me_pch15_cfg, [MEI_ME_PCH15_SPS_CFG] =3D &mei_me_pch15_sps_cfg, + [MEI_ME_GSC_CFG] =3D &mei_me_gsc_cfg, + [MEI_ME_GSCFI_CFG] =3D &mei_me_gscfi_cfg, }; =20 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) @@ -1602,7 +1624,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t i= dx) return NULL; =20 return mei_cfg_list[idx]; -}; +} +EXPORT_SYMBOL_GPL(mei_me_get_cfg); =20 /** * mei_me_dev_init - allocates and initializes the mei device structure @@ -1637,4 +1660,4 @@ struct mei_device *mei_me_dev_init(struct device *par= ent, =20 return dev; } - +EXPORT_SYMBOL_GPL(mei_me_dev_init); diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index 00a7132ac7a2..a071c645e905 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -112,6 +112,8 @@ enum mei_cfg_idx { MEI_ME_PCH12_SPS_ITOUCH_CFG, MEI_ME_PCH15_CFG, MEI_ME_PCH15_SPS_CFG, + MEI_ME_GSC_CFG, + MEI_ME_GSCFI_CFG, MEI_ME_NUM_CFG, }; =20 --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C65EC433F5 for ; Thu, 7 Apr 2022 12:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245626AbiDGNBe (ORCPT ); Thu, 7 Apr 2022 09:01:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245615AbiDGNBb (ORCPT ); Thu, 7 Apr 2022 09:01:31 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8D8B188548 for ; Thu, 7 Apr 2022 05:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336371; x=1680872371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+l7ZQF/kGwb9eDT6CzfhLeAAWbTSQre5kLBCyn0KjB0=; b=feHxusIaMVG0cuy5mieW4a6eJRlfoq7RJpUK8iGFfCTjeakXa9Cp5dH5 Jmr0uJ9YTD6Zf4NIAbFB899SJlOrYFD2ZwM2/K4tlD4c/0BL23NGd/BPR 94Yx8yGDotCtorw2R3Kc15R1XfGL0r2D1WU2lC0ujJBl3NHIQ0e4mB2Ad 6Xbk+ZYCEAvoIe/mup/hbg9m24LP05kCkFZBWiP814VqUB+HNl07fTcYQ yFsYkoa+nWAOQRJ0eSUL3Qh2WKKK4z+ZjdOP2P1i/Z1t+XIXcaXlIDmkc o/gQ3kiAZQFOT+Azj3KyRp5jAJcEUi0WbKBUnlde8VrdggNBJwRTd8aBe Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907442" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907442" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:30 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040793" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:26 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 03/20] mei: gsc: setup char driver alive in spite of firmware handshake failure Date: Thu, 7 Apr 2022 15:58:22 +0300 Message-Id: <20220407125839.1479249-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Setup char device in spite of firmware handshake failure. In order to provide host access to the firmware status registers and other information required for the manufacturing process. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/gsc-me.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 64b02adf3149..58e39c00f150 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -79,11 +79,12 @@ static int mei_gsc_probe(struct auxiliary_device *aux_d= ev, pm_runtime_set_active(device); pm_runtime_enable(device); =20 - if (mei_start(dev)) { - dev_err(device, "init hw failure.\n"); - ret =3D -ENODEV; - goto irq_err; - } + /* Continue to char device setup in spite of firmware handshake failure. + * In order to provide access to the firmware status registers to the user + * space via sysfs. + */ + if (mei_start(dev)) + dev_warn(device, "init hw failure.\n"); =20 pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT); pm_runtime_use_autosuspend(device); @@ -97,7 +98,6 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev, =20 register_err: mei_stop(dev); -irq_err: devm_free_irq(device, hw->irq, dev); =20 err: --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B75EC433F5 for ; Thu, 7 Apr 2022 12:59:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245631AbiDGNBi (ORCPT ); Thu, 7 Apr 2022 09:01:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245627AbiDGNBe (ORCPT ); Thu, 7 Apr 2022 09:01:34 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C29C1903D6 for ; Thu, 7 Apr 2022 05:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336374; x=1680872374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WovsgYiVLZg/i7UC+9r4MQsqX4gv9lKhRB/u0hmFKfI=; b=GKQ8b/kpuavsOokcR4+ahZPVRBAfinvttCTRpd4o/rmGqDaVHNqVjIoQ ho8O6Y3kNV3UZRdUCvkfG3M8pKiiTHoRBr2nllJCkDlINwwm+Cugerq6F 9Emo4llhBYriAhl/mCOCJ8BAr6aEy8DOfpcsvbPKegHVWa5mvO4ZFpzqU +opLtcM2SRKg9zESGLf2JYtaKwHGfPBgwRthEsMg+ph0qfwO4xEQAo2tc wxsWsObKtVK4kaZhhpY99xomd1U/SrHXoPX2KyGgJ0aHyiGhzQ/+1k905 eqyZNn2UxPoh7sVSjbuecU5eTjpOYwjg94++i4XIQ8hcNXpFLFlhL3Moa w==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907462" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907462" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:34 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040806" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:30 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/20] mei: gsc: add runtime pm handlers Date: Thu, 7 Apr 2022 15:58:23 +0300 Message-Id: <20220407125839.1479249-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler Implement runtime handlers for mei-gsc, to track idle state of the device properly. CC: Rodrigo Vivi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Rodrigo Vivi --- drivers/misc/mei/gsc-me.c | 67 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 58e39c00f150..32ea75f5e7aa 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -159,7 +159,72 @@ static int __maybe_unused mei_gsc_pm_resume(struct dev= ice *device) return 0; } =20 -static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_re= sume); +static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + + if (!dev) + return -ENODEV; + if (mei_write_is_idle(dev)) + pm_runtime_autosuspend(device); + + return -EBUSY; +} + +static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *devic= e) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + int ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + if (mei_write_is_idle(dev)) { + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_ON; + ret =3D 0; + } else { + ret =3D -EAGAIN; + } + + mutex_unlock(&dev->device_lock); + + return ret; +} + +static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device) +{ + struct mei_device *dev =3D dev_get_drvdata(device); + struct mei_me_hw *hw; + irqreturn_t irq_ret; + + if (!dev) + return -ENODEV; + + mutex_lock(&dev->device_lock); + + hw =3D to_me_hw(dev); + hw->pg_state =3D MEI_PG_OFF; + + mutex_unlock(&dev->device_lock); + + irq_ret =3D mei_me_irq_thread_handler(1, dev); + if (irq_ret !=3D IRQ_HANDLED) + dev_err(dev->dev, "thread handler fail %d\n", irq_ret); + + return 0; +} + +static const struct dev_pm_ops mei_gsc_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(mei_gsc_pm_suspend, + mei_gsc_pm_resume) + SET_RUNTIME_PM_OPS(mei_gsc_pm_runtime_suspend, + mei_gsc_pm_runtime_resume, + mei_gsc_pm_runtime_idle) +}; =20 static const struct auxiliary_device_id mei_gsc_id_table[] =3D { { --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32AEAC433F5 for ; Thu, 7 Apr 2022 12:59:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244841AbiDGNBo (ORCPT ); Thu, 7 Apr 2022 09:01:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245633AbiDGNBi (ORCPT ); Thu, 7 Apr 2022 09:01:38 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7763F1945EE for ; Thu, 7 Apr 2022 05:59:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336379; x=1680872379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2tDSaTXga5Q4o87KQEHKUYopCWX0617A/UkXwV6T7RA=; b=dtIKRUJ5KiSpAFFG4fn/9G3WL+REAh1I4gtS+vMI2Zexd/4jJutERIT/ 1Dco1R+jILnW4kOBp4iR1yo+UZC1nEBPz95qi4SWG10p6+ehlGOv9UZ6i rx1D1FhhXQqjzKQsSUNzXw6juzoYgWSCtrn68+4J1GlvsuUg2CI/3uBtI dYDRjT7WxmEj82vLhroP4vnkOJcUi4BcmIBh4XY4FHwlimI9hURl6MXPA IhOUnM2JvQqZkcElQVeIk6UsEN75l1h08F5wZ2QE3cO4C3xmQM2tL7JPU a1AHd+6G0xGhmVi6RaOq95SxNysT4Egxq/uw+n4+W9CJZOozrUcFYyiXm A==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907472" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907472" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:39 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040822" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:35 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ashutosh Dixit , Daniele Ceraolo Spurio Subject: [PATCH 05/20] mei: gsc: retrieve the firmware version Date: Thu, 7 Apr 2022 15:58:24 +0300 Message-Id: <20220407125839.1479249-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a hook to retrieve the firmware version of the GSC devices to bus-fixup. GSC has a different MKHI clients GUIDs but the same message structure to retrieve the firmware version as MEI so mei_fwver() can be reused. CC: Ashutosh Dixit Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/bus-fixup.c | 25 +++++++++++++++++++++++++ drivers/misc/mei/hw-me.c | 2 ++ 2 files changed, 27 insertions(+) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 67844089db21..59506ba6fc48 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -30,6 +30,12 @@ static const uuid_le mei_nfc_info_guid =3D MEI_UUID_NFC_= INFO; #define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \ 0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb) =20 +#define MEI_UUID_IGSC_MKHI UUID_LE(0xE2C2AFA2, 0x3817, 0x4D19, \ + 0x9D, 0x95, 0x06, 0xB1, 0x6B, 0x58, 0x8A, 0x5D) + +#define MEI_UUID_IGSC_MKHI_FIX UUID_LE(0x46E0C1FB, 0xA546, 0x414F, \ + 0x91, 0x70, 0xB7, 0xF4, 0x6D, 0x57, 0xB4, 0xAD) + #define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \ 0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04) =20 @@ -241,6 +247,23 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev) mei_cldev_disable(cldev); } =20 +static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev) +{ + int ret; + + /* No need to enable the client if nothing is needed from it */ + if (!cldev->bus->fw_f_fw_ver_supported) + return; + + ret =3D mei_cldev_enable(cldev); + if (ret) + return; + + ret =3D mei_fwver(cldev); + if (ret < 0) + dev_err(&cldev->dev, "FW version command failed %d\n", ret); + mei_cldev_disable(cldev); +} /** * mei_wd - wd client on the bus, change protocol version * as the API has changed. @@ -492,6 +515,8 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc), MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), + MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), MEI_FIXUP(MEI_UUID_PAVP, whitelist), diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 03945d3b34da..9870bf717979 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1584,12 +1584,14 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = =3D { static const struct mei_cfg mei_me_gsc_cfg =3D { MEI_CFG_TYPE_GSC, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* Graphics System Controller Firmware Interface */ static const struct mei_cfg mei_me_gscfi_cfg =3D { MEI_CFG_TYPE_GSCFI, MEI_CFG_PCH8_HFS, + MEI_CFG_FW_VER_SUPP, }; =20 /* --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69A3EC433EF for ; Thu, 7 Apr 2022 12:59:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245644AbiDGNBr (ORCPT ); Thu, 7 Apr 2022 09:01:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245635AbiDGNBn (ORCPT ); Thu, 7 Apr 2022 09:01:43 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8032194FDD for ; Thu, 7 Apr 2022 05:59:43 -0700 (PDT) DKIM-Signature: v=1; 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07 Apr 2022 05:59:40 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 06/20] HAX: drm/i915: force INTEL_MEI_GSC on for CI Date: Thu, 7 Apr 2022 15:58:25 +0300 Message-Id: <20220407125839.1479249-7-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniele Ceraolo Spurio After the new config option is merged we'll enable it by default in the CI config, but for now just force it on via the i915 Kconfig so we can get pre-merge CI results for it. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kcon= fig.debug index e7fd3e76f8a2..be4ef485d6c1 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,7 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC select BROKEN # for prototype uAPI default n help --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF64EC4332F for ; Thu, 7 Apr 2022 12:59:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236667AbiDGNBz (ORCPT ); Thu, 7 Apr 2022 09:01:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245646AbiDGNBs (ORCPT ); Thu, 7 Apr 2022 09:01:48 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18007197AD6 for ; Thu, 7 Apr 2022 05:59:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336388; x=1680872388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lsoZE2d3OyKfgT4dCGNVeGzAtVUNKUrOZNf5/f//xAA=; b=BPhgk7Q8afv6oaNxOZc4koESh50SQsies6PEfA0Anif2X1ajG4kapvMW ILa734DuXZZbCSsJMW2qv8qy0pTdiwKMa78nuQr2ZHusoZPBlCMn8Vabr FNRxrf0jHWfWMi4Ic0xheZRYPmjaFI6KpI4YwD23C/tHOZr2kAjmA3tUz 3O+jgcGuhRuU8Q9MiY2EvHMwsj3hyDT4Bui+JjRMWRlFLKkY+Yqd71maH ul8s4WChAx5b3mpbfFUj5+maA3jIiQfa8wYieBOErQWxR25UbyPQEz56d etDJcwie9avaey4niQkbXPl10wGiMYMC9sJ2QTDfYPGv1pP8djb+ywyWp w==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907485" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907485" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:47 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040853" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:44 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/20] drm/i915/gsc: skip irq initialization if using polling Date: Thu, 7 Apr 2022 15:58:26 +0300 Message-Id: <20220407125839.1479249-8-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart If we use polling instead of interrupts, irq initialization should be skipped. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index 21e860861f0b..280dba4fd32d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -40,6 +40,7 @@ struct gsc_def { const char *name; unsigned long bar; size_t bar_size; + bool use_polling; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -97,6 +98,10 @@ static void gsc_init_one(struct drm_i915_private *i915, return; } =20 + /* skip irq initialization */ + if (def->use_polling) + goto add_device; + intf->irq =3D irq_alloc_desc(0); if (intf->irq < 0) { drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); @@ -109,6 +114,7 @@ static void gsc_init_one(struct drm_i915_private *i915, goto fail; } =20 +add_device: adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); if (!adev) goto fail; @@ -162,10 +168,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsig= ned int intf_id) return; } =20 - if (gt->gsc.intf[intf_id].irq < 0) { - drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set"); + if (gt->gsc.intf[intf_id].irq < 0) return; - } =20 ret =3D generic_handle_irq(gt->gsc.intf[intf_id].irq); if (ret) --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73371C433EF for ; Thu, 7 Apr 2022 13:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241002AbiDGNB6 (ORCPT ); Thu, 7 Apr 2022 09:01:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245637AbiDGNBw (ORCPT ); Thu, 7 Apr 2022 09:01:52 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 814AD1A1289 for ; Thu, 7 Apr 2022 05:59:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336392; x=1680872392; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=563hB/rXHNGZzJHbLZ19JTAegWPlZpDTmnNbjcAniLA=; b=iJuiDbcTx8j3KL9ttC1TjdZyPBy5K5zyp/rRArTSnL4zvA890E1asR4T an5KDfh17ogBOp6lo8LUILnr1fE99jVs5NRqFaZc3F3STbZI5A6Uqsgl9 542bpbK+Uoh5M0X6+MWKgeBrNUH9TN25QDRAhOkhxmyng6wjbRqwbLfgB 6p+9y9fM74tpY1F/nnO2UnWNtjL+iNhQGvhs2jMk9ysy45s4T9wkdHnY0 J6s+wK9iwtseAtvOMIL3wMqjv23MJnmHflLK/P3iM55x5gg5yZSRXQrkP j+JnG3lu2idSg7vGFD3RzW7NrmjiQp4S5fskkN1ZmSECfS+4cHKFUSz59 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907489" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907489" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:52 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040877" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:48 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/20] drm/i915/gsc: add slow_fw flag to the mei auxiliary device Date: Thu, 7 Apr 2022 15:58:27 +0300 Message-Id: <20220407125839.1479249-9-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add slow_fw flag to the mei auxiliary device info to inform the mei driver about slow underlying firmware. Such firmware will require to use larger operation timeouts. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- include/linux/mei_aux.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index 587f25128848..a29f4064b9c0 100644 --- a/include/linux/mei_aux.h +++ b/include/linux/mei_aux.h @@ -11,6 +11,7 @@ struct mei_aux_device { struct auxiliary_device aux_dev; int irq; struct resource bar; + bool slow_fw; }; =20 #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EA07C433EF for ; Thu, 7 Apr 2022 13:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245666AbiDGNCQ (ORCPT ); Thu, 7 Apr 2022 09:02:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245658AbiDGNB5 (ORCPT ); Thu, 7 Apr 2022 09:01:57 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30C3E1A4D48 for ; Thu, 7 Apr 2022 05:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336396; x=1680872396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hwEb6OZ/96yiSjjHSnsTjHLw9pIKJbgTq6k7ARM4atc=; b=DWZV66nkIxWLdwQezucUp8gwmk5BbpbIWGXJI02FtqLDWA/wE/+BLY01 s2Jf49Hgt+oLrnxObnJ3pEYDL+AsYvFJ52etoAHVttt2bh0VVJM9wFdgJ ReCwayuXv5iuUedCJCGAlcdGXA9unI2L86LmhVvTDBLky02n5FJ/DhaGH 0m1tGJCIwO0nP3GhxqN93qfc58Vi6bCn9c0bKE20JkIbsyJZSpXmqB+2y 7fVnS2YBm7wKJfwyIHbXXS7UT+KQTnk3g/92EccmNp6O18/+t6YvEwWsy 9edk5O3kpsBobf7VDIOLNjgZJfq5fERlXnyBoIHaqb7hzfrrMJGIqXqV2 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907497" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907497" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:55 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040897" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:52 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/20] drm/i915/gsc: add slow_fw flag to the gsc device definition Date: Thu, 7 Apr 2022 15:58:28 +0300 Message-Id: <20220407125839.1479249-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add slow_fw flag to the gsc device definition and pass it to mei auxiliary device. Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index 280dba4fd32d..175571c6f71d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -41,6 +41,7 @@ struct gsc_def { unsigned long bar; size_t bar_size; bool use_polling; + bool slow_fw; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -125,6 +126,7 @@ static void gsc_init_one(struct drm_i915_private *i915, adev->bar.end =3D adev->bar.start + def->bar_size - 1; adev->bar.flags =3D IORESOURCE_MEM; adev->bar.desc =3D IORES_DESC_NONE; + adev->slow_fw =3D def->slow_fw; =20 aux_dev =3D &adev->aux_dev; aux_dev->name =3D def->name; --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4D17C433F5 for ; Thu, 7 Apr 2022 13:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245674AbiDGNCU (ORCPT ); Thu, 7 Apr 2022 09:02:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245664AbiDGNCC (ORCPT ); Thu, 7 Apr 2022 09:02:02 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 801A11A4D4C for ; Thu, 7 Apr 2022 06:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336400; x=1680872400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uTo4JKBz3R9DB0Jqa/bBGyfl+v7N2xIKemzf6pgX930=; b=mgZb7GKayQk/ddElYJ8n8j6CNXrHpOiukAWZCOFZQfyZMl9+VELq3wiQ c7UV4ii5Tns6hgHNvtwt0mAbSDAzS0PZubWzmP+hDgQN2oHej6+9m5SEI 7ccOWoRfcgcsPrlECKk6UL7Gly/qgNLDtCW8lrvexTEp20V8EO1yOqEY4 lXboQkD+nK/4Qn88UedoPj/BbS9nt1pQQpxPk8jPAnKYtGXaqYxvhNcEo hfvzRSGoSJ9mRi4IPCQYm5eM56wQ0v7CBHIxeWLFokOcx9ew54Q07z2kn NCYmz0862287oG6v54gH5cWM90K0h/cxFhhSMvhKNJU9a07c1mrSicuTm A==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="241907508" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="241907508" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:00 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571040921" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 05:59:56 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/20] drm/i915/gsc: add GSC XeHP SDV platform definition Date: Thu, 7 Apr 2022 15:58:29 +0300 Message-Id: <20220407125839.1479249-11-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index 175571c6f71d..ffe6716590f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] =3D { } }; =20 +static const struct gsc_def gsc_def_xehpsdv[] =3D { + { + /* HECI1 not enabled on the device. */ + }, + { + .name =3D "mei-gscfi", + .bar =3D DG1_GSC_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + .use_polling =3D true, + .slow_fw =3D true, + } +}; + static void gsc_release_dev(struct device *dev) { struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); @@ -92,7 +105,14 @@ static void gsc_init_one(struct drm_i915_private *i915, if (intf_id =3D=3D 0 && !HAS_HECI_PXP(i915)) return; =20 - def =3D &gsc_def_dg1[intf_id]; + if (IS_DG1(i915)) { + def =3D &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def =3D &gsc_def_xehpsdv[intf_id]; + } else { + drm_warn_once(&i915->drm, "Unknown platform\n"); + return; + } =20 if (!def->name) { drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1); --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D0CC43219 for ; Thu, 7 Apr 2022 13:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245637AbiDGNDb (ORCPT ); Thu, 7 Apr 2022 09:03:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245678AbiDGNCZ (ORCPT ); Thu, 7 Apr 2022 09:02:25 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6147833EB7 for ; Thu, 7 Apr 2022 06:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336414; x=1680872414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PNb+/xiehX/7uIkJ1zKWm+EG1KxQy+hDFZDfI5dC5F4=; b=Sq8mPaopooZAeUDb4y8kkPnVeDvIjhXivBCThEWDH7iTQfla+VH5/y7x C77Cu+54aWF9DjS3oHxdc3mmK3JCmle5/BN3G5/+Amzq8dNBsxJSJPoIB d6Dggh27X+z87Y6OviBYN5vAfTGOYhju++9npWOi/ixJTEHwIYw6WlWvj d+VGgWQqmYIt/47p4x3UZODhr1o4e4nKNVEsPN/4DhCexHj5dAb3U+OA5 j5hi04Ff2N1Wl7l06fGoH/W1tLvj7+RYc2SJiCJsfo6Kwp+sGXNeefCHF dCQa+GGeGezaCjXGUjbe5ZikQ0jXLEDFT2J1w71k5dNexreaRyZ+4nxJA A==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="248842011" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="248842011" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:10 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041028" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:01 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, James Ausmus Subject: [PATCH 11/20] mei: gsc: use polling instead of interrupts Date: Thu, 7 Apr 2022 15:58:30 +0300 Message-Id: <20220407125839.1479249-12-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler A work-around for a HW issue in XEHPSDV that manifests itself when SW reads a gsc register when gsc is sending an interrupt. The work-around is to disable interrupts and to use polling instead. Cc: James Ausmus Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------ drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++--- drivers/misc/mei/hw-me.h | 12 ++++++++ 3 files changed, 105 insertions(+), 13 deletions(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 32ea75f5e7aa..6f262ddfd25a 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "mei_dev.h" #include "hw-me.h" @@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_d= ev, =20 dev_set_drvdata(device, dev); =20 - ret =3D devm_request_threaded_irq(device, hw->irq, - mei_me_irq_quick_handler, - mei_me_irq_thread_handler, - IRQF_ONESHOT, KBUILD_MODNAME, dev); - if (ret) { - dev_err(device, "irq register failed %d\n", ret); - goto err; + /* use polling */ + if (mei_me_hw_use_polling(hw)) { + mei_disable_interrupts(dev); + mei_clear_interrupts(dev); + init_waitqueue_head(&hw->wait_active); + hw->is_active =3D true; /* start in active mode for initialization */ + hw->polling_thread =3D kthread_run(mei_me_polling_thread, dev, + "kmegscirqd/%s", dev_name(device)); + if (IS_ERR(hw->polling_thread)) { + ret =3D PTR_ERR(hw->polling_thread); + dev_err(device, "unable to create kernel thread: %d\n", ret); + goto err; + } + } else { + ret =3D devm_request_threaded_irq(device, hw->irq, + mei_me_irq_quick_handler, + mei_me_irq_thread_handler, + IRQF_ONESHOT, KBUILD_MODNAME, dev); + if (ret) { + dev_err(device, "irq register failed %d\n", ret); + goto err; + } } =20 pm_runtime_get_noresume(device); @@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_de= v, =20 register_err: mei_stop(dev); - devm_free_irq(device, hw->irq, dev); + if (!mei_me_hw_use_polling(hw)) + devm_free_irq(device, hw->irq, dev); =20 err: dev_err(device, "probe failed: %d\n", ret); @@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *a= ux_dev) =20 mei_stop(dev); =20 + hw =3D to_me_hw(dev); + if (mei_me_hw_use_polling(hw)) + kthread_stop(hw->polling_thread); + mei_deregister(dev); =20 pm_runtime_disable(&aux_dev->dev); =20 mei_disable_interrupts(dev); - devm_free_irq(&aux_dev->dev, hw->irq, dev); + if (!mei_me_hw_use_polling(hw)) + devm_free_irq(&aux_dev->dev, hw->irq, dev); } =20 static int __maybe_unused mei_gsc_pm_suspend(struct device *device) @@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(s= truct device *device) if (mei_write_is_idle(dev)) { hw =3D to_me_hw(dev); hw->pg_state =3D MEI_PG_ON; + + if (mei_me_hw_use_polling(hw)) + hw->is_active =3D false; ret =3D 0; } else { ret =3D -EAGAIN; @@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(st= ruct device *device) hw =3D to_me_hw(dev); hw->pg_state =3D MEI_PG_OFF; =20 + if (mei_me_hw_use_polling(hw)) { + hw->is_active =3D true; + wake_up(&hw->wait_active); + } + mutex_unlock(&dev->device_lock); =20 irq_ret =3D mei_me_irq_thread_handler(1, dev); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 9870bf717979..959b3329af60 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include "mei_dev.h" #include "hbm.h" @@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev) */ static void mei_me_intr_enable(struct mei_device *dev) { - u32 hcsr =3D mei_hcsr_read(dev); + u32 hcsr; + + if (mei_me_hw_use_polling(to_me_hw(dev))) + return; =20 - hcsr |=3D H_CSR_IE_MASK; + hcsr =3D mei_hcsr_read(dev) | H_CSR_IE_MASK; mei_hcsr_set(dev, hcsr); } =20 @@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *d= ev) { struct mei_me_hw *hw =3D to_me_hw(dev); =20 + if (mei_me_hw_use_polling(hw)) + return; + synchronize_irq(hw->irq); } =20 @@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *d= ev) { u32 hcsr =3D mei_hcsr_read(dev); =20 - hcsr |=3D H_CSR_IE_MASK | H_IG | H_RDY; + if (!mei_me_hw_use_polling(to_me_hw(dev))) + hcsr |=3D H_CSR_IE_MASK; + + hcsr |=3D H_IG | H_RDY; mei_hcsr_set(dev, hcsr); } =20 @@ -1174,7 +1184,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bo= ol intr_enable) =20 hcsr |=3D H_RST | H_IG | H_CSR_IS_MASK; =20 - if (!intr_enable) + if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev))) hcsr &=3D ~H_CSR_IE_MASK; =20 dev->recvd_hw_ready =3D false; @@ -1329,6 +1339,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void = *dev_id) } EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); =20 +#define MEI_POLLING_TIMEOUT_ACTIVE 100 +#define MEI_POLLING_TIMEOUT_IDLE 500 + +int mei_me_polling_thread(void *_dev) +{ + struct mei_device *dev =3D _dev; + irqreturn_t irq_ret; + long polling_timeout =3D MEI_POLLING_TIMEOUT_ACTIVE; + + dev_dbg(dev->dev, "kernel thread is running\n"); + while (!kthread_should_stop()) { + struct mei_me_hw *hw =3D to_me_hw(dev); + u32 hcsr; + + wait_event_timeout(hw->wait_active, + hw->is_active || kthread_should_stop(), + msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE)); + + if (kthread_should_stop()) + break; + + hcsr =3D mei_hcsr_read(dev); + if (me_intr_src(hcsr)) { + polling_timeout =3D MEI_POLLING_TIMEOUT_ACTIVE; + irq_ret =3D mei_me_irq_thread_handler(1, dev); + if (irq_ret !=3D IRQ_HANDLED) + dev_err(dev->dev, "irq_ret %d\n", irq_ret); + } else { + polling_timeout =3D clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACT= IVE, + MEI_POLLING_TIMEOUT_ACTIVE, + MEI_POLLING_TIMEOUT_IDLE); + } + + schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout)); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mei_me_polling_thread); + static const struct mei_hw_ops mei_me_hw_ops =3D { =20 .trc_status =3D mei_me_trc_status, diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index a071c645e905..ca09274ac299 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -51,6 +51,8 @@ struct mei_cfg { * @d0i3_supported: di03 support * @hbuf_depth: depth of hardware host/write buffer in slots * @read_fws: read FW status register handler + * @wait_active: the polling thread activity wait queue + * @is_active: the device is active */ struct mei_me_hw { const struct mei_cfg *cfg; @@ -60,10 +62,19 @@ struct mei_me_hw { bool d0i3_supported; u8 hbuf_depth; int (*read_fws)(const struct mei_device *dev, int where, u32 *val); + /* polling */ + struct task_struct *polling_thread; + wait_queue_head_t wait_active; + bool is_active; }; =20 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) =20 +static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw) +{ + return hw->irq < 0; +} + /** * enum mei_cfg_idx - indices to platform specific configurations. * @@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev); =20 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); +int mei_me_polling_thread(void *_dev); =20 #endif /* _MEI_INTERFACE_H_ */ --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98BCDC433EF for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="248842022" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="248842022" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:14 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041131" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:07 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/20] mei: gsc: wait for reset thread on stop Date: Thu, 7 Apr 2022 15:58:31 +0300 Message-Id: <20220407125839.1479249-13-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wait for reset work to complete before initiating stop reset flow sequence. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler --- drivers/misc/mei/init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index eb052005ca86..5bb6ba662cc0 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev) =20 mei_clear_interrupts(dev); mei_synchronize_irq(dev); + /* to catch HW-initiated reset */ + mei_cancel_work(dev); =20 mutex_lock(&dev->device_lock); =20 --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C416AC433EF for ; Thu, 7 Apr 2022 13:02:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240506AbiDGNEf (ORCPT ); Thu, 7 Apr 2022 09:04:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245700AbiDGNCa (ORCPT ); Thu, 7 Apr 2022 09:02:30 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1673E994A for ; Thu, 7 Apr 2022 06:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336418; x=1680872418; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2HzDU9iJlkMViSTHOB1v0XvsV1lU5Pq9laruzE8ErdM=; b=KZzw2tFw30Iayz0Vw8XpsJNWr6BpfqzfbnzeCge/+m9EgvfQLLai/lNw a04nhHwXxyIqE9wJgVW0HkZT0slG2lAVU5Z9zwPvdD2Lk7PmmlobYHUbb 23Ko84UkDVUn3AacGvdkNvEIX9m4Y7/l69AA6VjmNXysEX+t3KkIIc/Zv gSBqX7oSvdeMcgFk7sS+THzOACukR3hE3g6M7T91X7Q35q7W6LUctGotg 3mgmV8lKa5hgHatFrKr64tQmj91L+U2Ry2UmrPyUB+lBNWNLWpNjvVoK1 XE4ZERx6o+klvsXWK5DuJXMad7uNZrYvo47lRWqI2ZW1UbRnvLDfnMyw7 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="248842039" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="248842039" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:17 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041147" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:12 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/20] mei: extend timeouts on slow devices. Date: Thu, 7 Apr 2022 15:58:32 +0300 Message-Id: <20220407125839.1479249-14-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Parametrize operational timeouts in order to support slow firmware on some graphic devices. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler --- drivers/misc/mei/bus-fixup.c | 3 +-- drivers/misc/mei/client.c | 14 +++++++------- drivers/misc/mei/gsc-me.c | 2 +- drivers/misc/mei/hbm.c | 12 ++++++------ drivers/misc/mei/hw-me.c | 30 ++++++++++++++++-------------- drivers/misc/mei/hw-me.h | 2 +- drivers/misc/mei/hw-txe.c | 2 +- drivers/misc/mei/hw.h | 5 +++++ drivers/misc/mei/init.c | 19 ++++++++++++++++++- drivers/misc/mei/main.c | 2 +- drivers/misc/mei/mei_dev.h | 16 ++++++++++++++++ drivers/misc/mei/pci-me.c | 2 +- 12 files changed, 74 insertions(+), 35 deletions(-) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 59506ba6fc48..24e91a9ea558 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev) sizeof(struct mkhi_fw_ver)) #define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \ sizeof(struct mkhi_fw_ver_block) * (__num)) -#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */ static int mei_fwver(struct mei_cl_device *cldev) { char buf[MKHI_FWVER_BUF_LEN]; @@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev) =20 ret =3D 0; bytes_recv =3D __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0, - MKHI_RCV_TIMEOUT); + cldev->bus->timeouts.mkhi_recv); if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) { /* * Should be at least one version block, diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c index 31264ab2eb13..e7a16d9b2241 100644 --- a/drivers/misc/mei/client.c +++ b/drivers/misc/mei/client.c @@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, st= ruct mei_cl_cb *cb) } =20 list_move_tail(&cb->list, &dev->ctrl_rd_list); - cl->timer_count =3D MEI_CONNECT_TIMEOUT; + cl->timer_count =3D dev->timeouts.connect; mei_schedule_stall_timer(dev); =20 return 0; @@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl) wait_event_timeout(cl->wait, cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY || cl->state =3D=3D MEI_FILE_DISCONNECTED, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 rets =3D cl->status; @@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, str= uct mei_cl_cb *cb) } =20 list_move_tail(&cb->list, &dev->ctrl_rd_list); - cl->timer_count =3D MEI_CONNECT_TIMEOUT; + cl->timer_count =3D dev->timeouts.connect; mei_schedule_stall_timer(dev); return 0; } @@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_c= lient *me_cl, cl->state =3D=3D MEI_FILE_DISCONNECTED || cl->state =3D=3D MEI_FILE_DISCONNECT_REQUIRED || cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (!mei_cl_is_connected(cl)) { @@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl, cl->notify_en =3D=3D request || cl->status || !mei_cl_is_connected(cl), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (cl->notify_en !=3D request && !cl->status) @@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const= struct file *fp, mutex_unlock(&dev->device_lock); wait_event_timeout(cl->wait, cl->dma_mapped || cl->status, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (!cl->dma_mapped && !cl->status) @@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct = file *fp) mutex_unlock(&dev->device_lock); wait_event_timeout(cl->wait, !cl->dma_mapped || cl->status, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (cl->dma_mapped && !cl->status) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 6f262ddfd25a..38d035ae2904 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev, =20 device =3D &aux_dev->dev; =20 - dev =3D mei_me_dev_init(device, cfg); + dev =3D mei_me_dev_init(device, cfg, adev->slow_fw); if (IS_ERR(dev)) { ret =3D PTR_ERR(dev); goto err; diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c index cebcca6d6d3e..4ff4dbfd07c0 100644 --- a/drivers/misc/mei/hbm.c +++ b/drivers/misc/mei/hbm.c @@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev) mutex_unlock(&dev->device_lock); ret =3D wait_event_timeout(dev->wait_hbm_start, dev->hbm_state !=3D MEI_HBM_STARTING, - mei_secs_to_jiffies(MEI_HBM_TIMEOUT)); + dev->timeouts.hbm); mutex_lock(&dev->device_lock); =20 if (ret =3D=3D 0 && (dev->hbm_state <=3D MEI_HBM_STARTING)) { @@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev) } =20 dev->hbm_state =3D MEI_HBM_STARTING; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev) } =20 dev->hbm_state =3D MEI_HBM_DR_SETUP; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *= dev) } =20 dev->hbm_state =3D MEI_HBM_CAP_SETUP; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *= dev) return ret; } dev->hbm_state =3D MEI_HBM_ENUM_CLIENTS; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, uns= igned long start_idx) return ret; } =20 - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); =20 return 0; diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 959b3329af60..93d8b6dcedda 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev) mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, - mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); + dev->timeouts.hw_ready); mutex_lock(&dev->device_lock); if (!dev->recvd_hw_ready) { dev_err(dev->dev, "wait hw ready failed\n"); @@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev) static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; =20 dev->pg_event =3D MEI_PG_EVENT_WAIT; @@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_devic= e *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED) { @@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_devic= e *dev) static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED) @@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device= *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 reply: @@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device= *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED) @@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev) static int mei_me_d0i3_enter_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long d0i3_timeout =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); - unsigned long pgi_timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; u32 reg; =20 @@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *de= v) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, pgi_timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_RECEIVED) { @@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *de= v) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.d0i3); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_INTR_RECEIVED) { @@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev) static int mei_me_d0i3_exit_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); int ret; u32 reg; =20 @@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *d= ev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_INTR_RECEIVED) { @@ -1684,11 +1685,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg); * * @parent: device associated with physical device (pci/platform) * @cfg: per device generation config + * @slow_fw: configure longer timeouts as FW is slow * * Return: The mei_device pointer on success, NULL on failure. */ struct mei_device *mei_me_dev_init(struct device *parent, - const struct mei_cfg *cfg) + const struct mei_cfg *cfg, bool slow_fw) { struct mei_device *dev; struct mei_me_hw *hw; @@ -1703,7 +1705,7 @@ struct mei_device *mei_me_dev_init(struct device *par= ent, for (i =3D 0; i < DMA_DSCR_NUM; i++) dev->dr_dscr[i].size =3D cfg->dma_size[i]; =20 - mei_device_init(dev, parent, &mei_me_hw_ops); + mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops); hw->cfg =3D cfg; =20 dev->fw_f_fw_ver_supported =3D cfg->fw_ver_supported; diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index ca09274ac299..0e9d90808bcf 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -131,7 +131,7 @@ enum mei_cfg_idx { const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); =20 struct mei_device *mei_me_dev_init(struct device *parent, - const struct mei_cfg *cfg); + const struct mei_cfg *cfg, bool slow_fw); =20 int mei_me_pg_enter_sync(struct mei_device *dev); int mei_me_pg_exit_sync(struct mei_device *dev); diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c index 00652c137cc7..fccfa806bd63 100644 --- a/drivers/misc/mei/hw-txe.c +++ b/drivers/misc/mei/hw-txe.c @@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *p= dev) if (!dev) return NULL; =20 - mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); + mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops); =20 hw =3D to_txe_hw(dev); =20 diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h index b46077b17114..9381e5c13b4f 100644 --- a/drivers/misc/mei/hw.h +++ b/drivers/misc/mei/hw.h @@ -16,11 +16,16 @@ #define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */ =20 #define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */ +#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slo= w FW */ #define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout= */ =20 #define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec= */ #define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time= */ #define MEI_HBM_TIMEOUT 1 /* 1 second */ +#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */ + +#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */ +#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */ =20 /* * FW page size for DMA allocations diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index 5bb6ba662cc0..ce030a882d0c 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev) EXPORT_SYMBOL_GPL(mei_write_is_idle); =20 /** - * mei_device_init -- initialize mei_device structure + * mei_device_init - initialize mei_device structure * * @dev: the mei device * @device: the device structure + * @slow_fw: configure longer timeouts as FW is slow * @hw_ops: hw operations */ void mei_device_init(struct mei_device *dev, struct device *device, + bool slow_fw, const struct mei_hw_ops *hw_ops) { /* setup our list array */ @@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev, dev->pg_event =3D MEI_PG_EVENT_IDLE; dev->ops =3D hw_ops; dev->dev =3D device; + + dev->timeouts.hw_ready =3D mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT); + dev->timeouts.connect =3D MEI_CONNECT_TIMEOUT; + dev->timeouts.client_init =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->timeouts.pgi =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); + dev->timeouts.d0i3 =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); + if (slow_fw) { + dev->timeouts.cl_connect =3D mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_= SLOW); + dev->timeouts.hbm =3D mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW); + dev->timeouts.mkhi_recv =3D msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW); + } else { + dev->timeouts.cl_connect =3D mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT); + dev->timeouts.hbm =3D mei_secs_to_jiffies(MEI_HBM_TIMEOUT); + dev->timeouts.mkhi_recv =3D msecs_to_jiffies(MKHI_RCV_TIMEOUT); + } } EXPORT_SYMBOL_GPL(mei_device_init); =20 diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c index 786f7c8f7f61..261939b945ef 100644 --- a/drivers/misc/mei/main.c +++ b/drivers/misc/mei/main.c @@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file, cl->state =3D=3D MEI_FILE_DISCONNECTED || cl->state =3D=3D MEI_FILE_DISCONNECT_REQUIRED || cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); } =20 diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 694f866f87ef..16f59b3a45fc 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -415,6 +415,17 @@ struct mei_fw_version { =20 #define MEI_MAX_FW_VER_BLOCKS 3 =20 +struct mei_dev_timeouts { + unsigned long hw_ready; /* Timeout on ready message, in jiffies */ + int connect; /* HPS: at least 2 seconds, in seconds */ + unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */ + int client_init; /* HPS: Clients Enumeration Timeout, in seconds */ + unsigned long pgi; /* PG Isolation time response, in jiffies */ + unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */ + unsigned long hbm; /* HBM operation timeout, in jiffies */ + unsigned long mkhi_recv; /* receive timeout, in jiffies */ +}; + /** * struct mei_device - MEI private device struct * @@ -480,6 +491,8 @@ struct mei_fw_version { * @allow_fixed_address: allow user space to connect a fixed client * @override_fixed_address: force allow fixed address behavior * + * @timeouts: actual timeout values + * * @reset_work : work item for the device reset * @bus_rescan_work : work item for the bus rescan * @@ -568,6 +581,8 @@ struct mei_device { bool allow_fixed_address; bool override_fixed_address; =20 + struct mei_dev_timeouts timeouts; + struct work_struct reset_work; struct work_struct bus_rescan_work; =20 @@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots) */ void mei_device_init(struct mei_device *dev, struct device *device, + bool slow_fw, const struct mei_hw_ops *hw_ops); int mei_reset(struct mei_device *dev); int mei_start(struct mei_device *dev); diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c index 33e58821e478..0288784f8ffd 100644 --- a/drivers/misc/mei/pci-me.c +++ b/drivers/misc/mei/pci-me.c @@ -201,7 +201,7 @@ static int mei_me_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) } =20 /* allocates and initializes the mei dev structure */ - dev =3D mei_me_dev_init(&pdev->dev, cfg); + dev =3D mei_me_dev_init(&pdev->dev, cfg, false); if (!dev) { err =3D -ENOMEM; goto end; --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C5B9C433EF for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293644" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293644" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:28 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041197" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:17 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/20] drm/i915/dg2: add gsc with special gsc bar offsets Date: Thu, 7 Apr 2022 15:58:33 +0300 Message-Id: <20220407125839.1479249-15-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler DG2 uses different GSC offsets on memory bar and uses PXP head (HECI1). Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index ffe6716590f0..bfc307e49bf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -69,6 +69,19 @@ static const struct gsc_def gsc_def_xehpsdv[] =3D { } }; =20 +static const struct gsc_def gsc_def_dg2[] =3D { + { + .name =3D "mei-gsc", + .bar =3D DG2_GSC_HECI1_BASE, + .bar_size =3D GSC_BAR_LENGTH, + }, + { + .name =3D "mei-gscfi", + .bar =3D DG2_GSC_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + } +}; + static void gsc_release_dev(struct device *dev) { struct auxiliary_device *aux_dev =3D to_auxiliary_dev(dev); @@ -109,6 +122,8 @@ static void gsc_init_one(struct drm_i915_private *i915, def =3D &gsc_def_dg1[intf_id]; } else if (IS_XEHPSDV(i915)) { def =3D &gsc_def_xehpsdv[intf_id]; + } else if (IS_DG2(i915)) { + def =3D &gsc_def_dg2[intf_id]; } else { drm_warn_once(&i915->drm, "Unknown platform\n"); return; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pc= i.c index 06e6dad0d7f7..cb6dcc3f48f4 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1051,6 +1051,7 @@ static const struct intel_device_info xehpsdv_info = =3D { .has_4tile =3D 1, \ .has_64k_pages =3D 1, \ .has_guc_deprivilege =3D 1, \ + .has_heci_pxp =3D 1, \ .needs_compact_pt =3D 1, \ .platform_engine_mask =3D \ BIT(RCS0) | BIT(BCS0) | \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index 1dd7b7de6002..efcfe32cd8eb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -978,6 +978,8 @@ #define BLT_RING_BASE 0x22000 #define DG1_GSC_HECI1_BASE 0x00258000 #define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI1_BASE 0x00373000 +#define DG2_GSC_HECI2_BASE 0x00374000 =20 =20 =20 --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2419AC433EF for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293642" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293642" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:28 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041229" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:21 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/20] mei: bus: export common mkhi definitions into a separate header Date: Thu, 7 Apr 2022 15:58:34 +0300 Message-Id: <20220407125839.1479249-16-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Exported common mkhi definitions from bus-fixup.c into a separate header file mkhi.h for other driver usage. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/bus-fixup.c | 32 ++----------------------- drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 30 deletions(-) create mode 100644 drivers/misc/mei/mkhi.h diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 24e91a9ea558..190691abddc9 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -15,6 +15,7 @@ =20 #include "mei_dev.h" #include "client.h" +#include "mkhi.h" =20 #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \ 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06) @@ -80,6 +81,7 @@ static void whitelist(struct mei_cl_device *cldev) } =20 #define OSTYPE_LINUX 2 + struct mei_os_ver { __le16 build; __le16 reserved1; @@ -89,20 +91,6 @@ struct mei_os_ver { u8 reserved2; } __packed; =20 -#define MKHI_FEATURE_PTT 0x10 - -struct mkhi_rule_id { - __le16 rule_type; - u8 feature_id; - u8 reserved; -} __packed; - -struct mkhi_fwcaps { - struct mkhi_rule_id id; - u8 len; - u8 data[]; -} __packed; - struct mkhi_fw_ver_block { u16 minor; u8 major; @@ -115,22 +103,6 @@ struct mkhi_fw_ver { struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS]; } __packed; =20 -#define MKHI_FWCAPS_GROUP_ID 0x3 -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 -#define MKHI_GEN_GROUP_ID 0xFF -#define MKHI_GEN_GET_FW_VERSION_CMD 0x2 -struct mkhi_msg_hdr { - u8 group_id; - u8 command; - u8 reserved; - u8 result; -} __packed; - -struct mkhi_msg { - struct mkhi_msg_hdr hdr; - u8 data[]; -} __packed; - #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \ sizeof(struct mkhi_fwcaps) + \ sizeof(struct mei_os_ver)) diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h new file mode 100644 index 000000000000..27a9b476904e --- /dev/null +++ b/drivers/misc/mei/mkhi.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Intel Management Engine Interface (Intel MEI) Linux driver + */ + +#ifndef _MEI_MKHI_H_ +#define _MEI_MKHI_H_ + +#include "mei_dev.h" + +#define MKHI_FEATURE_PTT 0x10 + +#define MKHI_FWCAPS_GROUP_ID 0x3 +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 +#define MKHI_GEN_GROUP_ID 0xFF +#define MKHI_GEN_GET_FW_VERSION_CMD 0x2 + +#define MCHI_GROUP_ID 0xA + +struct mkhi_rule_id { + __le16 rule_type; + u8 feature_id; + u8 reserved; +} __packed; + +struct mkhi_fwcaps { + struct mkhi_rule_id id; + u8 len; + u8 data[]; +} __packed; + +struct mkhi_msg_hdr { + u8 group_id; + u8 command; + u8 reserved; + u8 result; +} __packed; + +struct mkhi_msg { + struct mkhi_msg_hdr hdr; + u8 data[]; +} __packed; + +#endif /* _MEI_MKHI_H_ */ --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0E35C433F5 for ; Thu, 7 Apr 2022 13:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245696AbiDGNEX (ORCPT ); Thu, 7 Apr 2022 09:04:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245719AbiDGNCg (ORCPT ); Thu, 7 Apr 2022 09:02:36 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 851511AF7C9 for ; Thu, 7 Apr 2022 06:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336436; x=1680872436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FqQD8V1tZDNnF7Zs/RsGtMzs5YtWuA1/y2GnU/ZA+R8=; b=dnOncD7KhXsH1cr9w8ke8iAuC+R3x15z2VGwwyuCK5CWW4y8ekdxxjt8 Qlz6gvhlB/ZYldDm0WFOKFGqHEePhHHgzopzvIWQR2ny8wKuC2hJstT6x izrQsBH/uW9JAPzWqXZQrNGbvTXZY0S30drxLblJQ5QdUI9jHud6cK/nE cz8F4q20NiQc/Y+LryneWVMopUXiCGKcaVrQI0ogr2rYCHBVlItThCLz2 sF8mHAEJdij/3lw3Ua0hSFIy6fdn5Pkqhta8pzsaxh96Q2DDspAaYRz3y 321WKsQXjDdtUPoJwNEovGVccrUunC3eLl3DELFpDbQGQtyrnJg9jTD0J Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293651" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293651" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:29 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041242" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:25 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 16/20] mei: mkhi: add memory ready command Date: Thu, 7 Apr 2022 15:58:35 +0300 Message-Id: <20220407125839.1479249-17-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler Add GSC memory ready command. The command indicates to the firmware that extend operation memory was setup and the firmware may enter PXP mode. CC: Daniele Ceraolo Spurio Signed-off-by: Tomas Winkler --- drivers/misc/mei/mkhi.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h index 27a9b476904e..ea9fe487cb0f 100644 --- a/drivers/misc/mei/mkhi.h +++ b/drivers/misc/mei/mkhi.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2021, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -18,6 +18,13 @@ =20 #define MCHI_GROUP_ID 0xA =20 +#define MKHI_GROUP_ID_GFX 0x30 +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0 +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1 + +/* Allow transition to PXP mode without approval */ +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1 + struct mkhi_rule_id { __le16 rule_type; u8 feature_id; @@ -42,4 +49,9 @@ struct mkhi_msg { u8 data[]; } __packed; =20 +struct mkhi_gfx_mem_ready { + struct mkhi_msg_hdr hdr; + uint32_t flags; +} __packed; + #endif /* _MEI_MKHI_H_ */ --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC0BC433EF for ; Thu, 7 Apr 2022 13:02:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343533AbiDGNEw (ORCPT ); Thu, 7 Apr 2022 09:04:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245727AbiDGNCj (ORCPT ); Thu, 7 Apr 2022 09:02:39 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F0341B931F for ; Thu, 7 Apr 2022 06:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336439; x=1680872439; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ds6mcmDptUyWkh8bjJkuqA30cxbloOaQu7qcIggaNIo=; b=m7cBaGTdzu4JBnic7ZjLNrhrFym6wKItHiQRets8L/tv1a9l4WiQpNf/ YsC53mex5HhL78gySwRTJp/r/OEcpZYcGRzv65UTnI+p/U/zHJUnS39zY 551zc5CkN7Ih0zJ56XaR7olweTz4Lh5RV3nM1v4Yb88ts+FslZYmO+m+h jb930GX8kZfsMdHVmE7cTbJfTY0JxcAQEX/Xaiyo5Qeivfhw9sqdjtv39 8vvVfwwL7HT3GCWTHeYWg0+070c1b21pR98AsYjqAOqbLthA6owv/rZza IRJQwYHjKCWvbWCu71W+L8zb8j2VbEq1OWgjbXQMcGwjboOjmOFgK/zpp g==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293676" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293676" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:33 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041289" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:29 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 17/20] mei: gsc: setup gsc extended operational memory Date: Thu, 7 Apr 2022 15:58:36 +0300 Message-Id: <20220407125839.1479249-18-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler 1. Retrieve extended operational memory physical pointers from the auxiliary device info. 2. Setup memory registers. 3. Notify firmware that the memory is ready by sending the memory ready command. 4. Disable PXP device if GSC is not in PXP mode. CC: Daniele Ceraolo Spurio Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++- drivers/misc/mei/gsc-me.c | 16 ++++++++ drivers/misc/mei/hw-me-regs.h | 7 ++++ drivers/misc/mei/hw-me.c | 28 +++++++++++++- drivers/misc/mei/mei_dev.h | 10 +++++ include/linux/mei_aux.h | 1 + 6 files changed, 129 insertions(+), 3 deletions(-) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 190691abddc9..d2929f68604d 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -189,6 +189,19 @@ static int mei_fwver(struct mei_cl_device *cldev) return ret; } =20 +static int mei_gfx_memory_ready(struct mei_cl_device *cldev) +{ + struct mkhi_gfx_mem_ready req =3D {0}; + unsigned int mode =3D MEI_CL_IO_TX_INTERNAL; + + req.hdr.group_id =3D MKHI_GROUP_ID_GFX; + req.hdr.command =3D MKHI_GFX_MEMORY_READY_CMD_REQ; + req.flags =3D MKHI_GFX_MEM_READY_PXP_ALLOWED; + + dev_dbg(&cldev->dev, "Sending memory ready command\n"); + return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode); +} + static void mei_mkhi_fix(struct mei_cl_device *cldev) { int ret; @@ -235,6 +248,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cld= ev) dev_err(&cldev->dev, "FW version command failed %d\n", ret); mei_cldev_disable(cldev); } + +static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev) +{ + int ret; + + /* No need to enable the client if nothing is needed from it */ + if (!cldev->bus->fw_f_fw_ver_supported && + (cldev->bus->pxp_mode !=3D MEI_DEV_PXP_INIT)) + return; + + ret =3D mei_cldev_enable(cldev); + if (ret) + return; + + if (cldev->bus->pxp_mode =3D=3D MEI_DEV_PXP_INIT) { + ret =3D mei_gfx_memory_ready(cldev); + if (ret < 0) + dev_err(&cldev->dev, "memory ready command failed %d\n", ret); + else + dev_dbg(&cldev->dev, "memory ready command sent\n"); + /* we go to reset after that */ + cldev->bus->pxp_mode =3D MEI_DEV_PXP_SETUP; + goto out; + } + + ret =3D mei_fwver(cldev); + if (ret < 0) + dev_err(&cldev->dev, "FW version command failed %d\n", + ret); +out: + mei_cldev_disable(cldev); +} + /** * mei_wd - wd client on the bus, change protocol version * as the API has changed. @@ -474,6 +520,26 @@ static void vt_support(struct mei_cl_device *cldev) cldev->do_match =3D 1; } =20 +/** + * pxp_isready - enable bus client if pxp is ready + * + * @cldev: me clients device + */ +static void pxp_isready(struct mei_cl_device *cldev) +{ + struct mei_device *bus =3D cldev->bus; + + switch (bus->pxp_mode) { + case MEI_DEV_PXP_READY: + case MEI_DEV_PXP_DEFAULT: + cldev->do_match =3D 1; + break; + default: + cldev->do_match =3D 0; + break; + } +} + #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook } =20 static struct mei_fixup { @@ -487,10 +553,10 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), - MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), - MEI_FIXUP(MEI_UUID_PAVP, whitelist), + MEI_FIXUP(MEI_UUID_PAVP, pxp_isready), }; =20 /** diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 38d035ae2904..fc9419054290 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev= , int where, u32 *val) return 0; } =20 +static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct reso= urce *mem) +{ + u32 low =3D lower_32_bits(mem->start); + u32 hi =3D upper_32_bits(mem->start); + u32 limit =3D (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID; + + iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG); + iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG); + iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG); +} + static int mei_gsc_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *aux_dev_id) { @@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_de= v, =20 dev_set_drvdata(device, dev); =20 + if (adev->ext_op_mem.start) { + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem); + dev->pxp_mode =3D MEI_DEV_PXP_INIT; + } + /* use polling */ if (mei_me_hw_use_polling(hw)) { mei_disable_interrupts(dev); diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h index 64ce3f830262..8bbe3e9f1269 100644 --- a/drivers/misc/mei/hw-me-regs.h +++ b/drivers/misc/mei/hw-me-regs.h @@ -125,6 +125,8 @@ # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 #define PCI_CFG_HFS_4 0x64 #define PCI_CFG_HFS_5 0x68 +# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003 +# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3 #define PCI_CFG_HFS_6 0x6C =20 /* MEI registers */ @@ -141,6 +143,11 @@ /* H_D0I3C - D0I3 Control */ #define H_D0I3C 0x800 =20 +#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100 +#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104 +#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108 +#define GSC_EXT_OP_MEM_VALID BIT(31) + /* register bits of H_CSR (Host Control Status register) */ /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ #define H_CBD 0xFF000000 diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 93d8b6dcedda..b70a36021fc4 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *= dev) return (mecsr & ME_RST_HRA) =3D=3D ME_RST_HRA; } =20 +/** + * mei_gsc_pxp_check - check for gsc firmware entering pxp mode + * + * @dev: the device structure + */ +static void mei_gsc_pxp_check(struct mei_device *dev) +{ + struct mei_me_hw *hw =3D to_me_hw(dev); + u32 fwsts5 =3D 0; + + if (dev->pxp_mode =3D=3D MEI_DEV_PXP_DEFAULT) + return; + + hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5); + trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5); + if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) =3D=3D GSC_CFG_HFS_5_BOOT_TYPE= _PXP) { + dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5); + dev->pxp_mode =3D MEI_DEV_PXP_READY; + } else { + dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5); + } +} + /** * mei_me_hw_ready_wait - wait until the me(hw) has turned ready * or timeout is reached @@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev) return -ETIME; } =20 + mei_gsc_pxp_check(dev); + mei_me_hw_reset_release(dev); dev->recvd_hw_ready =3D false; return 0; @@ -1268,7 +1293,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *= dev_id) =20 /* check if ME wants a reset */ if (!mei_hw_is_ready(dev) && dev->dev_state !=3D MEI_DEV_RESETTING) { - dev_warn(dev->dev, "FW not ready: resetting.\n"); + dev_warn(dev->dev, "FW not ready: resetting: dev_state =3D %d pxp =3D %d= \n", + dev->dev_state, dev->pxp_mode); if (dev->dev_state =3D=3D MEI_DEV_POWERING_DOWN || dev->dev_state =3D=3D MEI_DEV_POWER_DOWN) mei_cl_all_disconnect(dev); diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 16f59b3a45fc..7c508bca9a00 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -62,6 +62,14 @@ enum mei_dev_state { MEI_DEV_POWER_UP }; =20 +/* MEI PXP mode state */ +enum mei_dev_pxp_mode { + MEI_DEV_PXP_DEFAULT =3D 0, + MEI_DEV_PXP_INIT =3D 1, + MEI_DEV_PXP_SETUP =3D 2, + MEI_DEV_PXP_READY =3D 3, +}; + const char *mei_dev_state_str(int state); =20 enum mei_file_transaction_states { @@ -454,6 +462,7 @@ struct mei_dev_timeouts { * @reset_count : number of consecutive resets * @dev_state : device state * @hbm_state : state of host bus message protocol + * @pxp_mode : PXP device mode * @init_clients_timer : HBM init handshake timeout * * @pg_event : power gating event @@ -537,6 +546,7 @@ struct mei_device { unsigned long reset_count; enum mei_dev_state dev_state; enum mei_hbm_state hbm_state; + enum mei_dev_pxp_mode pxp_mode; u16 init_clients_timer; =20 /* diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index a29f4064b9c0..c3fc137a2aba 100644 --- a/include/linux/mei_aux.h +++ b/include/linux/mei_aux.h @@ -11,6 +11,7 @@ struct mei_aux_device { struct auxiliary_device aux_dev; int irq; struct resource bar; + struct resource ext_op_mem; bool slow_fw; }; =20 --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05DD3C433FE for ; Thu, 7 Apr 2022 13:02:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343530AbiDGNEo (ORCPT ); Thu, 7 Apr 2022 09:04:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245730AbiDGNCk (ORCPT ); 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07 Apr 2022 06:00:36 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041312" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:33 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio Subject: [PATCH 18/20] mei: gsc: add transition to PXP mode in resume flow Date: Thu, 7 Apr 2022 15:58:37 +0300 Message-Id: <20220407125839.1479249-19-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Added transition to PXP mode in resume flow. CC: Daniele Ceraolo Spurio Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/gsc-me.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index fc9419054290..d75fce49e4f7 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct d= evice *device) static int __maybe_unused mei_gsc_pm_resume(struct device *device) { struct mei_device *dev =3D dev_get_drvdata(device); + struct auxiliary_device *aux_dev; + struct mei_aux_device *adev; int err; + struct mei_me_hw *hw; =20 if (!dev) return -ENODEV; =20 + hw =3D to_me_hw(dev); + aux_dev =3D to_auxiliary_dev(device); + adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + if (adev->ext_op_mem.start) { + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem); + dev->pxp_mode =3D MEI_DEV_PXP_INIT; + } + err =3D mei_restart(dev); if (err) return err; --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EF34C433F5 for ; Thu, 7 Apr 2022 13:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245756AbiDGNE4 (ORCPT ); Thu, 7 Apr 2022 09:04:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245735AbiDGNCl (ORCPT ); Thu, 7 Apr 2022 09:02:41 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C77F1BA45B for ; Thu, 7 Apr 2022 06:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336442; x=1680872442; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Olr/UAxz6mOZ13vGKwY6QrXads5Ij3YBYs7osIbTZXI=; b=YY3+JT0GzaSUGvC+HzDly/dzyLA8BL++LkVssBSgnnCCe49lOQkUZpD1 Yg5s3M/StPsBAp6x9mU9crAiSOq7yCKxLTCeMC12IU+SpTAvT7xtrGRrG XtOOmIBTlo/ENlOq+xEjHVUMYiqthp9WUVyHytAVl9/TaymM55Fg9HwTu Z9Yc9dTNirKjXhXjZJnW4iL0sW2v4GGcGZRar9Lire3+Bs5v/Z+aTrRPK egn8tp6+xipHB3pidmbAP1YS+t4lsvCEheL9bBu9EjoIOqRZH2KZj0qlv A1t6HMvqskjgP5Z36CzaLBa35roh/WSTqEd2k/H+dCRwKext/PL75QESy g==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293724" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293724" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:40 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041344" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:36 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/20] mei: debugfs: add pxp mode to devstate in debugfs Date: Thu, 7 Apr 2022 15:58:38 +0300 Message-Id: <20220407125839.1479249-20-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler CC: Vitaly Lubart Signed-off-by: Tomas Winkler --- drivers/misc/mei/debugfs.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c index 1ce61e9e24fc..4074fec866a6 100644 --- a/drivers/misc/mei/debugfs.c +++ b/drivers/misc/mei/debugfs.c @@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, voi= d *unused) } DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active); =20 +static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state) +{ +#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state + switch (state) { + MEI_PXP_MODE(DEFAULT); + MEI_PXP_MODE(INIT); + MEI_PXP_MODE(SETUP); + MEI_PXP_MODE(READY); + default: + return "unknown"; + } +#undef MEI_PXP_MODE +} + static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused) { struct mei_device *dev =3D m->private; @@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, = void *unused) seq_printf(m, "pg: %s, %s\n", mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED", mei_pg_state_str(mei_pg_state(dev))); + + seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode)); + return 0; } DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate); --=20 2.32.0 From nobody Thu May 14 07:08:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE6A9C433EF for ; Thu, 7 Apr 2022 13:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343575AbiDGNFC (ORCPT ); Thu, 7 Apr 2022 09:05:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245742AbiDGNCo (ORCPT ); Thu, 7 Apr 2022 09:02:44 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C8FF1BB7A7 for ; Thu, 7 Apr 2022 06:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649336444; x=1680872444; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HxcK3Y9CYtajuNDTLIHEUDdKJgVEo2P2iuRGDnGLJJM=; b=TWlVtJqW3FHP5VKZPF6/tZvHlSHQHbgStR2/8w6OjpyxhEIum6rZ4Hyp ZnmTzb407whxvERqUk7D+sWXhtSmm6tnaoZao+zT0llTUjKeuG3eFSWXe qhZH08xC2rtYl0uNt0Md7pULpXOs8IXT6Fk+dvmAGLDreeHwL4VgG9X7j L0O7OhRGdtvKgeQSEqVlU4xdJLfwHADKGG5+z0GFhjGmOZY5bakuQ06G4 GSCLaE5VUKNak3sMDIKRXJzdOYMlUM7jdD/LFM5YtQ/jJDw7Tt6ShOuLl EhItbTlMJsFA5xh95iyiBvslwp69iSHkyhytetdNwsx/pyVMFYt5exlN8 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10309"; a="286293752" X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="286293752" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:44 -0700 X-IronPort-AV: E=Sophos;i="5.90,242,1643702400"; d="scan'208";a="571041388" Received: from sannilnx.jer.intel.com ([10.12.231.73]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2022 06:00:40 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Daniele Ceraolo Spurio , Alan Previn Subject: [PATCH 20/20] drm/i915/gsc: allocate extended operational memory in LMEM Date: Thu, 7 Apr 2022 15:58:39 +0300 Message-Id: <20220407125839.1479249-21-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220407125839.1479249-1-alexander.usyskin@intel.com> References: <20220407125839.1479249-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tomas Winkler GSC requires more operational memory than available on chip. Reserve 4M of LMEM for GSC operation. The memory is provided to the GSC as struct resource to the auxiliary data of the child device. Signed-off-by: Tomas Winkler Signed-off-by: Daniele Ceraolo Spurio Cc: Alan Previn --- drivers/gpu/drm/i915/gt/intel_gsc.c | 92 ++++++++++++++++++++++++++--- drivers/gpu/drm/i915/gt/intel_gsc.h | 3 + 2 files changed, 88 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index bfc307e49bf9..4d87519d5773 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -7,6 +7,7 @@ #include #include "i915_drv.h" #include "i915_reg.h" +#include "gem/i915_gem_region.h" #include "gt/intel_gsc.h" #include "gt/intel_gt.h" =20 @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq) return irq_set_chip_data(irq, NULL); } =20 +static int +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_= t size) +{ + struct intel_gt *gt =3D gsc_to_gt(gsc); + struct drm_i915_gem_object *obj; + void *vaddr; + int err; + + obj =3D i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGU= OUS); + if (IS_ERR(obj)) { + drm_err(>->i915->drm, "Failed to allocate gsc memory\n"); + return PTR_ERR(obj); + } + + err =3D i915_gem_object_pin_pages_unlocked(obj); + if (err) { + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n"); + goto out_put; + } + + vaddr =3D i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt= ->i915, obj, true)); + if (IS_ERR(vaddr)) { + err =3D PTR_ERR(vaddr); + drm_err(>->i915->drm, "Failed to map gsc memory\n"); + goto out_unpin; + } + + memset(vaddr, 0, obj->base.size); + + i915_gem_object_unpin_map(obj); + + intf->gem_obj =3D obj; + + return 0; + +out_unpin: + i915_gem_object_unpin_pages(obj); +out_put: + i915_gem_object_put(obj); + return err; +} + +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf) +{ + struct drm_i915_gem_object *obj =3D fetch_and_zero(&intf->gem_obj); + + if (!obj) + return; + + if (i915_gem_object_has_pinned_pages(obj)) + i915_gem_object_unpin_pages(obj); + + i915_gem_object_put(obj); +} + struct gsc_def { const char *name; unsigned long bar; size_t bar_size; bool use_polling; bool slow_fw; + size_t lmem_size; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] =3D { .name =3D "mei-gsc", .bar =3D DG2_GSC_HECI1_BASE, .bar_size =3D GSC_BAR_LENGTH, + .lmem_size =3D SZ_4M, }, { .name =3D "mei-gscfi", @@ -90,26 +148,33 @@ static void gsc_release_dev(struct device *dev) kfree(adev); } =20 -static void gsc_destroy_one(struct intel_gsc_intf *intf) +static void gsc_destroy_one(struct drm_i915_private *i915, + struct intel_gsc *gsc, unsigned int intf_id) { + struct intel_gsc_intf *intf =3D &gsc->intf[intf_id]; + if (intf->adev) { auxiliary_device_delete(&intf->adev->aux_dev); auxiliary_device_uninit(&intf->adev->aux_dev); intf->adev =3D NULL; } + if (intf->irq >=3D 0) irq_free_desc(intf->irq); intf->irq =3D -1; + + gsc_ext_om_destroy(intf); } =20 static void gsc_init_one(struct drm_i915_private *i915, - struct intel_gsc_intf *intf, - unsigned int intf_id) + struct intel_gsc *gsc, + unsigned int intf_id) { struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); struct mei_aux_device *adev; struct auxiliary_device *aux_dev; const struct gsc_def *def; + struct intel_gsc_intf *intf =3D &gsc->intf[intf_id]; int ret; =20 intf->irq =3D -1; @@ -141,7 +206,7 @@ static void gsc_init_one(struct drm_i915_private *i915, intf->irq =3D irq_alloc_desc(0); if (intf->irq < 0) { drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); - return; + goto fail; } =20 ret =3D gsc_irq_init(intf->irq); @@ -155,6 +220,19 @@ static void gsc_init_one(struct drm_i915_private *i915, if (!adev) goto fail; =20 + if (def->lmem_size) { + dev_dbg(&pdev->dev, "setting up GSC lmem\n"); + + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) { + dev_err(&pdev->dev, "setting up gsc extended operational memory failed\= n"); + kfree(adev); + goto fail; + } + + adev->ext_op_mem.start =3D i915_gem_object_get_dma_address(intf->gem_obj= , 0); + adev->ext_op_mem.end =3D adev->ext_op_mem.start + def->lmem_size; + } + adev->irq =3D intf->irq; adev->bar.parent =3D &pdev->resource[0]; adev->bar.start =3D def->bar + pdev->resource[0].start; @@ -188,7 +266,7 @@ static void gsc_init_one(struct drm_i915_private *i915, =20 return; fail: - gsc_destroy_one(intf); + gsc_destroy_one(i915, gsc, intf->id); } =20 static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id) @@ -229,7 +307,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i= 915_private *i915) return; =20 for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) - gsc_init_one(i915, &gsc->intf[i], i); + gsc_init_one(i915, gsc, i); } =20 void intel_gsc_fini(struct intel_gsc *gsc) @@ -241,5 +319,5 @@ void intel_gsc_fini(struct intel_gsc *gsc) return; =20 for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) - gsc_destroy_one(&gsc->intf[i]); + gsc_destroy_one(gt->i915, gsc, i); } diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/= intel_gsc.h index 68582f912b21..fcac1775e9c3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.h +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h @@ -20,11 +20,14 @@ struct mei_aux_device; =20 /** * struct intel_gsc - graphics security controller + * + * @gem_obj: scratch memory GSC operations * @intf : gsc interface */ struct intel_gsc { struct intel_gsc_intf { struct mei_aux_device *adev; + struct drm_i915_gem_object *gem_obj; int irq; unsigned int id; } intf[INTEL_GSC_NUM_INTERFACES]; --=20 2.32.0