From nobody Fri Jun 19 08:29:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22400C43217 for ; Wed, 6 Apr 2022 00:17:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1582796AbiDEXtp (ORCPT ); Tue, 5 Apr 2022 19:49:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573271AbiDESlF (ORCPT ); Tue, 5 Apr 2022 14:41:05 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D77622124B for ; Tue, 5 Apr 2022 11:39:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 443B1616C5 for ; Tue, 5 Apr 2022 18:39:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A454C385A3; Tue, 5 Apr 2022 18:39:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649183944; bh=v+twvuAPSyK4b9502wrkUr1BlR4MnKo9qztL8KChOdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pv/LoVtXOikiDXbs7bvRbuyDMtSYWg3kDLXSm5gSlnXCaEDv8ryyXjbIGSmiISwCQ wyDN7BH5runsczVlOX1mNta4Ix1KXHlnwYSTfbvSChDhmoCtqbWI/rC6JkcF30GxzB vewmoNYu8MPfREU7T8OFmhmpXRBDRyzYocN5V8D0CJ7EkS6/VrD9gcxqhEMK6tUJIb pbT8gvjm3hS2sDVrm6MG4Mpgryubw25r2KH9VquuPGTDM1WP1paP5DiukvMJskpGxR UenfyqZD+PyIRpqNBCM5nGzl9UfCzmD/yVMXA1/82JZhkTft9bMEj95fk+ZrP/tm3w hsY3Qx5PU4bXg== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nbo50-001tkq-8e; Tue, 05 Apr 2022 19:39:02 +0100 From: Marc Zyngier To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Andre Przywara , Thomas Gleixner , Eric Auger Subject: [PATCH v2 1/3] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Date: Tue, 5 Apr 2022 19:38:55 +0100 Message-Id: <20220405183857.205960-2-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220405183857.205960-1-maz@kernel.org> References: <20220405183857.205960-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, andre.przywara@arm.com, tglx@linutronix.de, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As we're about to expose GICR_CTLR.{IR,CES} to guests, populate the include file with the architectural values. Signed-off-by: Marc Zyngier --- include/linux/irqchip/arm-gic-v3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm= -gic-v3.h index 12d91f0dedf9..728691365464 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -127,6 +127,8 @@ #define GICR_PIDR2 GICD_PIDR2 =20 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_CES (1UL << 1) +#define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) =20 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) --=20 2.34.1 From nobody Fri Jun 19 08:29:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7725DC4321E for ; Wed, 6 Apr 2022 00:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1838734AbiDFA4h (ORCPT ); Tue, 5 Apr 2022 20:56:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573269AbiDESlE (ORCPT ); Tue, 5 Apr 2022 14:41:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9848B20BEF for ; Tue, 5 Apr 2022 11:39:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 34DC3618D9 for ; Tue, 5 Apr 2022 18:39:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BF6DC385A1; Tue, 5 Apr 2022 18:39:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649183944; bh=YINtmfTLrtIkESCqMaszau4vpZeKcCuTh9FLwNMrA9Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N4ia9nAZLyBw36K8gMDvcjYTjFJeMJB8dxuZ+h2NiUNDSRvtJAtuJpEFt6FVMB0il H3se+4jn2KzM6dycekuoXB2uV/pcCrsAeNESTlnrcvem82qc2o7TSLc/vOj/cjmdKb ib/a/iruIVYL3qZ45UT8kp6GhlUjprNi7RG/07e6S4hlWc9fLMU3ucJ3LacWOGHP5c sHFkc6j9oPSkcb2Z7ISJ237XBRv+X9myzzxuvhsHN8/d3HXpGGe+IVwcXb7KdHQt7S p1Cxm/KVGXYsgjZ4R0y4ITMUYWr2lU+PGzsyd+U77uP1YpydUDkd+vnh/ORIlVJdVr UlnHL9w1EoqHQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nbo50-001tkq-F6; Tue, 05 Apr 2022 19:39:02 +0100 From: Marc Zyngier To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Andre Przywara , Thomas Gleixner , Eric Auger Subject: [PATCH v2 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers Date: Tue, 5 Apr 2022 19:38:56 +0100 Message-Id: <20220405183857.205960-3-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220405183857.205960-1-maz@kernel.org> References: <20220405183857.205960-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, andre.przywara@arm.com, tglx@linutronix.de, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since GICv4.1, an implementation can offer the same MMIO-based implementation as DirectLPI, only with an ITS. Given that this can be hugely beneficial for workloads that are very LPI masking heavy (although these workloads are admitedly a bit odd). Interestingly, this is independent of RVPEI, which only *implies* the functionnality. So let's detect whether the implementation has GICR_CTLR.IR set, and propagate this as DirectLPI to the ITS driver. While we're at it, repaint the GICv3 banner so that we advertise the various capabilities at boot time to be slightly less invasive. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 0efe1a9a9f3b..4d8517232f1e 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -919,6 +919,7 @@ static int __gic_update_rdist_properties(struct redist_= region *region, void __iomem *ptr) { u64 typer =3D gic_read_typer(ptr + GICR_TYPER); + u32 ctlr =3D readl_relaxed(ptr + GICR_CTLR); =20 /* Boot-time cleanip */ if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) { @@ -938,9 +939,18 @@ static int __gic_update_rdist_properties(struct redist= _region *region, =20 gic_data.rdists.has_vlpis &=3D !!(typer & GICR_TYPER_VLPIS); =20 - /* RVPEID implies some form of DirectLPI, no matter what the doc says... = :-/ */ + /* + * TYPER.RVPEID implies some form of DirectLPI, no matter what the + * doc says... :-/ And CTLR.IR implies another subset of DirectLPI + * that the ITS driver can make use of for LPIs (and not VLPIs). + * + * These are 3 different ways to express the same thing, depending + * on the revision of the architecture and its relaxations over + * time. Just group them under the 'direct_lpi' banner. + */ gic_data.rdists.has_rvpeid &=3D !!(typer & GICR_TYPER_RVPEID); gic_data.rdists.has_direct_lpi &=3D (!!(typer & GICR_TYPER_DirectLPIS) | + !!(ctlr & GICR_CTLR_IR) | gic_data.rdists.has_rvpeid); gic_data.rdists.has_vpend_valid_dirty &=3D !!(typer & GICR_TYPER_DIRTY); =20 @@ -962,7 +972,11 @@ static void gic_update_rdist_properties(void) gic_iterate_rdists(__gic_update_rdist_properties); if (WARN_ON(gic_data.ppi_nr =3D=3D UINT_MAX)) gic_data.ppi_nr =3D 0; - pr_info("%d PPIs implemented\n", gic_data.ppi_nr); + pr_info("GICv3 features: %d PPIs%s%s\n", + gic_data.ppi_nr, + gic_data.has_rss ? ", RSS" : "", + gic_data.rdists.has_direct_lpi ? ", DirectLPI" : ""); +=09 if (gic_data.rdists.has_vlpis) pr_info("GICv4 features: %s%s%s\n", gic_data.rdists.has_direct_lpi ? "DirectLPI " : "", @@ -1797,8 +1811,6 @@ static int __init gic_init_bases(void __iomem *dist_b= ase, irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); =20 gic_data.has_rss =3D !!(typer & GICD_TYPER_RSS); - pr_info("Distributor has %sRange Selector support\n", - gic_data.has_rss ? "" : "no "); =20 if (typer & GICD_TYPER_MBIS) { err =3D mbi_init(handle, gic_data.domain); --=20 2.34.1 From nobody Fri Jun 19 08:29:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4498C43217 for ; Wed, 6 Apr 2022 02:07:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1846345AbiDFCD4 (ORCPT ); Tue, 5 Apr 2022 22:03:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573270AbiDESlE (ORCPT ); Tue, 5 Apr 2022 14:41:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A78C320F58 for ; Tue, 5 Apr 2022 11:39:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3EA42618DC for ; Tue, 5 Apr 2022 18:39:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9506CC385A5; Tue, 5 Apr 2022 18:39:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649183944; bh=Mf37t/W1q2zhLxqc/n4nwa3EUBb+kXfkqvJtsrPMcKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jnpevcrnJ2AGbRcedLVdF64TDhd8sWv1AVgExWfU4wjsrr1N6QwNKoTuDmLIl9H2e lP28dp6bsdL9ez+Jm4hzDbrxsHvElc4KuXIP1MNNDTvRpqHDANTEJP5CrnfYfsuZEI dOHBusJ+pofZUNCj9BckfFiOOaTtWQZMZoL+ncTm7AwGEVWHBNpwZb/5JSeUSkvJzl WWJJbvfpY3644p97Nsqqy4yPIEGTbe4xSFgHMRD28pvfQmNeH78jkC3Yci1Ee6faLP V5tIJcNHF8yl+CG5SGlgwP1pezkUSZdASyXbLB8S9W/+CS9kjtTVN9ORlOiM79XVoz cUl921gWrp1fA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nbo50-001tkq-KY; Tue, 05 Apr 2022 19:39:02 +0100 From: Marc Zyngier To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Andre Przywara , Thomas Gleixner , Eric Auger Subject: [PATCH v2 3/3] irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP Date: Tue, 5 Apr 2022 19:38:57 +0100 Message-Id: <20220405183857.205960-4-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220405183857.205960-1-maz@kernel.org> References: <20220405183857.205960-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, andre.przywara@arm.com, tglx@linutronix.de, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Recent work on the KVM GIC emulation has revealed that the GICv3 driver is a bit RWP-happy, as it polls this bit for each and every write MMIO access involving a single interrupt. As it turns out, polling RWP is only required when: - Disabling an SGI, PPI or SPI - Disabling LPIs at the redistributor level - Disabling groups - Enabling ARE - Dealing with DPG* Simplify the driver by removing all the other instances of RWP polling, and add the one that was missing when enabling the distributor (as that's where we set ARE). Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 38 +++++++++++++++++------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 4d8517232f1e..93cfd2b1efdd 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -352,28 +352,27 @@ static int gic_peek_irq(struct irq_data *d, u32 offse= t) =20 static void gic_poke_irq(struct irq_data *d, u32 offset) { - void (*rwp_wait)(void); void __iomem *base; u32 index, mask; =20 offset =3D convert_offset_index(d, offset, &index); mask =3D 1 << (index % 32); =20 - if (gic_irq_in_rdist(d)) { + if (gic_irq_in_rdist(d)) base =3D gic_data_rdist_sgi_base(); - rwp_wait =3D gic_redist_wait_for_rwp; - } else { + else base =3D gic_data.dist_base; - rwp_wait =3D gic_dist_wait_for_rwp; - } =20 writel_relaxed(mask, base + offset + (index / 32) * 4); - rwp_wait(); } =20 static void gic_mask_irq(struct irq_data *d) { gic_poke_irq(d, GICD_ICENABLER); + if (gic_irq_in_rdist(d)) + gic_redist_wait_for_rwp(); + else + gic_dist_wait_for_rwp(); } =20 static void gic_eoimode1_mask_irq(struct irq_data *d) @@ -420,7 +419,11 @@ static int gic_irq_set_irqchip_state(struct irq_data *= d, break; =20 case IRQCHIP_STATE_MASKED: - reg =3D val ? GICD_ICENABLER : GICD_ISENABLER; + if (val) { + gic_mask_irq(d); + return 0; + } + reg =3D GICD_ISENABLER; break; =20 default: @@ -574,7 +577,6 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) { enum gic_intid_range range; unsigned int irq =3D gic_irq(d); - void (*rwp_wait)(void); void __iomem *base; u32 offset, index; int ret; @@ -590,17 +592,14 @@ static int gic_set_type(struct irq_data *d, unsigned = int type) type !=3D IRQ_TYPE_LEVEL_HIGH && type !=3D IRQ_TYPE_EDGE_RISING) return -EINVAL; =20 - if (gic_irq_in_rdist(d)) { + if (gic_irq_in_rdist(d)) base =3D gic_data_rdist_sgi_base(); - rwp_wait =3D gic_redist_wait_for_rwp; - } else { + else base =3D gic_data.dist_base; - rwp_wait =3D gic_dist_wait_for_rwp; - } =20 offset =3D convert_offset_index(d, GICD_ICFGR, &index); =20 - ret =3D gic_configure_irq(index, type, base + offset, rwp_wait); + ret =3D gic_configure_irq(index, type, base + offset, NULL); if (ret && (range =3D=3D PPI_RANGE || range =3D=3D EPPI_RANGE)) { /* Misconfigured PPIs are usually not fatal */ pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); @@ -807,8 +806,8 @@ static void __init gic_dist_init(void) for (i =3D 0; i < GIC_ESPI_NR; i +=3D 4) writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); =20 - /* Now do the common stuff, and wait for the distributor to drain */ - gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); + /* Now do the common stuff */ + gic_dist_config(base, GIC_LINE_NR, NULL); =20 val =3D GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { @@ -816,8 +815,9 @@ static void __init gic_dist_init(void) val |=3D GICD_CTLR_nASSGIreq; } =20 - /* Enable distributor with ARE, Group1 */ + /* Enable distributor with ARE, Group1, and wait for it to drain */ writel_relaxed(val, base + GICD_CTLR); + gic_dist_wait_for_rwp(); =20 /* * Set all global interrupts to the boot CPU only. ARE must be @@ -1298,8 +1298,6 @@ static int gic_set_affinity(struct irq_data *d, const= struct cpumask *mask_val, */ if (enabled) gic_unmask_irq(d); - else - gic_dist_wait_for_rwp(); =20 irq_data_update_effective_affinity(d, cpumask_of(cpu)); =20 --=20 2.34.1