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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id c11-20020a056402120b00b004196059efd1sm6453247edw.75.2022.04.04.23.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Apr 2022 23:55:15 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2] dt-bindings: soc: qcom,smsm: convert to dtschema Date: Tue, 5 Apr 2022 08:55:12 +0200 Message-Id: <20220405065512.26521-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the Qualcomm Shared Memory State Machine to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes since v1: 1. Skip "^.*" from pattern. 2. Fix subjectprefix. 3. Add Rob's review. --- .../bindings/soc/qcom/qcom,smsm.txt | 104 ------------- .../bindings/soc/qcom/qcom,smsm.yaml | 138 ++++++++++++++++++ 2 files changed, 138 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.ya= ml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Doc= umentation/devicetree/bindings/soc/qcom/qcom,smsm.txt deleted file mode 100644 index 2993b5a97dd6..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm Shared Memory State Machine - -The Shared Memory State Machine facilitates broadcasting of single bit sta= te -information between the processors in a Qualcomm SoC. Each processor is -assigned 32 bits of state that can be modified. A processor can through a -matrix of bitmaps signal subscription of notifications upon changes to a -certain bit owned by a certain remote processor. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,smsm" - -- qcom,ipc-N: - Usage: required - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the N:th remote processor - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,local-host: - Usage: optional - Value type: - Definition: identifier of the local processor in the list of hosts, or - in other words specifier of the column in the subscription - matrix representing the local processor - defaults to host 0 - -- #address-cells: - Usage: required - Value type: - Definition: must be 1 - -- #size-cells: - Usage: required - Value type: - Definition: must be 0 - -=3D SUBNODES -Each processor's state bits are described by a subnode of the smsm device = node. -Nodes can either be flagged as an interrupt-controller to denote a remote -processor's state bits or the local processors bits. The node names are n= ot -important. - -- reg: - Usage: required - Value type: - Definition: specifies the offset, in words, of the first bit for this - entry - -- #qcom,smem-state-cells: - Usage: required for local entry - Value type: - Definition: must be 1 - denotes bit number - -- interrupt-controller: - Usage: required for remote entries - Value type: - Definition: marks the entry as a interrupt-controller and the state bits - to belong to a remote processor - -- #interrupt-cells: - Usage: required for remote entries - Value type: - Definition: must be 2 - denotes bit number and IRQ flags - -- interrupts: - Usage: required for remote entries - Value type: - Definition: one entry specifying remote IRQ used by the remote processor - to signal changes of its state bits - - -=3D EXAMPLE -The following example shows the SMEM setup for controlling properties of t= he -wireless processor, defined from the 8974 apps processor's point-of-view. = It -encompasses one outbound entry and the outgoing interrupt for the wireless -processor. - -smsm { - compatible =3D "qcom,smsm"; - - #address-cells =3D <1>; - #size-cells =3D <0>; - - qcom,ipc-3 =3D <&apcs 8 19>; - - apps_smsm: apps@0 { - reg =3D <0>; - - #qcom,smem-state-cells =3D <1>; - }; - - wcnss_smsm: wcnss@7 { - reg =3D <7>; - interrupts =3D <0 144 1>; - - interrupt-controller; - #interrupt-cells =3D <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Do= cumentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml new file mode 100644 index 000000000000..db67cf043256 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shared Memory State Machine + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The Shared Memory State Machine facilitates broadcasting of single bit s= tate + information between the processors in a Qualcomm SoC. Each processor is + assigned 32 bits of state that can be modified. A processor can through a + matrix of bitmaps signal subscription of notifications upon changes to a + certain bit owned by a certain remote processor. + +properties: + compatible: + const: qcom,smsm + + '#address-cells': + const: 1 + + qcom,local-host: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: + Identifier of the local processor in the list of hosts, or in other = words + specifier of the column in the subscription matrix representing the = local + processor. + + '#size-cells': + const: 0 + +patternProperties: + "^qcom,ipc-[1-4]$": + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS re= gisters + - description: u32 representing offset to the register within th= e syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the= N:th + remote processor. + + "@[0-9a-f]$": + type: object + description: + Each processor's state bits are described by a subnode of the SMSM d= evice + node. Nodes can either be flagged as an interrupt-controller to den= ote a + remote processor's state bits or the local processors bits. The node + names are not important. + + properties: + reg: + maxItems: 1 + + interrupt-controller: + description: + Marks the entry as a interrupt-controller and the state bits to + belong to a remote processor. + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + description: + One entry specifying remote IRQ used by the remote processor to + signal changes of its state bits. + + '#qcom,smem-state-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + description: + Required for local entry. Denotes bit number. + + required: + - reg + + oneOf: + - required: + - '#qcom,smem-state-cells' + - required: + - interrupt-controller + - '#interrupt-cells' + - interrupts + + additionalProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + +anyOf: + - required: + - qcom,ipc-1 + - required: + - qcom,ipc-2 + - required: + - qcom,ipc-3 + - required: + - qcom,ipc-4 + +additionalProperties: false + +examples: + # The following example shows the SMEM setup for controlling properties = of + # the wireless processor, defined from the 8974 apps processor's + # point-of-view. It encompasses one outbound entry and the outgoing inte= rrupt + # for the wireless processor. + - | + #include + + shared-memory { + compatible =3D "qcom,smsm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + qcom,ipc-3 =3D <&apcs 8 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smsm: wcnss@7 { + reg =3D <7>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; --=20 2.32.0